X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fgpu.cpp;h=e5855fea7eda560f68fcdc186f74b781febaf36d;hb=685bb45b7766e8a12cd0de8ee486b9a61183c425;hp=2ea973d864a0a30ef24175a355352740dc765634;hpb=f30bf746981a99079e766b0d4e9de5391a4175ff;p=virtualjaguar diff --git a/src/gpu.cpp b/src/gpu.cpp index 2ea973d..e5855fe 100644 --- a/src/gpu.cpp +++ b/src/gpu.cpp @@ -32,7 +32,7 @@ #include "jagdasm.h" #include "jaguar.h" #include "log.h" -#include "m68k.h" +#include "m68000/m68kinterface.h" //#include "memory.h" #include "tom.h" @@ -323,8 +323,8 @@ static uint32 gpu_div_control; // a bit before writing a result. I.e., if the result of an operation leaves a zero in // the carry flag, you don't have to zero gpu_flag_c before you can write that zero! static uint8 gpu_flag_z, gpu_flag_n, gpu_flag_c; -static uint32 gpu_reg_bank_0[32]; -static uint32 gpu_reg_bank_1[32]; +uint32 gpu_reg_bank_0[32]; +uint32 gpu_reg_bank_1[32]; static uint32 * gpu_reg; static uint32 * gpu_alternate_reg; @@ -501,7 +501,11 @@ uint16 GPUReadWord(uint32 offset, uint32 who/*=UNKNOWN*/) uint32 GPUReadLong(uint32 offset, uint32 who/*=UNKNOWN*/) { if (offset >= 0xF02000 && offset <= 0xF020FF) - WriteLog("GPU: ReadLong--Attempt to read from GPU register file by %s!\n", whoName[who]); + { + WriteLog("GPU: ReadLong--Attempt to read from GPU register file (%X) by %s!\n", offset, whoName[who]); + uint32 reg = (offset & 0xFC) >> 2; + return (reg < 32 ? gpu_reg_bank_0[reg] : gpu_reg_bank_1[reg - 32]); + } // if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE + 0x1000)) if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFC)) @@ -647,12 +651,15 @@ void GPUWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) { //WriteLog("[GPU W16:%08X,%04X]", offset, data); uint32 old_data = GPUReadLong(offset & 0xFFFFFFC, who); + if (offset & 0x02) old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF); else old_data = (old_data & 0x0000FFFF) | ((data & 0xFFFF) << 16); + GPUWriteLong(offset & 0xFFFFFFC, old_data, who); } + return; } else if ((offset == GPU_WORK_RAM_BASE + 0x0FFF) || (GPU_CONTROL_RAM_BASE + 0x1F)) @@ -700,7 +707,9 @@ void GPUWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) case 0x00: { bool IMASKCleared = (gpu_flags & IMASK) && !(data & IMASK); - gpu_flags = data; + // NOTE: According to the JTRM, writing a 1 to IMASK has no effect; only the + // IRQ logic can set it. So we mask it out here to prevent problems... + gpu_flags = data & (~IMASK); gpu_flag_z = gpu_flags & ZERO_FLAG; gpu_flag_c = (gpu_flags & CARRY_FLAG) >> 1; gpu_flag_n = (gpu_flags & NEGA_FLAG) >> 2; @@ -771,6 +780,7 @@ WriteLog("GPU: %s setting GPU PC to %08X %s\n", whoName[who], gpu_pc, (GPU_RUNNI { //WriteLog("asked to perform a single step (single step is %senabled)\n",(data&0x8)?"":"not "); } + gpu_control = (gpu_control & 0xF7C0) | (data & (~0xF7C0)); // if gpu wasn't running but is now running, execute a few cycles @@ -1981,6 +1991,17 @@ static void gpu_opcode_loadw(void) // Also, Power Drive Rally seems to contradict the idea that only LOADs in // the $F03000-$F03FFF range are aligned... #warning "!!! Alignment issues, need to find definitive final word on this !!!" +/* +Preliminary testing on real hardware seems to confirm that something strange goes on +with unaligned reads in main memory. When the address is off by 1, the result is the +same as the long address with the top byte replaced by something. So if the read is +from $401, and $400 has 12 34 56 78, the value read will be $nn345678, where nn is a currently unknown vlaue. +When the address is off by 2, the result would be $nnnn5678, where nnnn is unknown. +When the address is off by 3, the result would be $nnnnnn78, where nnnnnn is unknown. +It may be that the "unknown" values come from the prefetch queue, but not sure how +to test that. They seem to be stable, though, which would indicate such a mechanism. +Sometimes, however, the off by 2 case returns $12345678! +*/ static void gpu_opcode_load(void) { #ifdef GPU_DIS_LOAD @@ -1988,10 +2009,16 @@ static void gpu_opcode_load(void) WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT + uint32 mask[4] = { 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00 }; // if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) RN = GPUReadLong(RM & 0xFFFFFFFC, GPU); +// RN = GPUReadLong(RM & 0x00FFFFFC, GPU); // else // RN = GPUReadLong(RM, GPU); + // Simulate garbage in unaligned reads... +//seems that this behavior is different in GPU mem vs. main mem... +// if ((RM < 0xF03000) || (RM > 0xF0BFFF)) +// RN |= mask[RM & 0x03]; #else RN = GPUReadLong(RM, GPU); #endif