X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fgpu.cpp;h=c57b948d5088751dd169e4d20f0d5e89a7a11a3c;hb=5c28b6dbf7aa20441c8a51f484f4f64b1966f7e3;hp=c2cc94daf17ed0a7cc020be4954be331412d7781;hpb=b73c60485dcb9ccb1ed2fd47437346fa6d3ef54b;p=virtualjaguar diff --git a/src/gpu.cpp b/src/gpu.cpp index c2cc94d..c57b948 100644 --- a/src/gpu.cpp +++ b/src/gpu.cpp @@ -5,10 +5,10 @@ // // Originally by David Raingeard (Cal2) // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) -// Cleanups, endian wrongness, and bad ASM amelioration by James L. Hammons +// Cleanups, endian wrongness, and bad ASM amelioration by James Hammons // (C) 2010 Underground Software // -// JLH = James L. Hammons +// JLH = James Hammons // // Who When What // --- ---------- ------------------------------------------------------------- @@ -32,19 +32,18 @@ #include "jagdasm.h" #include "jaguar.h" #include "log.h" -#include "m68k.h" +#include "m68000/m68kinterface.h" //#include "memory.h" #include "tom.h" // Seems alignment in loads & stores was off... #define GPU_CORRECT_ALIGNMENT -//#define GPU_CORRECT_ALIGNMENT_STORE //#define GPU_DEBUG // For GPU dissasembly... -#if 1 +#if 0 #define GPU_DIS_ABS #define GPU_DIS_ADD #define GPU_DIS_ADDC @@ -648,12 +647,15 @@ void GPUWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) { //WriteLog("[GPU W16:%08X,%04X]", offset, data); uint32 old_data = GPUReadLong(offset & 0xFFFFFFC, who); + if (offset & 0x02) old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF); else old_data = (old_data & 0x0000FFFF) | ((data & 0xFFFF) << 16); + GPUWriteLong(offset & 0xFFFFFFC, old_data, who); } + return; } else if ((offset == GPU_WORK_RAM_BASE + 0x0FFF) || (GPU_CONTROL_RAM_BASE + 0x1F)) @@ -701,7 +703,9 @@ void GPUWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) case 0x00: { bool IMASKCleared = (gpu_flags & IMASK) && !(data & IMASK); - gpu_flags = data; + // NOTE: According to the JTRM, writing a 1 to IMASK has no effect; only the + // IRQ logic can set it. So we mask it out here to prevent problems... + gpu_flags = data & (~IMASK); gpu_flag_z = gpu_flags & ZERO_FLAG; gpu_flag_c = (gpu_flags & CARRY_FLAG) >> 1; gpu_flag_n = (gpu_flags & NEGA_FLAG) >> 2; @@ -1732,8 +1736,13 @@ static void gpu_opcode_store_r14_indexed(void) if (doGPUDis) WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2)); #endif -#ifdef GPU_CORRECT_ALIGNMENT_STORE - GPUWriteLong((gpu_reg[14] & 0xFFFFFFFC) + (gpu_convert_zero[IMM_1] << 2), RN, GPU); +#ifdef GPU_CORRECT_ALIGNMENT + uint32 address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); #else GPUWriteLong(gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2), RN, GPU); #endif @@ -1745,8 +1754,13 @@ static void gpu_opcode_store_r15_indexed(void) if (doGPUDis) WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2)); #endif -#ifdef GPU_CORRECT_ALIGNMENT_STORE - GPUWriteLong((gpu_reg[15] & 0xFFFFFFFC) + (gpu_convert_zero[IMM_1] << 2), RN, GPU); +#ifdef GPU_CORRECT_ALIGNMENT + uint32 address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); #else GPUWriteLong(gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2), RN, GPU); #endif @@ -1759,7 +1773,12 @@ static void gpu_opcode_load_r14_ri(void) WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[14], IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - RN = GPUReadLong((gpu_reg[14] + RM) & 0xFFFFFFFC, GPU); + uint32 address = gpu_reg[14] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); #else RN = GPUReadLong(gpu_reg[14] + RM, GPU); #endif @@ -1776,7 +1795,12 @@ static void gpu_opcode_load_r15_ri(void) WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[15], IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - RN = GPUReadLong((gpu_reg[15] + RM) & 0xFFFFFFFC, GPU); + uint32 address = gpu_reg[15] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); #else RN = GPUReadLong(gpu_reg[15] + RM, GPU); #endif @@ -1792,8 +1816,13 @@ static void gpu_opcode_store_r14_ri(void) if (doGPUDis) WriteLog("%06X: STORE R%02u, (R14+R%02u) [NCZ:%u%u%u, R%02u=%08X, R14+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[14]); #endif -#ifdef GPU_CORRECT_ALIGNMENT_STORE - GPUWriteLong((gpu_reg[14] + RM) & 0xFFFFFFFC, RN, GPU); +#ifdef GPU_CORRECT_ALIGNMENT + uint32 address = gpu_reg[14] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); #else GPUWriteLong(gpu_reg[14] + RM, RN, GPU); #endif @@ -1806,7 +1835,12 @@ static void gpu_opcode_store_r15_ri(void) WriteLog("%06X: STORE R%02u, (R15+R%02u) [NCZ:%u%u%u, R%02u=%08X, R15+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[15]); #endif #ifdef GPU_CORRECT_ALIGNMENT_STORE - GPUWriteLong((gpu_reg[15] + RM) & 0xFFFFFFFC, RN, GPU); + uint32 address = gpu_reg[15] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); #else GPUWriteLong(gpu_reg[15] + RM, RN, GPU); #endif @@ -1859,11 +1893,11 @@ static void gpu_opcode_storew(void) if (doGPUDis) WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM); #endif -#ifdef GPU_CORRECT_ALIGNMENT_STORE +#ifdef GPU_CORRECT_ALIGNMENT if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) GPUWriteLong(RM & 0xFFFFFFFE, RN & 0xFFFF, GPU); else - JaguarWriteWord(RM & 0xFFFFFFFE, RN, GPU); + JaguarWriteWord(RM, RN, GPU); #else if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) GPUWriteLong(RM, RN & 0xFFFF, GPU); @@ -1878,8 +1912,11 @@ static void gpu_opcode_store(void) if (doGPUDis) WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM); #endif -#ifdef GPU_CORRECT_ALIGNMENT_STORE - GPUWriteLong(RM & 0xFFFFFFFC, RN, GPU); +#ifdef GPU_CORRECT_ALIGNMENT + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + GPUWriteLong(RM & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(RM, RN, GPU); #else GPUWriteLong(RM, RN, GPU); #endif @@ -1887,9 +1924,17 @@ static void gpu_opcode_store(void) static void gpu_opcode_storep(void) { -#ifdef GPU_CORRECT_ALIGNMENT_STORE - GPUWriteLong((RM & 0xFFFFFFF8) + 0, gpu_hidata, GPU); - GPUWriteLong((RM & 0xFFFFFFF8) + 4, RN, GPU); +#ifdef GPU_CORRECT_ALIGNMENT + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + { + GPUWriteLong((RM & 0xFFFFFFF8) + 0, gpu_hidata, GPU); + GPUWriteLong((RM & 0xFFFFFFF8) + 4, RN, GPU); + } + else + { + GPUWriteLong(RM + 0, gpu_hidata, GPU); + GPUWriteLong(RM + 4, RN, GPU); + } #else GPUWriteLong(RM + 0, gpu_hidata, GPU); GPUWriteLong(RM + 4, RN, GPU); @@ -1922,7 +1967,7 @@ static void gpu_opcode_loadw(void) if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) RN = GPUReadLong(RM & 0xFFFFFFFE, GPU) & 0xFFFF; else - RN = JaguarReadWord(RM & 0xFFFFFFFE, GPU); + RN = JaguarReadWord(RM, GPU); #else if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) RN = GPUReadLong(RM, GPU) & 0xFFFF; @@ -1938,6 +1983,20 @@ static void gpu_opcode_loadw(void) // According to the docs, & "Do The Same", this address is long aligned... // So let's try it: // And it works!!! Need to fix all instances... +// Also, Power Drive Rally seems to contradict the idea that only LOADs in +// the $F03000-$F03FFF range are aligned... +#warning "!!! Alignment issues, need to find definitive final word on this !!!" +/* +Preliminary testing on real hardware seems to confirm that something strange goes on +with unaligned reads in main memory. When the address is off by 1, the result is the +same as the long address with the top byte replaced by something. So if the read is +from $401, and $400 has 12 34 56 78, the value read will be $nn345678, where nn is a currently unknown vlaue. +When the address is off by 2, the result would be $nnnn5678, where nnnn is unknown. +When the address is off by 3, the result would be $nnnnnn78, where nnnnnn is unknown. +It may be that the "unknown" values come from the prefetch queue, but not sure how +to test that. They seem to be stable, though, which would indicate such a mechanism. +Sometimes, however, the off by 2 case returns $12345678! +*/ static void gpu_opcode_load(void) { #ifdef GPU_DIS_LOAD @@ -1945,7 +2004,16 @@ static void gpu_opcode_load(void) WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - RN = GPUReadLong(RM & 0xFFFFFFFC, GPU); + uint32 mask[4] = { 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00 }; +// if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(RM & 0xFFFFFFFC, GPU); +// RN = GPUReadLong(RM & 0x00FFFFFC, GPU); +// else +// RN = GPUReadLong(RM, GPU); + // Simulate garbage in unaligned reads... +//seems that this behavior is different in GPU mem vs. main mem... +// if ((RM < 0xF03000) || (RM > 0xF0BFFF)) +// RN |= mask[RM & 0x03]; #else RN = GPUReadLong(RM, GPU); #endif @@ -1958,8 +2026,16 @@ static void gpu_opcode_load(void) static void gpu_opcode_loadp(void) { #ifdef GPU_CORRECT_ALIGNMENT - gpu_hidata = GPUReadLong((RM & 0xFFFFFFF8) + 0, GPU); - RN = GPUReadLong((RM & 0xFFFFFFF8) + 4, GPU); + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + { + gpu_hidata = GPUReadLong((RM & 0xFFFFFFF8) + 0, GPU); + RN = GPUReadLong((RM & 0xFFFFFFF8) + 4, GPU); + } + else + { + gpu_hidata = GPUReadLong(RM + 0, GPU); + RN = GPUReadLong(RM + 4, GPU); + } #else gpu_hidata = GPUReadLong(RM + 0, GPU); RN = GPUReadLong(RM + 4, GPU); @@ -1973,7 +2049,12 @@ static void gpu_opcode_load_r14_indexed(void) WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - RN = GPUReadLong((gpu_reg[14] & 0xFFFFFFFC) + (gpu_convert_zero[IMM_1] << 2), GPU); + uint32 address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); + + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); #else RN = GPUReadLong(gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2), GPU); #endif @@ -1990,7 +2071,12 @@ static void gpu_opcode_load_r15_indexed(void) WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - RN = GPUReadLong((gpu_reg[15] & 0xFFFFFFFC) + (gpu_convert_zero[IMM_1] << 2), GPU); + uint32 address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); + + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); #else RN = GPUReadLong(gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2), GPU); #endif