X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fgpu.cpp;h=b83051cab3ddf478d4446de6cfe0f5e6bd88d107;hb=10d7ab1fb217c01030a0b637f9a571c1faf61ede;hp=e5855fea7eda560f68fcdc186f74b781febaf36d;hpb=376c605508b0c1903dee5357a6d95499c940d258;p=virtualjaguar diff --git a/src/gpu.cpp b/src/gpu.cpp index e5855fe..b83051c 100644 --- a/src/gpu.cpp +++ b/src/gpu.cpp @@ -250,7 +250,7 @@ static void gpu_opcode_sat24(void); static void gpu_opcode_pack(void); // This is wrong, since it doesn't take pipeline effects into account. !!! FIX !!! -/*uint8 gpu_opcode_cycles[64] = +/*uint8_t gpu_opcode_cycles[64] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, @@ -265,7 +265,7 @@ static void gpu_opcode_pack(void); //This is wrong, wrong, WRONG, but it seems to work for the time being... //(That is, it fixes Flip Out which relies on GPU timing rather than semaphores. Bad developers! Bad!) //What's needed here is a way to take pipeline effects into account (including pipeline stalls!)... -/*uint8 gpu_opcode_cycles[64] = +/*uint8_t gpu_opcode_cycles[64] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -276,7 +276,7 @@ static void gpu_opcode_pack(void); 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 3, 3, 1, 1, 1, 1 };//*/ -uint8 gpu_opcode_cycles[64] = +uint8_t gpu_opcode_cycles[64] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -308,29 +308,29 @@ void (*gpu_opcode[64])()= gpu_opcode_store_r14_ri, gpu_opcode_store_r15_ri, gpu_opcode_sat24, gpu_opcode_pack, }; -static uint8 gpu_ram_8[0x1000]; -uint32 gpu_pc; -static uint32 gpu_acc; -static uint32 gpu_remain; -static uint32 gpu_hidata; -static uint32 gpu_flags; -static uint32 gpu_matrix_control; -static uint32 gpu_pointer_to_matrix; -static uint32 gpu_data_organization; -static uint32 gpu_control; -static uint32 gpu_div_control; +static uint8_t gpu_ram_8[0x1000]; +uint32_t gpu_pc; +static uint32_t gpu_acc; +static uint32_t gpu_remain; +static uint32_t gpu_hidata; +static uint32_t gpu_flags; +static uint32_t gpu_matrix_control; +static uint32_t gpu_pointer_to_matrix; +static uint32_t gpu_data_organization; +static uint32_t gpu_control; +static uint32_t gpu_div_control; // There is a distinct advantage to having these separated out--there's no need to clear // a bit before writing a result. I.e., if the result of an operation leaves a zero in // the carry flag, you don't have to zero gpu_flag_c before you can write that zero! -static uint8 gpu_flag_z, gpu_flag_n, gpu_flag_c; -uint32 gpu_reg_bank_0[32]; -uint32 gpu_reg_bank_1[32]; -static uint32 * gpu_reg; -static uint32 * gpu_alternate_reg; +static uint8_t gpu_flag_z, gpu_flag_n, gpu_flag_c; +uint32_t gpu_reg_bank_0[32]; +uint32_t gpu_reg_bank_1[32]; +static uint32_t * gpu_reg; +static uint32_t * gpu_alternate_reg; -static uint32 gpu_instruction; -static uint32 gpu_opcode_first_parameter; -static uint32 gpu_opcode_second_parameter; +static uint32_t gpu_instruction; +static uint32_t gpu_opcode_first_parameter; +static uint32_t gpu_opcode_second_parameter; #define GPU_RUNNING (gpu_control & 0x01) @@ -342,7 +342,7 @@ static uint32 gpu_opcode_second_parameter; #define IMM_2 gpu_opcode_second_parameter #define SET_FLAG_Z(r) (gpu_flag_z = ((r) == 0)); -#define SET_FLAG_N(r) (gpu_flag_n = (((uint32)(r) >> 31) & 0x01)); +#define SET_FLAG_N(r) (gpu_flag_n = (((uint32_t)(r) >> 31) & 0x01)); #define RESET_FLAG_Z() gpu_flag_z = 0; #define RESET_FLAG_N() gpu_flag_n = 0; @@ -352,20 +352,20 @@ static uint32 gpu_opcode_second_parameter; #define CLR_ZN (gpu_flag_z = gpu_flag_n = 0) #define CLR_ZNC (gpu_flag_z = gpu_flag_n = gpu_flag_c = 0) #define SET_Z(r) (gpu_flag_z = ((r) == 0)) -#define SET_N(r) (gpu_flag_n = (((uint32)(r) >> 31) & 0x01)) -#define SET_C_ADD(a,b) (gpu_flag_c = ((uint32)(b) > (uint32)(~(a)))) -#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32)(b) > (uint32)(a))) +#define SET_N(r) (gpu_flag_n = (((uint32_t)(r) >> 31) & 0x01)) +#define SET_C_ADD(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(~(a)))) +#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(a))) #define SET_ZN(r) SET_N(r); SET_Z(r) #define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) #define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b) -uint32 gpu_convert_zero[32] = +uint32_t gpu_convert_zero[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; -uint8 * branch_condition_table = 0; +uint8_t * branch_condition_table = 0; #define BRANCH_CONDITION(x) branch_condition_table[(x) + ((jaguar_flags & 7) << 5)] -uint32 gpu_opcode_use[64]; +uint32_t gpu_opcode_use[64]; const char * gpu_opcode_str[64]= { @@ -387,15 +387,15 @@ const char * gpu_opcode_str[64]= "store_r14_ri", "store_r15_ri", "sat24", "pack", }; -static uint32 gpu_in_exec = 0; -static uint32 gpu_releaseTimeSlice_flag = 0; +static uint32_t gpu_in_exec = 0; +static uint32_t gpu_releaseTimeSlice_flag = 0; void GPUReleaseTimeslice(void) { gpu_releaseTimeSlice_flag = 1; } -uint32 GPUGetPC(void) +uint32_t GPUGetPC(void) { return gpu_pc; } @@ -404,7 +404,7 @@ void build_branch_condition_table(void) { if (!branch_condition_table) { - branch_condition_table = (uint8 *)malloc(32 * 8 * sizeof(branch_condition_table[0])); + branch_condition_table = (uint8_t *)malloc(32 * 8 * sizeof(branch_condition_table[0])); if (branch_condition_table) { @@ -435,7 +435,7 @@ void build_branch_condition_table(void) // // GPU byte access (read) // -uint8 GPUReadByte(uint32 offset, uint32 who/*=UNKNOWN*/) +uint8_t GPUReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF02000 && offset <= 0xF020FF) WriteLog("GPU: ReadByte--Attempt to read from GPU register file by %s!\n", whoName[who]); @@ -444,7 +444,7 @@ uint8 GPUReadByte(uint32 offset, uint32 who/*=UNKNOWN*/) return gpu_ram_8[offset & 0xFFF]; else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) { - uint32 data = GPUReadLong(offset & 0xFFFFFFFC, who); + uint32_t data = GPUReadLong(offset & 0xFFFFFFFC, who); if ((offset & 0x03) == 0) return data >> 24; @@ -462,7 +462,7 @@ uint8 GPUReadByte(uint32 offset, uint32 who/*=UNKNOWN*/) // // GPU word access (read) // -uint16 GPUReadWord(uint32 offset, uint32 who/*=UNKNOWN*/) +uint16_t GPUReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF02000 && offset <= 0xF020FF) WriteLog("GPU: ReadWord--Attempt to read from GPU register file by %s!\n", whoName[who]); @@ -470,7 +470,7 @@ uint16 GPUReadWord(uint32 offset, uint32 who/*=UNKNOWN*/) if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE+0x1000)) { offset &= 0xFFF; - uint16 data = ((uint16)gpu_ram_8[offset] << 8) | (uint16)gpu_ram_8[offset+1]; + uint16_t data = ((uint16_t)gpu_ram_8[offset] << 8) | (uint16_t)gpu_ram_8[offset+1]; return data; } else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) @@ -480,7 +480,7 @@ uint16 GPUReadWord(uint32 offset, uint32 who/*=UNKNOWN*/) if (offset & 0x01) // Catch cases 1 & 3... (unaligned read) return (GPUReadByte(offset, who) << 8) | GPUReadByte(offset+1, who); - uint32 data = GPUReadLong(offset & 0xFFFFFFFC, who); + uint32_t data = GPUReadLong(offset & 0xFFFFFFFC, who); if (offset & 0x02) // Cases 0 & 2... return data & 0xFFFF; @@ -498,12 +498,12 @@ uint16 GPUReadWord(uint32 offset, uint32 who/*=UNKNOWN*/) // // GPU dword access (read) // -uint32 GPUReadLong(uint32 offset, uint32 who/*=UNKNOWN*/) +uint32_t GPUReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF02000 && offset <= 0xF020FF) { WriteLog("GPU: ReadLong--Attempt to read from GPU register file (%X) by %s!\n", offset, whoName[who]); - uint32 reg = (offset & 0xFC) >> 2; + uint32_t reg = (offset & 0xFC) >> 2; return (reg < 32 ? gpu_reg_bank_0[reg] : gpu_reg_bank_1[reg - 32]); } @@ -511,8 +511,8 @@ uint32 GPUReadLong(uint32 offset, uint32 who/*=UNKNOWN*/) if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFC)) { offset &= 0xFFF; - return ((uint32)gpu_ram_8[offset] << 24) | ((uint32)gpu_ram_8[offset+1] << 16) - | ((uint32)gpu_ram_8[offset+2] << 8) | (uint32)gpu_ram_8[offset+3];//*/ + return ((uint32_t)gpu_ram_8[offset] << 24) | ((uint32_t)gpu_ram_8[offset+1] << 16) + | ((uint32_t)gpu_ram_8[offset+2] << 8) | (uint32_t)gpu_ram_8[offset+3];//*/ // return GET32(gpu_ram_8, offset); } // else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) @@ -562,7 +562,7 @@ uint32 GPUReadLong(uint32 offset, uint32 who/*=UNKNOWN*/) // // GPU byte access (write) // -void GPUWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) +void GPUWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF02000 && offset <= 0xF020FF) WriteLog("GPU: WriteByte--Attempt to write to GPU register file by %s!\n", whoName[who]); @@ -581,7 +581,7 @@ void GPUWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) } else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset <= GPU_CONTROL_RAM_BASE + 0x1F)) { - uint32 reg = offset & 0x1C; + uint32_t reg = offset & 0x1C; int bytenum = offset & 0x03; //This is definitely wrong! @@ -589,7 +589,7 @@ void GPUWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) gpu_div_control = (gpu_div_control & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); else { - uint32 old_data = GPUReadLong(offset & 0xFFFFFFC, who); + uint32_t old_data = GPUReadLong(offset & 0xFFFFFFC, who); bytenum = 3 - bytenum; // convention motorola !!! old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); GPUWriteLong(offset & 0xFFFFFFC, old_data, who); @@ -603,7 +603,7 @@ void GPUWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) // // GPU word access (write) // -void GPUWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) +void GPUWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF02000 && offset <= 0xF020FF) WriteLog("GPU: WriteWord--Attempt to write to GPU register file by %s!\n", whoName[who]); @@ -650,7 +650,7 @@ void GPUWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) else { //WriteLog("[GPU W16:%08X,%04X]", offset, data); - uint32 old_data = GPUReadLong(offset & 0xFFFFFFC, who); + uint32_t old_data = GPUReadLong(offset & 0xFFFFFFC, who); if (offset & 0x02) old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF); @@ -678,7 +678,7 @@ void GPUWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) // // GPU dword access (write) // -void GPUWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) +void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF02000 && offset <= 0xF020FF) WriteLog("GPU: WriteLong--Attempt to write to GPU register file by %s!\n", whoName[who]); @@ -745,7 +745,7 @@ WriteLog("GPU: %s setting GPU PC to %08X %s\n", whoName[who], gpu_pc, (GPU_RUNNI break; case 0x14: { -// uint32 gpu_was_running = GPU_RUNNING; +// uint32_t gpu_was_running = GPU_RUNNING; data &= ~0xF7C0; // Disable writes to INT_LAT0-4 & TOM version number // check for GPU -> CPU interrupt @@ -826,13 +826,13 @@ static bool finished = false; if (GPU_RUNNING && effect_start5 && gpu_pc == 0xF035D8) { // Let's do a dump of $6528! -/* uint32 numItems = JaguarReadWord(0x6BD6); +/* uint32_t numItems = JaguarReadWord(0x6BD6); WriteLog("\nDump of $6528: %u items.\n\n", numItems); for(int i=0; i ", 0x6528+i, JaguarReadLong(0x6528+i), JaguarReadLong(0x6528+i+4), JaguarReadLong(0x6528+i+8)); - uint16 link = JaguarReadWord(0x6528+i+8+2); + uint16_t link = JaguarReadWord(0x6528+i+8+2); for(int j=0; j<40; j+=4) WriteLog("%08X ", JaguarReadLong(link + j)); WriteLog("\n"); @@ -842,7 +842,7 @@ if (GPU_RUNNING && effect_start5 && gpu_pc == 0xF035D8) //This isn't working the way it should! !!! FIX !!! //Err, actually, it is. // NOW, it works right! Problem solved!!! It's a blitter bug! -/* uint32 src = 0x4D54, dst = 0xF03000, width = 10 * 4; +/* uint32_t src = 0x4D54, dst = 0xF03000, width = 10 * 4; for(int y=0; y<127; y++) { for(int x=0; x<2; x++) @@ -944,7 +944,7 @@ void GPUHandleIRQs(void) return; // Get the interrupt latch & enable bits - uint32 bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F; + uint32_t bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F; // Bail out if latched interrupts aren't enabled bits &= mask; @@ -952,7 +952,7 @@ void GPUHandleIRQs(void) return; // Determine which interrupt to service - uint32 which = 0; //Isn't there a #pragma to disable this warning??? + uint32_t which = 0; //Isn't there a #pragma to disable this warning??? if (bits & 0x01) which = 0; if (bits & 0x02) @@ -988,7 +988,7 @@ void GPUSetIRQLine(int irqline, int state) if (start_logging) WriteLog("GPU: Setting GPU IRQ line #%i\n", irqline); - uint32 mask = 0x0040 << irqline; + uint32_t mask = 0x0040 << irqline; gpu_control &= ~mask; // Clear the interrupt latch if (state) @@ -1005,8 +1005,8 @@ void GPUSetIRQLine(int irqline, int state) void GPUInit(void) { // memory_malloc_secure((void **)&gpu_ram_8, 0x1000, "GPU work RAM"); -// memory_malloc_secure((void **)&gpu_reg_bank_0, 32 * sizeof(int32), "GPU bank 0 regs"); -// memory_malloc_secure((void **)&gpu_reg_bank_1, 32 * sizeof(int32), "GPU bank 1 regs"); +// memory_malloc_secure((void **)&gpu_reg_bank_0, 32 * sizeof(int32_t), "GPU bank 0 regs"); +// memory_malloc_secure((void **)&gpu_reg_bank_1, 32 * sizeof(int32_t), "GPU bank 1 regs"); build_branch_condition_table(); @@ -1046,14 +1046,14 @@ void GPUReset(void) GPUResetStats(); } -uint32 GPUReadPC(void) +uint32_t GPUReadPC(void) { return gpu_pc; } void GPUResetStats(void) { - for(uint32 i=0; i<64; i++) + for(uint32_t i=0; i<64; i++) gpu_opcode_use[i] = 0; WriteLog("--> GPU stats were reset!\n"); } @@ -1063,10 +1063,10 @@ void GPUDumpDisassembly(void) char buffer[512]; WriteLog("\n---[GPU code at 00F03000]---------------------------\n"); - uint32 j = 0xF03000; + uint32_t j = 0xF03000; while (j <= 0xF03FFF) { - uint32 oldj = j; + uint32_t oldj = j; j += dasmjag(JAGUAR_GPU, buffer, j); WriteLog("\t%08X: %s\n", oldj, buffer); } @@ -1108,7 +1108,7 @@ void GPUDone(void) WriteLog("GPU: Stopped at PC=%08X (GPU %s running)\n", (unsigned int)gpu_pc, GPU_RUNNING ? "was" : "wasn't"); // Get the interrupt latch & enable bits - uint8 bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F; + uint8_t bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F; WriteLog("GPU: Latch bits = %02X, enable bits = %02X\n", bits, mask); GPUDumpRegisters(); @@ -1133,7 +1133,7 @@ void GPUDone(void) static int testCount = 1; static int len = 0; static bool tripwire = false; -void GPUExec(int32 cycles) +void GPUExec(int32_t cycles) { if (!GPU_RUNNING) return; @@ -1156,14 +1156,14 @@ if (gpu_ram_8[0x054] == 0x98 && gpu_ram_8[0x055] == 0x0A && gpu_ram_8[0x056] == { if (gpu_pc == 0xF03000) { - extern uint32 starCount; + extern uint32_t starCount; starCount = 0; /* WriteLog("GPU: Starting starfield generator... Dump of [R03=%08X]:\n", gpu_reg_bank_0[03]); - uint32 base = gpu_reg_bank_0[3]; - for(uint32 i=0; i<0x100; i+=16) + uint32_t base = gpu_reg_bank_0[3]; + for(uint32_t i=0; i<0x100; i+=16) { WriteLog("%02X: ", i); - for(uint32 j=0; j<16; j++) + for(uint32_t j=0; j<16; j++) { WriteLog("%02X ", JaguarReadByte(base + i + j)); } @@ -1189,8 +1189,8 @@ if (gpu_ram_8[0x054] == 0x98 && gpu_ram_8[0x055] == 0x0A && gpu_ram_8[0x056] == gpu_flag_z = (gpu_flag_z ? 1 : 0); gpu_flag_n = (gpu_flag_n ? 1 : 0);*/ - uint16 opcode = GPUReadWord(gpu_pc, GPU); - uint32 index = opcode >> 10; + uint16_t opcode = GPUReadWord(gpu_pc, GPU); + uint32_t index = opcode >> 10; gpu_instruction = opcode; // Added for GPU #3... gpu_opcode_first_parameter = (opcode >> 5) & 0x1F; gpu_opcode_second_parameter = opcode & 0x1F; @@ -1384,7 +1384,7 @@ const char * condition[32] = gpu_flag_z = (gpu_flag_z ? 1 : 0); gpu_flag_n = (gpu_flag_n ? 1 : 0);*/ // KLUDGE: Used by BRANCH_CONDITION - uint32 jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z; + uint32_t jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z; if (BRANCH_CONDITION(IMM_2)) { @@ -1394,10 +1394,10 @@ const char * condition[32] = #endif if (gpu_start_log) WriteLog(" --> JUMP: Branch taken.\n"); - uint32 delayed_pc = RM; + uint32_t delayed_pc = RM; GPUExec(1); gpu_pc = delayed_pc; -/* uint16 opcode = GPUReadWord(gpu_pc, GPU); +/* uint16_t opcode = GPUReadWord(gpu_pc, GPU); gpu_opcode_first_parameter = (opcode >> 5) & 0x1F; gpu_opcode_second_parameter = opcode & 0x1F; @@ -1424,8 +1424,8 @@ const char * condition[32] = #endif /* if (CONDITION(jaguar.op & 31)) { - int32 r1 = (INT8)((jaguar.op >> 2) & 0xF8) >> 2; - uint32 newpc = jaguar.PC + r1; + int32_t r1 = (INT8)((jaguar.op >> 2) & 0xF8) >> 2; + uint32_t newpc = jaguar.PC + r1; CALL_MAME_DEBUG; jaguar.op = ROPCODE(jaguar.PC); jaguar.PC = newpc; @@ -1438,7 +1438,7 @@ const char * condition[32] = gpu_flag_c = (gpu_flag_c ? 1 : 0); gpu_flag_z = (gpu_flag_z ? 1 : 0);*/ // KLUDGE: Used by BRANCH_CONDITION - uint32 jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z; + uint32_t jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z; if (BRANCH_CONDITION(IMM_2)) { @@ -1448,11 +1448,11 @@ const char * condition[32] = #endif if (gpu_start_log) WriteLog(" --> JR: Branch taken.\n"); - int32 offset = (IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1); // Sign extend IMM_1 - int32 delayed_pc = gpu_pc + (offset * 2); + int32_t offset = (IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1); // Sign extend IMM_1 + int32_t delayed_pc = gpu_pc + (offset * 2); GPUExec(1); gpu_pc = delayed_pc; -/* uint16 opcode = GPUReadWord(gpu_pc, GPU); +/* uint16_t opcode = GPUReadWord(gpu_pc, GPU); gpu_opcode_first_parameter = (opcode >> 5) & 0x1F; gpu_opcode_second_parameter = opcode & 0x1F; @@ -1472,7 +1472,7 @@ static void gpu_opcode_add(void) if (doGPUDis) WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - uint32 res = RN + RM; + uint32_t res = RN + RM; CLR_ZNC; SET_ZNC_ADD(RN, RM, res); RN = res; #ifdef GPU_DIS_ADD @@ -1488,14 +1488,14 @@ static void gpu_opcode_addc(void) WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif /* int dreg = jaguar.op & 31; - uint32 r1 = jaguar.r[(jaguar.op >> 5) & 31]; - uint32 r2 = jaguar.r[dreg]; - uint32 res = r2 + r1 + ((jaguar.FLAGS >> 1) & 1); + uint32_t r1 = jaguar.r[(jaguar.op >> 5) & 31]; + uint32_t r2 = jaguar.r[dreg]; + uint32_t res = r2 + r1 + ((jaguar.FLAGS >> 1) & 1); jaguar.r[dreg] = res; CLR_ZNC; SET_ZNC_ADD(r2,r1,res);*/ - uint32 res = RN + RM + gpu_flag_c; - uint32 carry = gpu_flag_c; + uint32_t res = RN + RM + gpu_flag_c; + uint32_t carry = gpu_flag_c; // SET_ZNC_ADD(RN, RM, res); //???BUG??? Yes! SET_ZNC_ADD(RN + carry, RM, res); // SET_ZNC_ADD(RN, RM + carry, res); @@ -1512,8 +1512,8 @@ static void gpu_opcode_addq(void) if (doGPUDis) WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 r1 = gpu_convert_zero[IMM_1]; - uint32 res = RN + r1; + uint32_t r1 = gpu_convert_zero[IMM_1]; + uint32_t res = RN + r1; CLR_ZNC; SET_ZNC_ADD(RN, r1, res); RN = res; #ifdef GPU_DIS_ADDQ @@ -1541,7 +1541,7 @@ static void gpu_opcode_sub(void) if (doGPUDis) WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - uint32 res = RN - RM; + uint32_t res = RN - RM; SET_ZNC_SUB(RN, RM, res); RN = res; #ifdef GPU_DIS_SUB @@ -1556,8 +1556,8 @@ static void gpu_opcode_subc(void) if (doGPUDis) WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - uint32 res = RN - RM - gpu_flag_c; - uint32 borrow = gpu_flag_c; + uint32_t res = RN - RM - gpu_flag_c; + uint32_t borrow = gpu_flag_c; // SET_ZNC_SUB(RN, RM, res); //???BUG??? YES!!! //No matter how you do it, there is a problem. With below, it's 0-0 with carry, //and the one below it it's FFFFFFFF - FFFFFFFF with carry... !!! FIX !!! @@ -1573,7 +1573,7 @@ static void gpu_opcode_subc(void) N = 5, M = 3, 3 - 5 = -2, C = 1... Or, in our case: N = 0, M = 1, 0 - 1 = -1, C = 0! -#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32)(b) > (uint32)(a))) +#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(a))) #define SET_ZN(r) SET_N(r); SET_Z(r) #define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) #define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b) @@ -1584,8 +1584,8 @@ static void gpu_opcode_subq(void) if (doGPUDis) WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 r1 = gpu_convert_zero[IMM_1]; - uint32 res = RN - r1; + uint32_t r1 = gpu_convert_zero[IMM_1]; + uint32_t res = RN - r1; SET_ZNC_SUB(RN, r1, res); RN = res; #ifdef GPU_DIS_SUBQ @@ -1613,7 +1613,7 @@ static void gpu_opcode_cmp(void) if (doGPUDis) WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - uint32 res = RN - RM; + uint32_t res = RN - RM; SET_ZNC_SUB(RN, RM, res); #ifdef GPU_DIS_CMP if (doGPUDis) @@ -1623,14 +1623,14 @@ static void gpu_opcode_cmp(void) static void gpu_opcode_cmpq(void) { - static int32 sqtable[32] = + static int32_t sqtable[32] = { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1 }; #ifdef GPU_DIS_CMPQ if (doGPUDis) WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, sqtable[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; - uint32 res = RN - r1; + uint32_t r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; + uint32_t res = RN - r1; SET_ZNC_SUB(RN, r1, res); #ifdef GPU_DIS_CMPQ if (doGPUDis) @@ -1715,7 +1715,7 @@ static void gpu_opcode_sat8(void) if (doGPUDis) WriteLog("%06X: SAT8 R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - RN = ((int32)RN < 0 ? 0 : (RN > 0xFF ? 0xFF : RN)); + RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFF ? 0xFF : RN)); SET_ZN(RN); #ifdef GPU_DIS_SAT8 if (doGPUDis) @@ -1725,13 +1725,13 @@ static void gpu_opcode_sat8(void) static void gpu_opcode_sat16(void) { - RN = ((int32)RN < 0 ? 0 : (RN > 0xFFFF ? 0xFFFF : RN)); + RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFFFF ? 0xFFFF : RN)); SET_ZN(RN); } static void gpu_opcode_sat24(void) { - RN = ((int32)RN < 0 ? 0 : (RN > 0xFFFFFF ? 0xFFFFFF : RN)); + RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFFFFFF ? 0xFFFFFF : RN)); SET_ZN(RN); } @@ -1742,7 +1742,7 @@ static void gpu_opcode_store_r14_indexed(void) WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2)); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); + uint32_t address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); if (address >= 0xF03000 && address <= 0xF03FFF) GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); @@ -1760,7 +1760,7 @@ static void gpu_opcode_store_r15_indexed(void) WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2)); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); + uint32_t address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); if (address >= 0xF03000 && address <= 0xF03FFF) GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); @@ -1778,7 +1778,7 @@ static void gpu_opcode_load_r14_ri(void) WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[14], IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 address = gpu_reg[14] + RM; + uint32_t address = gpu_reg[14] + RM; if (address >= 0xF03000 && address <= 0xF03FFF) RN = GPUReadLong(address & 0xFFFFFFFC, GPU); @@ -1800,7 +1800,7 @@ static void gpu_opcode_load_r15_ri(void) WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[15], IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 address = gpu_reg[15] + RM; + uint32_t address = gpu_reg[15] + RM; if (address >= 0xF03000 && address <= 0xF03FFF) RN = GPUReadLong(address & 0xFFFFFFFC, GPU); @@ -1822,7 +1822,7 @@ static void gpu_opcode_store_r14_ri(void) WriteLog("%06X: STORE R%02u, (R14+R%02u) [NCZ:%u%u%u, R%02u=%08X, R14+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[14]); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 address = gpu_reg[14] + RM; + uint32_t address = gpu_reg[14] + RM; if (address >= 0xF03000 && address <= 0xF03FFF) GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); @@ -1840,7 +1840,7 @@ static void gpu_opcode_store_r15_ri(void) WriteLog("%06X: STORE R%02u, (R15+R%02u) [NCZ:%u%u%u, R%02u=%08X, R15+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[15]); #endif #ifdef GPU_CORRECT_ALIGNMENT_STORE - uint32 address = gpu_reg[15] + RM; + uint32_t address = gpu_reg[15] + RM; if (address >= 0xF03000 && address <= 0xF03FFF) GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); @@ -1865,7 +1865,7 @@ static void gpu_opcode_pack(void) if (doGPUDis) WriteLog("%06X: %s R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, (!IMM_1 ? "PACK " : "UNPACK"), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 val = RN; + uint32_t val = RN; //BUG! if (RM == 0) // Pack if (IMM_1 == 0) // Pack @@ -2009,7 +2009,7 @@ static void gpu_opcode_load(void) WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 mask[4] = { 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00 }; + uint32_t mask[4] = { 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00 }; // if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) RN = GPUReadLong(RM & 0xFFFFFFFC, GPU); // RN = GPUReadLong(RM & 0x00FFFFFC, GPU); @@ -2054,7 +2054,7 @@ static void gpu_opcode_load_r14_indexed(void) WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); + uint32_t address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) RN = GPUReadLong(address & 0xFFFFFFFC, GPU); @@ -2076,7 +2076,7 @@ static void gpu_opcode_load_r15_indexed(void) WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN); #endif #ifdef GPU_CORRECT_ALIGNMENT - uint32 address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); + uint32_t address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) RN = GPUReadLong(address & 0xFFFFFFFC, GPU); @@ -2095,10 +2095,10 @@ static void gpu_opcode_movei(void) { #ifdef GPU_DIS_MOVEI if (doGPUDis) - WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, (uint32)GPUReadWord(gpu_pc) | ((uint32)GPUReadWord(gpu_pc + 2) << 16), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); + WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, (uint32_t)GPUReadWord(gpu_pc) | ((uint32_t)GPUReadWord(gpu_pc + 2) << 16), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif // This instruction is followed by 32-bit value in LSW / MSW format... - RN = (uint32)GPUReadWord(gpu_pc, GPU) | ((uint32)GPUReadWord(gpu_pc + 2, GPU) << 16); + RN = (uint32_t)GPUReadWord(gpu_pc, GPU) | ((uint32_t)GPUReadWord(gpu_pc + 2, GPU) << 16); gpu_pc += 4; #ifdef GPU_DIS_MOVEI if (doGPUDis) @@ -2169,7 +2169,7 @@ static void gpu_opcode_imult(void) if (doGPUDis) WriteLog("%06X: IMULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - RN = (int16)RN * (int16)RM; + RN = (int16_t)RN * (int16_t)RM; SET_ZN(RN); #ifdef GPU_DIS_IMULT if (doGPUDis) @@ -2183,7 +2183,7 @@ static void gpu_opcode_mult(void) if (doGPUDis) WriteLog("%06X: MULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - RN = (uint16)RM * (uint16)RN; + RN = (uint16_t)RM * (uint16_t)RN; SET_ZN(RN); #ifdef GPU_DIS_MULT if (doGPUDis) @@ -2197,7 +2197,7 @@ static void gpu_opcode_bclr(void) if (doGPUDis) WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 res = RN & ~(1 << IMM_1); + uint32_t res = RN & ~(1 << IMM_1); RN = res; SET_ZN(res); #ifdef GPU_DIS_BCLR @@ -2225,7 +2225,7 @@ static void gpu_opcode_bset(void) if (doGPUDis) WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 res = RN | (1 << IMM_1); + uint32_t res = RN | (1 << IMM_1); RN = res; SET_ZN(res); #ifdef GPU_DIS_BSET @@ -2236,21 +2236,21 @@ static void gpu_opcode_bset(void) static void gpu_opcode_imacn(void) { - uint32 res = (int16)RM * (int16)(RN); + uint32_t res = (int16_t)RM * (int16_t)(RN); gpu_acc += res; } static void gpu_opcode_mtoi(void) { - uint32 _RM = RM; - uint32 res = RN = (((int32)_RM >> 8) & 0xFF800000) | (_RM & 0x007FFFFF); + uint32_t _RM = RM; + uint32_t res = RN = (((int32_t)_RM >> 8) & 0xFF800000) | (_RM & 0x007FFFFF); SET_ZN(res); } static void gpu_opcode_normi(void) { - uint32 _RM = RM; - uint32 res = 0; + uint32_t _RM = RM; + uint32_t res = 0; if (_RM) { @@ -2272,21 +2272,21 @@ static void gpu_opcode_normi(void) static void gpu_opcode_mmult(void) { int count = gpu_matrix_control & 0x0F; // Matrix width - uint32 addr = gpu_pointer_to_matrix; // In the GPU's RAM - int64 accum = 0; - uint32 res; + uint32_t addr = gpu_pointer_to_matrix; // In the GPU's RAM + int64_t accum = 0; + uint32_t res; if (gpu_matrix_control & 0x10) // Column stepping { for(int i=0; i> 1)] >> 16) & 0xFFFF); + a = (int16_t)((gpu_alternate_reg[IMM_1 + (i >> 1)] >> 16) & 0xFFFF); else - a = (int16)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF); + a = (int16_t)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF); - int16 b = ((int16)GPUReadWord(addr + 2, GPU)); + int16_t b = ((int16_t)GPUReadWord(addr + 2, GPU)); accum += a * b; addr += 4 * count; } @@ -2295,18 +2295,18 @@ static void gpu_opcode_mmult(void) { for(int i=0; i> 1)] >> 16) & 0xFFFF); + a = (int16_t)((gpu_alternate_reg[IMM_1 + (i >> 1)] >> 16) & 0xFFFF); else - a = (int16)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF); + a = (int16_t)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF); - int16 b = ((int16)GPUReadWord(addr + 2, GPU)); + int16_t b = ((int16_t)GPUReadWord(addr + 2, GPU)); accum += a * b; addr += 4; } } - RN = res = (int32)accum; + RN = res = (int32_t)accum; // carry flag to do (out of the last add) SET_ZN(res); } @@ -2348,8 +2348,8 @@ static void gpu_opcode_div(void) // RN / RM { if (gpu_div_control & 0x01) // 16.16 division { - RN = ((uint64)RN << 16) / RM; - gpu_remain = ((uint64)RN << 16) % RM; + RN = ((uint64_t)RN << 16) / RM; + gpu_remain = ((uint64_t)RN << 16) % RM; } else { @@ -2363,17 +2363,17 @@ static void gpu_opcode_div(void) // RN / RM else RN = 0xFFFFFFFF; -/* uint32 _RM=RM; - uint32 _RN=RN; +/* uint32_t _RM=RM; + uint32_t _RN=RN; if (_RM) { if (gpu_div_control & 1) { - gpu_remain = (((uint64)_RN) << 16) % _RM; + gpu_remain = (((uint64_t)_RN) << 16) % _RM; if (gpu_remain&0x80000000) gpu_remain-=_RM; - RN = (((uint64)_RN) << 16) / _RM; + RN = (((uint64_t)_RN) << 16) / _RM; } else { @@ -2393,8 +2393,8 @@ static void gpu_opcode_div(void) // RN / RM static void gpu_opcode_imultn(void) { - uint32 res = (int32)((int16)RN * (int16)RM); - gpu_acc = (int32)res; + uint32_t res = (int32_t)((int16_t)RN * (int16_t)RM); + gpu_acc = (int32_t)res; SET_FLAG_Z(res); SET_FLAG_N(res); } @@ -2405,7 +2405,7 @@ static void gpu_opcode_neg(void) if (doGPUDis) WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 res = -RN; + uint32_t res = -RN; SET_ZNC_SUB(0, RN, res); RN = res; #ifdef GPU_DIS_NEG @@ -2422,8 +2422,8 @@ static void gpu_opcode_shlq(void) #endif // Was a bug here... // (Look at Aaron's code: If r1 = 32, then 32 - 32 = 0 which is wrong!) - int32 r1 = 32 - IMM_1; - uint32 res = RN << r1; + int32_t r1 = 32 - IMM_1; + uint32_t res = RN << r1; SET_ZN(res); gpu_flag_c = (RN >> 31) & 1; RN = res; #ifdef GPU_DIS_SHLQ @@ -2438,8 +2438,8 @@ static void gpu_opcode_shrq(void) if (doGPUDis) WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - int32 r1 = gpu_convert_zero[IMM_1]; - uint32 res = RN >> r1; + int32_t r1 = gpu_convert_zero[IMM_1]; + uint32_t res = RN >> r1; SET_ZN(res); gpu_flag_c = RN & 1; RN = res; #ifdef GPU_DIS_SHRQ @@ -2454,8 +2454,8 @@ static void gpu_opcode_ror(void) if (doGPUDis) WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - uint32 r1 = RM & 0x1F; - uint32 res = (RN >> r1) | (RN << (32 - r1)); + uint32_t r1 = RM & 0x1F; + uint32_t res = (RN >> r1) | (RN << (32 - r1)); SET_ZN(res); gpu_flag_c = (RN >> 31) & 1; RN = res; #ifdef GPU_DIS_ROR @@ -2470,9 +2470,9 @@ static void gpu_opcode_rorq(void) if (doGPUDis) WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 r1 = gpu_convert_zero[IMM_1 & 0x1F]; - uint32 r2 = RN; - uint32 res = (r2 >> r1) | (r2 << (32 - r1)); + uint32_t r1 = gpu_convert_zero[IMM_1 & 0x1F]; + uint32_t r2 = RN; + uint32_t res = (r2 >> r1) | (r2 << (32 - r1)); RN = res; SET_ZN(res); gpu_flag_c = (r2 >> 31) & 0x01; #ifdef GPU_DIS_RORQ @@ -2484,9 +2484,9 @@ static void gpu_opcode_rorq(void) static void gpu_opcode_sha(void) { /* int dreg = jaguar.op & 31; - int32 r1 = (int32)jaguar.r[(jaguar.op >> 5) & 31]; - uint32 r2 = jaguar.r[dreg]; - uint32 res; + int32_t r1 = (int32_t)jaguar.r[(jaguar.op >> 5) & 31]; + uint32_t r2 = jaguar.r[dreg]; + uint32_t res; CLR_ZNC; if (r1 < 0) @@ -2496,7 +2496,7 @@ static void gpu_opcode_sha(void) } else { - res = (r1 >= 32) ? ((int32)r2 >> 31) : ((int32)r2 >> r1); + res = (r1 >= 32) ? ((int32_t)r2 >> 31) : ((int32_t)r2 >> r1); jaguar.FLAGS |= (r2 << 1) & 2; } jaguar.r[dreg] = res; @@ -2506,16 +2506,16 @@ static void gpu_opcode_sha(void) if (doGPUDis) WriteLog("%06X: SHA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif - uint32 res; + uint32_t res; - if ((int32)RM < 0) + if ((int32_t)RM < 0) { - res = ((int32)RM <= -32) ? 0 : (RN << -(int32)RM); + res = ((int32_t)RM <= -32) ? 0 : (RN << -(int32_t)RM); gpu_flag_c = RN >> 31; } else { - res = ((int32)RM >= 32) ? ((int32)RN >> 31) : ((int32)RN >> (int32)RM); + res = ((int32_t)RM >= 32) ? ((int32_t)RN >> 31) : ((int32_t)RN >> (int32_t)RM); gpu_flag_c = RN & 0x01; } RN = res; @@ -2525,12 +2525,12 @@ static void gpu_opcode_sha(void) WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); #endif -/* int32 sRM=(int32)RM; - uint32 _RN=RN; +/* int32_t sRM=(int32_t)RM; + uint32_t _RN=RN; if (sRM<0) { - uint32 shift=-sRM; + uint32_t shift=-sRM; if (shift>=32) shift=32; gpu_flag_c=(_RN&0x80000000)>>31; while (shift) @@ -2541,12 +2541,12 @@ static void gpu_opcode_sha(void) } else { - uint32 shift=sRM; + uint32_t shift=sRM; if (shift>=32) shift=32; gpu_flag_c=_RN&0x1; while (shift) { - _RN=((int32)_RN)>>1; + _RN=((int32_t)_RN)>>1; shift--; } } @@ -2561,7 +2561,7 @@ static void gpu_opcode_sharq(void) if (doGPUDis) WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); #endif - uint32 res = (int32)RN >> gpu_convert_zero[IMM_1]; + uint32_t res = (int32_t)RN >> gpu_convert_zero[IMM_1]; SET_ZN(res); gpu_flag_c = RN & 0x01; RN = res; #ifdef GPU_DIS_SHARQ @@ -2579,7 +2579,7 @@ static void gpu_opcode_sh(void) if (RM & 0x80000000) // Shift left { gpu_flag_c = RN >> 31; - RN = ((int32)RM <= -32 ? 0 : RN << -(int32)RM); + RN = ((int32_t)RM <= -32 ? 0 : RN << -(int32_t)RM); } else // Shift right {