X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fdsp.cpp;h=8853f946ad519f4d7862d96c1a152c2bf5a2d6a0;hb=48dd9ba5b6742935eef61cec80964afe093139ad;hp=53a7d0889f9c6fbd76f6b208d1c4b6a591b8b0d4;hpb=5d76d651dfc3aa0a2e810e6b6db2ae8a2e34c53e;p=virtualjaguar diff --git a/src/dsp.cpp b/src/dsp.cpp index 53a7d08..8853f94 100644 --- a/src/dsp.cpp +++ b/src/dsp.cpp @@ -310,7 +310,7 @@ static void dsp_opcode_subqmod(void); static void dsp_opcode_subqt(void); static void dsp_opcode_illegal(void); -uint8_t dsp_opcode_cycles[64] = +/*uint8_t dsp_opcode_cycles[64] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, @@ -325,7 +325,10 @@ uint8_t dsp_opcode_cycles[64] = //This is wrong, wrong, WRONG, but it seems to work for the time being... //(That is, it fixes Flip Out which relies on GPU timing rather than semaphores. Bad developers! Bad!) //What's needed here is a way to take pipeline effects into account (including pipeline stalls!)... -/*uint8_t dsp_opcode_cycles[64] = +// Yup, without cheating like this, the sound in things like Rayman, FACTS, & +// Tripper Getem get starved for time and sounds like crap. So we have to figure +// out how to fix that. :-/ +uint8_t dsp_opcode_cycles[64] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -454,12 +457,14 @@ void dsp_reset_stats(void) dsp_opcode_use[i] = 0; } + void DSPReleaseTimeslice(void) { //This does absolutely nothing!!! !!! FIX !!! dsp_releaseTimeSlice_flag = 1; } + void dsp_build_branch_condition_table(void) { // Fill in the mirror table @@ -499,6 +504,7 @@ void dsp_build_branch_condition_table(void) } } + uint8_t DSPReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF1A000 && offset <= 0xF1A0FF) @@ -519,22 +525,20 @@ uint8_t DSPReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) { uint32_t data = DSPReadLong(offset & 0xFFFFFFFC, who); - if ((offset&0x03)==0) - return(data>>24); - else - if ((offset&0x03)==1) - return((data>>16)&0xff); - else - if ((offset&0x03)==2) - return((data>>8)&0xff); - else - if ((offset&0x03)==3) - return(data&0xff); + if ((offset & 0x03) == 0) + return (data >> 24); + else if ((offset & 0x03) == 1) + return ((data >> 16) & 0xFF); + else if ((offset & 0x03) == 2) + return ((data >> 8) & 0xFF); + else if ((offset & 0x03) == 3) + return (data & 0xFF); } return JaguarReadByte(offset, who); } + uint16_t DSPReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF1A000 && offset <= 0xF1A0FF) @@ -562,6 +566,7 @@ uint16_t DSPReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) return JaguarReadWord(offset, who); } + uint32_t DSPReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF1A000 && offset <= 0xF1A0FF) @@ -606,12 +611,13 @@ uint32_t DSPReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/) return JaguarReadLong(offset, who); } + void DSPWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF1A000 && offset <= 0xF1A0FF) WriteLog("DSP: WriteByte--Attempt to write to DSP register file by %s!\n", whoName[who]); - if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000)) + if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE + 0x2000)) { offset -= DSP_WORK_RAM_BASE; dsp_ram_8[offset] = data; @@ -623,7 +629,7 @@ void DSPWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) }*/ return; } - if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20)) + if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE + 0x20)) { uint32_t reg = offset & 0x1C; int bytenum = offset & 0x03; @@ -642,9 +648,11 @@ void DSPWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) } // WriteLog("dsp: writing %.2x at 0x%.8x\n",data,offset); //Should this *ever* happen??? Shouldn't we be saying "unknown" here??? +// Well, yes, it can. There are 3 MMU users after all: 68K, GPU & DSP...! JaguarWriteByte(offset, data, who); } + void DSPWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) { if (offset >= 0xF1A000 && offset <= 0xF1A0FF) @@ -706,6 +714,7 @@ SET16(ram2, offset, data); JaguarWriteWord(offset, data, who); } + //bool badWrite = false; void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/) { @@ -755,80 +764,6 @@ SET32(ram2, offset, data); DSPUpdateRegisterBanks(); dsp_control &= ~((dsp_flags & CINT04FLAGS) >> 3); dsp_control &= ~((dsp_flags & CINT5FLAG) >> 1); - -// NB: This is just a wild hairy-assed guess as to what the playback frequency is. -// It can be timed to anything really, anything that writes to L/RTXD at a regular -// interval. Most things seem to use either the I2S interrupt or the TIMER 0 -// interrupt, so that's what we check for here. Just know that this approach -// can be easily fooled! -// Note also that if both interrupts are enabled, the I2S freq will win. :-P - -// Further Note: -// The impetus for this "fix" was Cybermorph, which sets the SCLK to 7 which is an -// audio frequency > 48 KHz. However, it stuffs the L/RTXD registers using TIMER0. -// So, while this works, it's a by-product of the lame way in which audio is currently -// handled. Hopefully, once we run the DSP in the host audio IRQ, this problem will -// go away of its own accord. :-P -// Or does it? It seems the I2S interrupt isn't on with Cybermorph, so something -// weird is going on here... -// Maybe it works like this: It acknowledges the 1st interrupt, but never clears it. -// So subsequent interrupts come into the chip, but they're never serviced but the -// I2S subsystem keeps going. -// After some testing on real hardware, it seems that if you enable TIMER0 and EXTERNAL -// IRQs on J_INT ($F10020), you don't have to run an I2S interrupt on the DSP. Also, -// It seems that it's only stable for values of SCLK <= 9. - -// All of the preceeding is moot now; we run the DSP in the host audio IRQ. This means -// that we don't actually need this stuff anymore. :-D -#if 0 - if (data & INT_ENA1) // I2S interrupt - { - int freq = GetCalculatedFrequency(); -//This happens too often to be useful... -// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq); - DACSetNewFrequency(freq); - } - else if (data & INT_ENA2) // TIMER 0 interrupt - { - int freq = JERRYGetPIT1Frequency(); -//This happens too often to be useful... -// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq); - DACSetNewFrequency(freq); - } -#endif - -/* if (IMASKCleared) // If IMASK was cleared, -#ifdef DSP_DEBUG_IRQ - { - WriteLog("DSP: Finished interrupt.\n"); -#endif - DSPHandleIRQs(); // see if any other interrupts need servicing! -#ifdef DSP_DEBUG_IRQ - } -#endif//*/ -#if 0 - if (/*4-8, 16*/data & 0x101F0) - WriteLog("DSP: %s is enabling interrupts %s%s%s%s%s%s\n", whoName[who], - (data & 0x010 ? "CPU " : ""), (data & 0x020 ? "I2S " : ""), - (data & 0x040 ? "TIMER0 " : ""), (data & 0x080 ? "TIMER1 " : ""), - (data & 0x100 ? "EXT0 " : ""), (data & 0x10000 ? "EXT1" : "")); -/*if (data & 0x00020) // CD BIOS DSP code... -{ -//001AC1BA: movea.l #$1AC200, A0 -//001AC1C0: move.l #$1AC68C, D0 - char buffer[512]; - - WriteLog("\n---[DSP code at 00F1B97C]---------------------------\n"); - uint32_t j = 0xF1B97C;//0x1AC200; - while (j <= 0xF1BE08)//0x1AC68C) - { - uint32_t oldj = j; - j += dasmjag(JAGUAR_DSP, buffer, j); -// WriteLog("\t%08X: %s\n", oldj+0xD6F77C, buffer); - WriteLog("\t%08X: %s\n", oldj, buffer); - } -}//*/ -#endif break; } case 0x04: @@ -867,10 +802,9 @@ WriteLog("Write to DSP CTRL by %s: %08X (DSP PC=$%08X)\n", whoName[who], data, d #ifdef DSP_DEBUG WriteLog("DSP: DSP -> CPU interrupt\n"); #endif -// This was WRONG -// Why do we check for a valid handler at 64? Isn't that the Jag programmer's responsibility? (YES) + #warning "!!! DSP IRQs that go to the 68K have to be routed thru TOM !!! FIX !!!" - if (JERRYIRQEnabled(IRQ2_DSP))// && jaguar_interrupt_handler_is_valid(64)) + if (JERRYIRQEnabled(IRQ2_DSP)) { JERRYSetPendingIRQ(IRQ2_DSP); DSPReleaseTimeslice(); @@ -961,6 +895,7 @@ WriteLog("DSP: Modulo data %08X written by %s.\n", data, whoName[who]); JaguarWriteLong(offset, data, who); } + // // Update the DSP register file pointers depending on REGPAGE bit // @@ -981,6 +916,7 @@ void DSPUpdateRegisterBanks(void) #endif } + // // Check for and handle any asserted DSP IRQs // @@ -1126,6 +1062,7 @@ ctrl2[0] = regs2[30] = dsp_pc; FlushDSPPipeline(); } + // // Non-pipelined version... // @@ -1231,6 +1168,7 @@ ctrl1[0] = regs1[30] = dsp_pc; //!!!!!!!! } + // // Set the specified DSP IRQ line to a given state // @@ -1265,11 +1203,13 @@ DSPHandleIRQsNP(); // GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE); } + bool DSPIsRunning(void) { return (DSP_RUNNING ? true : false); } + void DSPInit(void) { // memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM"); @@ -1280,6 +1220,7 @@ void DSPInit(void) DSPReset(); } + void DSPReset(void) { dsp_pc = 0x00F1B000; @@ -1310,6 +1251,7 @@ void DSPReset(void) *((uint32_t *)(&dsp_ram_8[i])) = rand(); } + void DSPDumpDisassembly(void) { char buffer[512]; @@ -1325,6 +1267,7 @@ void DSPDumpDisassembly(void) } } + void DSPDumpRegisters(void) { //Shoud add modulus, etc to dump here... @@ -1352,62 +1295,56 @@ void DSPDumpRegisters(void) } } + void DSPDone(void) { - int i, j; + WriteLog("\n\n---------------------------------------------------------------------\n"); + WriteLog("DSP I/O Registers\n"); + WriteLog("---------------------------------------------------------------------\n"); + WriteLog("F1%04X (D_FLAGS): $%06X\n", 0xA100, (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z); + WriteLog("F1%04X (D_MTXC): $%04X\n", 0xA104, dsp_matrix_control); + WriteLog("F1%04X (D_MTXA): $%04X\n", 0xA108, dsp_pointer_to_matrix); + WriteLog("F1%04X (D_END): $%02X\n", 0xA10C, dsp_data_organization); + WriteLog("F1%04X (D_PC): $%06X\n", 0xA110, dsp_pc); + WriteLog("F1%04X (D_CTRL): $%06X\n", 0xA114, dsp_control); + WriteLog("F1%04X (D_MOD): $%08X\n", 0xA118, dsp_modulo); + WriteLog("F1%04X (D_REMAIN): $%08X\n", 0xA11C, dsp_remain); + WriteLog("F1%04X (D_DIVCTRL): $%02X\n", 0xA11C, dsp_div_control); + WriteLog("F1%04X (D_MACHI): $%02X\n", 0xA120, (dsp_acc >> 32) & 0xFF); + WriteLog("---------------------------------------------------------------------\n\n\n"); + WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp was%s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "" : "n't")); WriteLog("DSP: %sin interrupt handler\n", (dsp_flags & IMASK ? "" : "not ")); - // get the active interrupt bits + // Get the active interrupt bits int bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F); - // get the interrupt mask + // Get the interrupt mask int mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F); WriteLog("DSP: pending=$%X enabled=$%X (%s%s%s%s%s%s)\n", bits, mask, (mask & 0x01 ? "CPU " : ""), (mask & 0x02 ? "I2S " : ""), (mask & 0x04 ? "Timer0 " : ""), (mask & 0x08 ? "Timer1 " : ""), (mask & 0x10 ? "Ext0 " : ""), (mask & 0x20 ? "Ext1" : "")); - WriteLog("\nRegisters bank 0\n"); - - for(int j=0; j<8; j++) - { - WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n", - (j << 2) + 0, dsp_reg_bank_0[(j << 2) + 0], - (j << 2) + 1, dsp_reg_bank_0[(j << 2) + 1], - (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2], - (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]); - } - - WriteLog("\nRegisters bank 1\n"); - - for (j=0; j<8; j++) - { - WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n", - (j << 2) + 0, dsp_reg_bank_1[(j << 2) + 0], - (j << 2) + 1, dsp_reg_bank_1[(j << 2) + 1], - (j << 2) + 2, dsp_reg_bank_1[(j << 2) + 2], - (j << 2) + 3, dsp_reg_bank_1[(j << 2) + 3]); - } - + DSPDumpRegisters(); WriteLog("\n"); static char buffer[512]; - j = DSP_WORK_RAM_BASE; + int j = DSP_WORK_RAM_BASE; while (j <= 0xF1CFFF) { uint32_t oldj = j; j += dasmjag(JAGUAR_DSP, buffer, j); WriteLog("\t%08X: %s\n", oldj, buffer); - }//*/ + } WriteLog("DSP opcodes use:\n"); - for (i=0;i<64;i++) + for(int i=0; i<64; i++) { if (dsp_opcode_use[i]) WriteLog("\t%s %i\n", dsp_opcode_str[i], dsp_opcode_use[i]); - }//*/ + } } @@ -1711,6 +1648,7 @@ if ((dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFE) && !tripwire) dsp_in_exec--; } + // // DSP opcode handlers // @@ -1753,6 +1691,7 @@ const char * condition[32] = #endif } + static void dsp_opcode_jr(void) { #ifdef DSP_DIS_JR @@ -1789,6 +1728,7 @@ const char * condition[32] = #endif } + static void dsp_opcode_add(void) { #ifdef DSP_DIS_ADD @@ -1804,6 +1744,7 @@ static void dsp_opcode_add(void) #endif } + static void dsp_opcode_addc(void) { #ifdef DSP_DIS_ADDC @@ -1822,6 +1763,7 @@ static void dsp_opcode_addc(void) #endif } + static void dsp_opcode_addq(void) { #ifdef DSP_DIS_ADDQ @@ -1838,6 +1780,7 @@ static void dsp_opcode_addq(void) #endif } + static void dsp_opcode_sub(void) { #ifdef DSP_DIS_SUB @@ -1853,22 +1796,26 @@ static void dsp_opcode_sub(void) #endif } + static void dsp_opcode_subc(void) { #ifdef DSP_DIS_SUBC if (doDSPDis) WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif - uint32_t res = RN - RM - dsp_flag_c; - uint32_t borrow = dsp_flag_c; - SET_ZNC_SUB(RN - borrow, RM, res); - RN = res; + // This is how the DSP ALU does it--Two's complement with inverted carry + uint64_t res = (uint64_t)RN + (uint64_t)(RM ^ 0xFFFFFFFF) + (dsp_flag_c ^ 1); + // Carry out of the result is inverted too + dsp_flag_c = ((res >> 32) & 0x01) ^ 1; + RN = (res & 0xFFFFFFFF); + SET_ZN(RN); #ifdef DSP_DIS_SUBC if (doDSPDis) WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif } + static void dsp_opcode_subq(void) { #ifdef DSP_DIS_SUBQ @@ -1885,6 +1832,7 @@ static void dsp_opcode_subq(void) #endif } + static void dsp_opcode_cmp(void) { #ifdef DSP_DIS_CMP @@ -1899,6 +1847,7 @@ static void dsp_opcode_cmp(void) #endif } + static void dsp_opcode_cmpq(void) { static int32_t sqtable[32] = @@ -1916,6 +1865,7 @@ static void dsp_opcode_cmpq(void) #endif } + static void dsp_opcode_and(void) { #ifdef DSP_DIS_AND @@ -1930,6 +1880,7 @@ static void dsp_opcode_and(void) #endif } + static void dsp_opcode_or(void) { #ifdef DSP_DIS_OR @@ -1944,6 +1895,7 @@ static void dsp_opcode_or(void) #endif } + static void dsp_opcode_xor(void) { #ifdef DSP_DIS_XOR @@ -1958,6 +1910,7 @@ static void dsp_opcode_xor(void) #endif } + static void dsp_opcode_not(void) { #ifdef DSP_DIS_NOT @@ -1972,11 +1925,13 @@ static void dsp_opcode_not(void) #endif } + static void dsp_opcode_move_pc(void) { RN = dsp_pc - 2; } + static void dsp_opcode_store_r14_indexed(void) { #ifdef DSP_DIS_STORE14I @@ -1990,6 +1945,7 @@ static void dsp_opcode_store_r14_indexed(void) #endif } + static void dsp_opcode_store_r15_indexed(void) { #ifdef DSP_DIS_STORE15I @@ -2003,6 +1959,7 @@ static void dsp_opcode_store_r15_indexed(void) #endif } + static void dsp_opcode_load_r14_ri(void) { #ifdef DSP_DIS_LOAD14R @@ -2020,6 +1977,7 @@ static void dsp_opcode_load_r14_ri(void) #endif } + static void dsp_opcode_load_r15_ri(void) { #ifdef DSP_DIS_LOAD15R @@ -2037,16 +1995,19 @@ static void dsp_opcode_load_r15_ri(void) #endif } + static void dsp_opcode_store_r14_ri(void) { DSPWriteLong(dsp_reg[14] + RM, RN, DSP); } + static void dsp_opcode_store_r15_ri(void) { DSPWriteLong(dsp_reg[15] + RM, RN, DSP); } + static void dsp_opcode_nop(void) { #ifdef DSP_DIS_NOP @@ -2055,6 +2016,7 @@ static void dsp_opcode_nop(void) #endif } + static void dsp_opcode_storeb(void) { #ifdef DSP_DIS_STOREB @@ -2067,6 +2029,7 @@ static void dsp_opcode_storeb(void) JaguarWriteByte(RM, RN, DSP); } + static void dsp_opcode_storew(void) { #ifdef DSP_DIS_STOREW @@ -2086,6 +2049,7 @@ static void dsp_opcode_storew(void) #endif } + static void dsp_opcode_store(void) { #ifdef DSP_DIS_STORE @@ -2099,6 +2063,7 @@ static void dsp_opcode_store(void) #endif } + static void dsp_opcode_loadb(void) { #ifdef DSP_DIS_LOADB @@ -2115,6 +2080,7 @@ static void dsp_opcode_loadb(void) #endif } + static void dsp_opcode_loadw(void) { #ifdef DSP_DIS_LOADW @@ -2138,6 +2104,7 @@ static void dsp_opcode_loadw(void) #endif } + static void dsp_opcode_load(void) { #ifdef DSP_DIS_LOAD @@ -2155,6 +2122,7 @@ static void dsp_opcode_load(void) #endif } + static void dsp_opcode_load_r14_indexed(void) { #ifdef DSP_DIS_LOAD14I @@ -2172,6 +2140,7 @@ static void dsp_opcode_load_r14_indexed(void) #endif } + static void dsp_opcode_load_r15_indexed(void) { #ifdef DSP_DIS_LOAD15I @@ -2189,6 +2158,7 @@ static void dsp_opcode_load_r15_indexed(void) #endif } + static void dsp_opcode_movei(void) { #ifdef DSP_DIS_MOVEI @@ -2204,6 +2174,7 @@ static void dsp_opcode_movei(void) #endif } + static void dsp_opcode_moveta(void) { #ifdef DSP_DIS_MOVETA @@ -2217,6 +2188,7 @@ static void dsp_opcode_moveta(void) #endif } + static void dsp_opcode_movefa(void) { #ifdef DSP_DIS_MOVEFA @@ -2230,6 +2202,7 @@ static void dsp_opcode_movefa(void) #endif } + static void dsp_opcode_move(void) { #ifdef DSP_DIS_MOVE @@ -2243,6 +2216,7 @@ static void dsp_opcode_move(void) #endif } + static void dsp_opcode_moveq(void) { #ifdef DSP_DIS_MOVEQ @@ -2256,6 +2230,7 @@ static void dsp_opcode_moveq(void) #endif } + static void dsp_opcode_resmac(void) { #ifdef DSP_DIS_RESMAC @@ -2269,6 +2244,7 @@ static void dsp_opcode_resmac(void) #endif } + static void dsp_opcode_imult(void) { #ifdef DSP_DIS_IMULT @@ -2283,6 +2259,7 @@ static void dsp_opcode_imult(void) #endif } + static void dsp_opcode_mult(void) { #ifdef DSP_DIS_MULT @@ -2297,6 +2274,7 @@ static void dsp_opcode_mult(void) #endif } + static void dsp_opcode_bclr(void) { #ifdef DSP_DIS_BCLR @@ -2312,6 +2290,7 @@ static void dsp_opcode_bclr(void) #endif } + static void dsp_opcode_btst(void) { #ifdef DSP_DIS_BTST @@ -2325,6 +2304,7 @@ static void dsp_opcode_btst(void) #endif } + static void dsp_opcode_bset(void) { #ifdef DSP_DIS_BSET @@ -2340,6 +2320,7 @@ static void dsp_opcode_bset(void) #endif } + static void dsp_opcode_subqt(void) { #ifdef DSP_DIS_SUBQT @@ -2353,6 +2334,7 @@ static void dsp_opcode_subqt(void) #endif } + static void dsp_opcode_addqt(void) { #ifdef DSP_DIS_ADDQT @@ -2366,6 +2348,7 @@ static void dsp_opcode_addqt(void) #endif } + static void dsp_opcode_imacn(void) { #ifdef DSP_DIS_IMACN @@ -2381,12 +2364,14 @@ static void dsp_opcode_imacn(void) #endif } + static void dsp_opcode_mtoi(void) { RN = (((int32_t)RM >> 8) & 0xFF800000) | (RM & 0x007FFFFF); SET_ZN(RN); } + static void dsp_opcode_normi(void) { uint32_t _Rm = RM; @@ -2409,6 +2394,7 @@ static void dsp_opcode_normi(void) SET_ZN(RN); } + static void dsp_opcode_mmult(void) { int count = dsp_matrix_control&0x0f; @@ -2450,6 +2436,7 @@ static void dsp_opcode_mmult(void) SET_ZN(RN); } + static void dsp_opcode_abs(void) { #ifdef DSP_DIS_ABS @@ -2473,32 +2460,57 @@ static void dsp_opcode_abs(void) #endif } + static void dsp_opcode_div(void) { - uint32_t _Rm=RM; - uint32_t _Rn=RN; - - if (_Rm) +#if 0 + if (RM) { - if (dsp_div_control & 1) + if (dsp_div_control & 0x01) // 16.16 division { - dsp_remain = (((uint64_t)_Rn) << 16) % _Rm; - if (dsp_remain&0x80000000) - dsp_remain-=_Rm; - RN = (((uint64_t)_Rn) << 16) / _Rm; + dsp_remain = ((uint64_t)RN << 16) % RM; + RN = ((uint64_t)RN << 16) / RM; } else { - dsp_remain = _Rn % _Rm; - if (dsp_remain&0x80000000) - dsp_remain-=_Rm; - RN/=_Rm; + // We calculate the remainder first because we destroy RN after + // this by assigning it to itself. + dsp_remain = RN % RM; + RN = RN / RM; } + } else - RN=0xffffffff; + { + // This is what happens according to SCPCD. NYAN! + RN = 0xFFFFFFFF; + dsp_remain = 0; + } +#else + // Real algorithm, courtesy of SCPCD: NYAN! + uint32_t q = RN; + uint32_t r = 0; + + // If 16.16 division, stuff top 16 bits of RN into remainder and put the + // bottom 16 of RN in top 16 of quotient + if (dsp_div_control & 0x01) + q <<= 16, r = RN >> 16; + + for(int i=0; i<32; i++) + { +// uint32_t sign = (r >> 31) & 0x01; + uint32_t sign = r & 0x80000000; + r = (r << 1) | ((q >> 31) & 0x01); + r += (sign ? RM : -RM); + q = (q << 1) | (((~r) >> 31) & 0x01); + } + + RN = q; + dsp_remain = r; +#endif } + static void dsp_opcode_imultn(void) { #ifdef DSP_DIS_IMULTN @@ -2515,6 +2527,7 @@ static void dsp_opcode_imultn(void) #endif } + static void dsp_opcode_neg(void) { #ifdef DSP_DIS_NEG @@ -2530,6 +2543,7 @@ static void dsp_opcode_neg(void) #endif } + static void dsp_opcode_shlq(void) { #ifdef DSP_DIS_SHLQ @@ -2547,6 +2561,7 @@ static void dsp_opcode_shlq(void) #endif } + static void dsp_opcode_shrq(void) { #ifdef DSP_DIS_SHRQ @@ -2563,6 +2578,7 @@ static void dsp_opcode_shrq(void) #endif } + static void dsp_opcode_ror(void) { #ifdef DSP_DIS_ROR @@ -2579,6 +2595,7 @@ static void dsp_opcode_ror(void) #endif } + static void dsp_opcode_rorq(void) { #ifdef DSP_DIS_RORQ @@ -2596,6 +2613,7 @@ static void dsp_opcode_rorq(void) #endif } + static void dsp_opcode_sha(void) { int32_t sRm=(int32_t)RM; @@ -2627,6 +2645,7 @@ static void dsp_opcode_sha(void) SET_ZN(RN); } + static void dsp_opcode_sharq(void) { #ifdef DSP_DIS_SHARQ @@ -2642,6 +2661,7 @@ static void dsp_opcode_sharq(void) #endif } + static void dsp_opcode_sh(void) { int32_t sRm=(int32_t)RM;