X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fdsp.cpp;h=7a0553f292b6c432a8daaa80b56c51daf88e7ef5;hb=6f25f63a18153bc2adc49c5f9a3862c2760716df;hp=878d4443e148f91971fa6af125d6060b6d7722b2;hpb=f28b39e7d7d5fff9d7790da5bd6585e07b7f555e;p=virtualjaguar

diff --git a/src/dsp.cpp b/src/dsp.cpp
index 878d444..7a0553f 100644
--- a/src/dsp.cpp
+++ b/src/dsp.cpp
@@ -1,21 +1,49 @@
 //
 // DSP core
 //
-// by Cal2
+// Originally by David Raingeard
 // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS)
-// Extensive cleanups/rewrites by James L. Hammons
+// Extensive cleanups/rewrites by James Hammons
+// (C) 2010 Underground Software
+//
+// JLH = James Hammons <jlhamm@acm.org>
+//
+// Who  When        What
+// ---  ----------  -------------------------------------------------------------
+// JLH  01/16/2010  Created this log ;-)
+// JLH  11/26/2011  Added fixes for LOAD/STORE alignment issues
 //
 
-#include <SDL.h>	// Used only for SDL_GetTicks...
 #include "dsp.h"
 
+#include <SDL.h>								// Used only for SDL_GetTicks...
+#include <stdlib.h>
+#include <time.h>
+#include "dac.h"
+#include "gpu.h"
+#include "jagdasm.h"
+#include "jaguar.h"
+#include "jerry.h"
+#include "log.h"
+#include "m68000/m68kinterface.h"
+//#include "memory.h"
+
+
+// Seems alignment in loads & stores was off...
+#define DSP_CORRECT_ALIGNMENT
+//#define DSP_CORRECT_ALIGNMENT_STORE
+
 //#define DSP_DEBUG
 //#define DSP_DEBUG_IRQ
+//#define DSP_DEBUG_PL2
 //#define DSP_DEBUG_STALL
+//#define DSP_DEBUG_CC
+#define NEW_SCOREBOARD
 
 // Disassembly definitions
 
-#define DSP_DIS_ABS									// Pipelined only
+#if 0
+#define DSP_DIS_ABS
 #define DSP_DIS_ADD
 #define DSP_DIS_ADDC
 #define DSP_DIS_ADDQ
@@ -44,6 +72,7 @@
 #define DSP_DIS_MOVEI
 #define DSP_DIS_MOVEQ
 #define DSP_DIS_MOVEFA
+#define DSP_DIS_MOVEPC								// Pipeline only!
 #define DSP_DIS_MOVETA
 #define DSP_DIS_MULT
 #define DSP_DIS_NEG
@@ -69,7 +98,7 @@
 //*/
 bool doDSPDis = false;
 //bool doDSPDis = true;
-
+#endif
 
 /*
 No dis yet:
@@ -154,7 +183,11 @@ struct PipelineStage
 #define TYPE_WORD			1
 #define TYPE_DWORD			2
 #define PIPELINE_STALL		64						// Set to # of opcodes + 1
+#ifndef NEW_SCOREBOARD
 bool scoreboard[32];
+#else
+uint8 scoreboard[32];
+#endif
 uint8 plPtrFetch, plPtrRead, plPtrExec, plPtrWrite;
 PipelineStage pipeline[4];
 bool IMASKCleared = false;
@@ -214,7 +247,7 @@ static void dsp_opcode_abs(void);
 static void dsp_opcode_add(void);
 static void dsp_opcode_addc(void);
 static void dsp_opcode_addq(void);
-static void dsp_opcode_addqmod(void);	
+static void dsp_opcode_addqmod(void);
 static void dsp_opcode_addqt(void);
 static void dsp_opcode_and(void);
 static void dsp_opcode_bclr(void);
@@ -235,7 +268,7 @@ static void dsp_opcode_load_r14_indexed(void);
 static void dsp_opcode_load_r14_ri(void);
 static void dsp_opcode_load_r15_indexed(void);
 static void dsp_opcode_load_r15_ri(void);
-static void dsp_opcode_mirror(void);	
+static void dsp_opcode_mirror(void);
 static void dsp_opcode_mmult(void);
 static void dsp_opcode_move(void);
 static void dsp_opcode_movei(void);
@@ -254,8 +287,8 @@ static void dsp_opcode_resmac(void);
 static void dsp_opcode_ror(void);
 static void dsp_opcode_rorq(void);
 static void dsp_opcode_xor(void);
-static void dsp_opcode_sat16s(void);	
-static void dsp_opcode_sat32s(void);	
+static void dsp_opcode_sat16s(void);
+static void dsp_opcode_sat32s(void);
 static void dsp_opcode_sh(void);
 static void dsp_opcode_sha(void);
 static void dsp_opcode_sharq(void);
@@ -271,31 +304,38 @@ static void dsp_opcode_store_r15_ri(void);
 static void dsp_opcode_sub(void);
 static void dsp_opcode_subc(void);
 static void dsp_opcode_subq(void);
-static void dsp_opcode_subqmod(void);	
+static void dsp_opcode_subqmod(void);
 static void dsp_opcode_subqt(void);
 
 uint8 dsp_opcode_cycles[64] =
 {
-	3,  3,  3,  3,  
-	3,  3,  3,  3,  
-	3,  3,  3,  3,  
-	3,  3,  3,  3,
-	3,  3,  1,  3,  
-	1, 18,  3,  3,  
-	3,  3,  3,  3,  
-	3,  3,  3,  3,
-	3,  3,  2,  2,  
-	2,  2,  3,  4,  
-	5,  4,  5,  6,  
-	6,  1,  1,  1,
-	1,  2,  2,  2,  
-	1,  1,  9,  3,  
-	3,  1,  6,  6,  
-	2,  2,  3,  3
-};
+	3,  3,  3,  3,  3,  3,  3,  3,
+	3,  3,  3,  3,  3,  3,  3,  3,
+	3,  3,  1,  3,  1, 18,  3,  3,
+	3,  3,  3,  3,  3,  3,  3,  3,
+	3,  3,  2,  2,  2,  2,  3,  4,
+	5,  4,  5,  6,  6,  1,  1,  1,
+	1,  2,  2,  2,  1,  1,  9,  3,
+	3,  1,  6,  6,  2,  2,  3,  3
+};//*/
+//Here's a QnD kludge...
+//This is wrong, wrong, WRONG, but it seems to work for the time being...
+//(That is, it fixes Flip Out which relies on GPU timing rather than semaphores. Bad developers! Bad!)
+//What's needed here is a way to take pipeline effects into account (including pipeline stalls!)...
+/*uint8 dsp_opcode_cycles[64] =
+{
+	1,  1,  1,  1,  1,  1,  1,  1,
+	1,  1,  1,  1,  1,  1,  1,  1,
+	1,  1,  1,  1,  1,  9,  1,  1,
+	1,  1,  1,  1,  1,  1,  1,  1,
+	1,  1,  1,  1,  1,  1,  1,  2,
+	2,  2,  2,  3,  3,  1,  1,  1,
+	1,  1,  1,  1,  1,  1,  4,  1,
+	1,  1,  3,  3,  1,  1,  1,  1
+};//*/
 
 void (* dsp_opcode[64])() =
-{	
+{
 	dsp_opcode_add,					dsp_opcode_addc,				dsp_opcode_addq,				dsp_opcode_addqt,
 	dsp_opcode_sub,					dsp_opcode_subc,				dsp_opcode_subq,				dsp_opcode_subqt,
 	dsp_opcode_neg,					dsp_opcode_and,					dsp_opcode_or,					dsp_opcode_xor,
@@ -316,8 +356,8 @@ void (* dsp_opcode[64])() =
 
 uint32 dsp_opcode_use[65];
 
-char * dsp_opcode_str[65]=
-{	
+const char * dsp_opcode_str[65]=
+{
 	"add",				"addc",				"addq",				"addqt",
 	"sub",				"subc",				"subq",				"subqt",
 	"neg",				"and",				"or",				"xor",
@@ -347,9 +387,9 @@ static uint32 dsp_pointer_to_matrix;
 static uint32 dsp_data_organization;
 uint32 dsp_control;
 static uint32 dsp_div_control;
-static uint8 dsp_flag_z, dsp_flag_n, dsp_flag_c;    
-static uint32 * dsp_reg, * dsp_alternate_reg;
-static uint32 * dsp_reg_bank_0, * dsp_reg_bank_1;
+static uint8 dsp_flag_z, dsp_flag_n, dsp_flag_c;
+static uint32 * dsp_reg = NULL, * dsp_alternate_reg = NULL;
+static uint32 dsp_reg_bank_0[32], dsp_reg_bank_1[32];
 
 static uint32 dsp_opcode_first_parameter;
 static uint32 dsp_opcode_second_parameter;
@@ -367,17 +407,20 @@ static uint32 dsp_opcode_second_parameter;
 #define CLR_ZN				(dsp_flag_z = dsp_flag_n = 0)
 #define CLR_ZNC				(dsp_flag_z = dsp_flag_n = dsp_flag_c = 0)
 #define SET_Z(r)			(dsp_flag_z = ((r) == 0))
-#define SET_N(r)			(dsp_flag_n = (((UINT32)(r) >> 31) & 0x01))
-#define SET_C_ADD(a,b)		(dsp_flag_c = ((UINT32)(b) > (UINT32)(~(a))))
-#define SET_C_SUB(a,b)		(dsp_flag_c = ((UINT32)(b) > (UINT32)(a)))
+#define SET_N(r)			(dsp_flag_n = (((uint32)(r) >> 31) & 0x01))
+#define SET_C_ADD(a,b)		(dsp_flag_c = ((uint32)(b) > (uint32)(~(a))))
+#define SET_C_SUB(a,b)		(dsp_flag_c = ((uint32)(b) > (uint32)(a)))
 #define SET_ZN(r)			SET_N(r); SET_Z(r)
 #define SET_ZNC_ADD(a,b,r)	SET_N(r); SET_Z(r); SET_C_ADD(a,b)
 #define SET_ZNC_SUB(a,b,r)	SET_N(r); SET_Z(r); SET_C_SUB(a,b)
 
-uint32 dsp_convert_zero[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 };
-uint8 * dsp_branch_condition_table = NULL;
-static uint16 * mirror_table = NULL;
-static uint8 * dsp_ram_8 = NULL;
+uint32 dsp_convert_zero[32] = {
+	32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+	17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+};
+uint8 dsp_branch_condition_table[32 * 8];
+static uint16 mirror_table[65536];
+static uint8 dsp_ram_8[0x2000];
 
 #define BRANCH_CONDITION(x)		dsp_branch_condition_table[(x) + ((jaguar_flags & 7) << 5)]
 
@@ -386,6 +429,14 @@ static uint32 dsp_releaseTimeSlice_flag = 0;
 
 FILE * dsp_fp;
 
+#ifdef DSP_DEBUG_CC
+// Comparison core vars (used only for core comparison! :-)
+static uint64 count = 0;
+static uint8 ram1[0x2000], ram2[0x2000];
+static uint32 regs1[64], regs2[64];
+static uint32 ctrl1[14], ctrl2[14];
+#endif
+
 // Private function prototypes
 
 void DSPDumpRegisters(void);
@@ -399,7 +450,7 @@ void dsp_reset_stats(void)
 		dsp_opcode_use[i] = 0;
 }
 
-void dsp_releaseTimeslice(void)
+void DSPReleaseTimeslice(void)
 {
 //This does absolutely nothing!!! !!! FIX !!!
 	dsp_releaseTimeSlice_flag = 1;
@@ -407,49 +458,39 @@ void dsp_releaseTimeslice(void)
 
 void dsp_build_branch_condition_table(void)
 {
-	// Allocate the mirror table
-	if (!mirror_table)
-		mirror_table = (uint16 *)malloc(65536 * sizeof(mirror_table[0]));
-
 	// Fill in the mirror table
-	if (mirror_table)
-		for(int i=0; i<65536; i++)
-			mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002) |
-			                  ((i >> 11) & 0x0004) | ((i >> 9)  & 0x0008) |
-			                  ((i >> 7)  & 0x0010) | ((i >> 5)  & 0x0020) |
-			                  ((i >> 3)  & 0x0040) | ((i >> 1)  & 0x0080) |
-			                  ((i << 1)  & 0x0100) | ((i << 3)  & 0x0200) |
-			                  ((i << 5)  & 0x0400) | ((i << 7)  & 0x0800) |
-			                  ((i << 9)  & 0x1000) | ((i << 11) & 0x2000) |
-			                  ((i << 13) & 0x4000) | ((i << 15) & 0x8000);
-
-	if (!dsp_branch_condition_table)
-	{
-		dsp_branch_condition_table = (uint8 *)malloc(32 * 8 * sizeof(dsp_branch_condition_table[0]));
-
-		// Fill in the condition table
-		if (dsp_branch_condition_table)
+	for(int i=0; i<65536; i++)
+	{
+		mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002)
+			| ((i >> 11) & 0x0004) | ((i >> 9)  & 0x0008)
+			| ((i >> 7)  & 0x0010) | ((i >> 5)  & 0x0020)
+			| ((i >> 3)  & 0x0040) | ((i >> 1)  & 0x0080)
+			| ((i << 1)  & 0x0100) | ((i << 3)  & 0x0200)
+			| ((i << 5)  & 0x0400) | ((i << 7)  & 0x0800)
+			| ((i << 9)  & 0x1000) | ((i << 11) & 0x2000)
+			| ((i << 13) & 0x4000) | ((i << 15) & 0x8000);
+	}
+
+	// Fill in the condition table
+	for(int i=0; i<8; i++)
+	{
+		for(int j=0; j<32; j++)
 		{
-			for(int i=0; i<8; i++)
-			{
-				for(int j=0; j<32; j++)
-				{
-					int result = 1;
-					if (j & 1)
-						if (i & ZERO_FLAG)
-							result = 0;
-					if (j & 2)
-						if (!(i & ZERO_FLAG))
-							result = 0;
-					if (j & 4)
-						if (i & (CARRY_FLAG << (j >> 4)))
-							result = 0;
-					if (j & 8)
-						if (!(i & (CARRY_FLAG << (j >> 4))))
-							result = 0;
-					dsp_branch_condition_table[i * 32 + j] = result;
-				}
-			}
+			int result = 1;
+
+			if ((j & 1) && (i & ZERO_FLAG))
+				result = 0;
+
+			if ((j & 2) && (!(i & ZERO_FLAG)))
+				result = 0;
+
+			if ((j & 4) && (i & (CARRY_FLAG << (j >> 4))))
+				result = 0;
+
+			if ((j & 8) && (!(i & (CARRY_FLAG << (j >> 4)))))
+				result = 0;
+
+			dsp_branch_condition_table[i * 32 + j] = result;
 		}
 	}
 }
@@ -488,7 +529,7 @@ uint8 DSPReadByte(uint32 offset, uint32 who/*=UNKNOWN*/)
 	}
 
 	return JaguarReadByte(offset, who);
-} 
+}
 
 uint16 DSPReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
 {
@@ -513,12 +554,12 @@ uint16 DSPReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
 		if (offset==0xF1B2C2) return(0x0000);
 	}
 */
-	// pour permettre à wolfenstein 3d de tourner sans le dsp
+	// pour permettre � wolfenstein 3d de tourner sans le dsp
 /*	if ((offset==0xF1B0D0)||(offset==0xF1B0D2))
 		return(0);
 */
 
-		// pour permettre à nba jam de tourner sans le dsp
+		// pour permettre � nba jam de tourner sans le dsp
 /*	if (jaguar_mainRom_crc32==0x4faddb18)
 	{
 		if (offset==0xf1b2c0) return(0);
@@ -583,12 +624,9 @@ uint32 DSPReadLong(uint32 offset, uint32 who/*=UNKNOWN*/)
 		offset &= 0x3F;
 		switch (offset)
 		{
-		case 0x00:	/*dsp_flag_c?(dsp_flag_c=1):(dsp_flag_c=0);
-					dsp_flag_z?(dsp_flag_z=1):(dsp_flag_z=0);
-					dsp_flag_n?(dsp_flag_n=1):(dsp_flag_n=0);*/
-
-					dsp_flags = (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z;
-					return dsp_flags & 0xFFFFC1FF;
+		case 0x00:
+			dsp_flags = (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z;
+			return dsp_flags & 0xFFFFC1FF;
 		case 0x04: return dsp_matrix_control;
 		case 0x08: return dsp_pointer_to_matrix;
 		case 0x0C: return dsp_data_organization;
@@ -619,7 +657,7 @@ void DSPWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
 /*		if (dsp_in_exec == 0)
 		{
 			m68k_end_timeslice();
-			gpu_releaseTimeslice();
+			dsp_releaseTimeslice();
 		}*/
 		return;
 	}
@@ -627,7 +665,7 @@ void DSPWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
 	{
 		uint32 reg = offset & 0x1C;
 		int bytenum = offset & 0x03;
-		
+
 		if ((reg >= 0x1C) && (reg <= 0x1F))
 			dsp_div_control = (dsp_div_control & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3));
 		else
@@ -635,7 +673,7 @@ void DSPWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
 //This looks funky. !!! FIX !!!
 			uint32 old_data = DSPReadLong(offset&0xFFFFFFC, who);
 			bytenum = 3 - bytenum; // convention motorola !!!
-			old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3));	
+			old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3));
 			DSPWriteLong(offset & 0xFFFFFFC, old_data, who);
 		}
 		return;
@@ -657,6 +695,10 @@ void DSPWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
 //	WriteLog("dsp: writing %.4x at 0x%.8x\n",data,offset);
 	if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
 	{
+/*if (offset == 0xF1B2F4)
+{
+	WriteLog("DSP: %s is writing %04X at location 0xF1B2F4 (DSP_PC: %08X)...\n", whoName[who], data, dsp_pc);
+}//*/
 		offset -= DSP_WORK_RAM_BASE;
 		dsp_ram_8[offset] = data >> 8;
 		dsp_ram_8[offset+1] = data & 0xFF;
@@ -665,8 +707,14 @@ void DSPWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
 		{
 //			WriteLog("dsp: writing %.4x at 0x%.8x\n",data,offset+DSP_WORK_RAM_BASE);
 			m68k_end_timeslice();
-			gpu_releaseTimeslice();
+			dsp_releaseTimeslice();
 		}*/
+//CC only!
+#ifdef DSP_DEBUG_CC
+SET16(ram1, offset, data),
+SET16(ram2, offset, data);
+#endif
+//!!!!!!!!
 		return;
 	}
 	else if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
@@ -674,19 +722,22 @@ void DSPWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
 		if ((offset & 0x1C) == 0x1C)
 		{
 			if (offset & 0x03)
-				dsp_div_control = (dsp_div_control&0xffff0000)|(data&0xffff);
+				dsp_div_control = (dsp_div_control & 0xFFFF0000) | (data & 0xFFFF);
 			else
-				dsp_div_control = (dsp_div_control&0xffff)|((data&0xffff)<<16);
+				dsp_div_control = (dsp_div_control & 0xFFFF) | ((data & 0xFFFF) << 16);
 		}
 		else
 		{
-			uint32 old_data = DSPReadLong(offset & 0xffffffc, who);
+			uint32 old_data = DSPReadLong(offset & 0xFFFFFFC, who);
+
 			if (offset & 0x03)
-				old_data = (old_data&0xffff0000)|(data&0xffff);
+				old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF);
 			else
-				old_data = (old_data&0xffff)|((data&0xffff)<<16);
-			DSPWriteLong(offset & 0xffffffc, old_data, who);
+				old_data = (old_data & 0xFFFF) | ((data & 0xFFFF) << 16);
+
+			DSPWriteLong(offset & 0xFFFFFFC, old_data, who);
 		}
+
 		return;
 	}
 
@@ -713,6 +764,12 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
 }//*/
 		offset -= DSP_WORK_RAM_BASE;
 		SET32(dsp_ram_8, offset, data);
+//CC only!
+#ifdef DSP_DEBUG_CC
+SET32(ram1, offset, data),
+SET32(ram2, offset, data);
+#endif
+//!!!!!!!!
 		return;
 	}
 	else if (offset >= DSP_CONTROL_RAM_BASE && offset <= (DSP_CONTROL_RAM_BASE + 0x1F))
@@ -723,17 +780,61 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
 		case 0x00:
 		{
 #ifdef DSP_DEBUG
-			WriteLog("DSP: Writing %08X to DSP_FLAGS by %s (REGPAGE is %s)...\n", data, whoName[who], (dsp_flags & REGPAGE ? "set" : "not set"));
+			WriteLog("DSP: Writing %08X to DSP_FLAGS by %s (REGPAGE is %sset)...\n", data, whoName[who], (dsp_flags & REGPAGE ? "" : "not "));
 #endif
 //			bool IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK);
 			IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK);
-			dsp_flags = data;
+			// NOTE: According to the JTRM, writing a 1 to IMASK has no effect; only the
+			//       IRQ logic can set it. So we mask it out here to prevent problems...
+			dsp_flags = data & (~IMASK);
 			dsp_flag_z = dsp_flags & 0x01;
 			dsp_flag_c = (dsp_flags >> 1) & 0x01;
 			dsp_flag_n = (dsp_flags >> 2) & 0x01;
 			DSPUpdateRegisterBanks();
 			dsp_control &= ~((dsp_flags & CINT04FLAGS) >> 3);
 			dsp_control &= ~((dsp_flags & CINT5FLAG) >> 1);
+
+// NB: This is just a wild hairy-assed guess as to what the playback frequency is.
+//     It can be timed to anything really, anything that writes to L/RTXD at a regular
+//     interval. Most things seem to use either the I2S interrupt or the TIMER 0
+//     interrupt, so that's what we check for here. Just know that this approach
+//     can be easily fooled!
+//     Note also that if both interrupts are enabled, the I2S freq will win. :-P
+
+// Further Note:
+// The impetus for this "fix" was Cybermorph, which sets the SCLK to 7 which is an
+// audio frequency > 48 KHz. However, it stuffs the L/RTXD registers using TIMER0.
+// So, while this works, it's a by-product of the lame way in which audio is currently
+// handled. Hopefully, once we run the DSP in the host audio IRQ, this problem will
+// go away of its own accord. :-P
+// Or does it? It seems the I2S interrupt isn't on with Cybermorph, so something
+// weird is going on here...
+// Maybe it works like this: It acknowledges the 1st interrupt, but never clears it.
+// So subsequent interrupts come into the chip, but they're never serviced but the
+// I2S subsystem keeps going.
+// After some testing on real hardware, it seems that if you enable TIMER0 and EXTERNAL
+// IRQs on J_INT ($F10020), you don't have to run an I2S interrupt on the DSP. Also,
+// It seems that it's only stable for values of SCLK <= 9.
+
+// All of the preceeding is moot now; we run the DSP in the host audio IRQ. This means
+// that we don't actually need this stuff anymore. :-D
+#if 0
+			if (data & INT_ENA1) // I2S interrupt
+			{
+				int freq = GetCalculatedFrequency();
+//This happens too often to be useful...
+//				WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq);
+				DACSetNewFrequency(freq);
+			}
+			else if (data & INT_ENA2) // TIMER 0 interrupt
+			{
+				int freq = JERRYGetPIT1Frequency();
+//This happens too often to be useful...
+//				WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq);
+				DACSetNewFrequency(freq);
+			}
+#endif
+
 /*			if (IMASKCleared)						// If IMASK was cleared,
 #ifdef DSP_DEBUG_IRQ
 			{
@@ -743,13 +844,36 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
 #ifdef DSP_DEBUG_IRQ
 			}
 #endif//*/
+#if 0
+			if (/*4-8, 16*/data & 0x101F0)
+				WriteLog("DSP: %s is enabling interrupts %s%s%s%s%s%s\n", whoName[who],
+					(data & 0x010 ? "CPU " : ""), (data & 0x020 ? "I2S " : ""),
+					(data & 0x040 ? "TIMER0 " : ""), (data & 0x080 ? "TIMER1 " : ""),
+					(data & 0x100 ? "EXT0 " : ""), (data & 0x10000 ? "EXT1" : ""));
+/*if (data & 0x00020) // CD BIOS DSP code...
+{
+//001AC1BA: movea.l #$1AC200, A0
+//001AC1C0: move.l  #$1AC68C, D0
+	char buffer[512];
+
+	WriteLog("\n---[DSP code at 00F1B97C]---------------------------\n");
+	uint32 j = 0xF1B97C;//0x1AC200;
+	while (j <= 0xF1BE08)//0x1AC68C)
+	{
+		uint32 oldj = j;
+		j += dasmjag(JAGUAR_DSP, buffer, j);
+//		WriteLog("\t%08X: %s\n", oldj+0xD6F77C, buffer);
+		WriteLog("\t%08X: %s\n", oldj, buffer);
+	}
+}//*/
+#endif
 			break;
 		}
 		case 0x04:
 			dsp_matrix_control = data;
 			break;
 		case 0x08:
-			// According to JTRM, only lines 2-11 are adressable, the rest being
+			// According to JTRM, only lines 2-11 are addressable, the rest being
 			// hardwired to $F1Bxxx.
 			dsp_pointer_to_matrix = 0xF1B000 | (data & 0x000FFC);
 			break;
@@ -761,21 +885,34 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
 #ifdef DSP_DEBUG
 			WriteLog("DSP: Setting DSP PC to %08X by %s%s\n", dsp_pc, whoName[who], (DSP_RUNNING ? " (DSP is RUNNING!)" : ""));//*/
 #endif
+//CC only!
+#ifdef DSP_DEBUG_CC
+if (who != DSP)
+	ctrl1[0] = ctrl2[0] = data;
+#endif
+//!!!!!!!!
 			break;
 		case 0x14:
-		{	
+		{
+//#ifdef DSP_DEBUG
+WriteLog("Write to DSP CTRL by %s: %08X (DSP PC=$%08X)\n", whoName[who], data, dsp_pc);
+//#endif
+			bool wasRunning = DSP_RUNNING;
 //			uint32 dsp_was_running = DSP_RUNNING;
 			// Check for DSP -> CPU interrupt
 			if (data & CPUINT)
 			{
-//				WriteLog("DSP: DSP -> CPU interrupt\n");
+#ifdef DSP_DEBUG
+				WriteLog("DSP: DSP -> CPU interrupt\n");
+#endif
 // This was WRONG
-// Why do we check for a valid handler at 64? Isn't that the Jag programmer's responsibility?
+// Why do we check for a valid handler at 64? Isn't that the Jag programmer's responsibility? (YES)
+#warning "!!! DSP IRQs that go to the 68K have to be routed thru TOM !!! FIX !!!"
 				if (JERRYIRQEnabled(IRQ2_DSP))// && jaguar_interrupt_handler_is_valid(64))
 				{
 					JERRYSetPendingIRQ(IRQ2_DSP);
-					dsp_releaseTimeslice();
-					m68k_set_irq(7);			// Set 68000 NMI...
+					DSPReleaseTimeslice();
+					m68k_set_irq(2);			// Set 68000 IPL 2...
 				}
 				data &= ~CPUINT;
 			}
@@ -786,7 +923,7 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
 				WriteLog("DSP: CPU -> DSP interrupt\n");
 #endif
 				m68k_end_timeslice();
-				gpu_releaseTimeslice();
+				DSPReleaseTimeslice();
 				DSPSetIRQLine(DSPIRQ_CPU, ASSERT_LINE);
 				data &= ~DSPINT0;
 			}
@@ -799,6 +936,12 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
 			// Protect writes to VERSION and the interrupt latches...
 			uint32 mask = VERSION | INT_LAT0 | INT_LAT1 | INT_LAT2 | INT_LAT3 | INT_LAT4 | INT_LAT5;
 			dsp_control = (dsp_control & mask) | (data & ~mask);
+//CC only!
+#ifdef DSP_DEBUG_CC
+if (who != DSP)
+	ctrl1[8] = ctrl2[8] = dsp_control;
+#endif
+//!!!!!!!!
 
 			// if dsp wasn't running but is now running
 			// execute a few cycles
@@ -814,23 +957,23 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
 				DSPExec(1);
 #endif
 #ifdef DSP_DEBUG
-WriteLog("Write to DSP CTRL: %08X ", data);
 if (DSP_RUNNING)
 	WriteLog(" --> Starting to run at %08X by %s...", dsp_pc, whoName[who]);
 else
 	WriteLog(" --> Stopped by %s! (DSP PC: %08X)", whoName[who], dsp_pc);
 WriteLog("\n");
 #endif	// DSP_DEBUG
-//This isn't exactly right either--we don't know if it was the M68K or the GPU writing here...
+//This isn't exactly right either--we don't know if it was the M68K or the DSP writing here...
 // !!! FIX !!! [DONE]
 			if (DSP_RUNNING)
 			{
 				if (who == M68K)
 					m68k_end_timeslice();
-				else if (who == GPU)
-					gpu_releaseTimeslice();
+				else if (who == DSP)
+					DSPReleaseTimeslice();
 
-				FlushDSPPipeline();
+				if (!wasRunning)
+					FlushDSPPipeline();
 //DSPDumpDisassembly();
 			}
 			break;
@@ -872,7 +1015,7 @@ void DSPUpdateRegisterBanks(void)
 }
 
 //
-// Check for an handle any asserted DSP IRQs
+// Check for and handle any asserted DSP IRQs
 //
 void DSPHandleIRQs(void)
 {
@@ -889,7 +1032,7 @@ void DSPHandleIRQs(void)
 	if (!bits)										// Bail if nothing is enabled
 		return;
 
-	int which = 0;									// Determine which interrupt 
+	int which = 0;									// Determine which interrupt
 	if (bits & 0x01)
 		which = 0;
 	if (bits & 0x02)
@@ -921,6 +1064,16 @@ void DSPHandleIRQs(void)
 		if (affectsScoreboard[pipeline[plPtrWrite].opcode])
 			scoreboard[pipeline[plPtrWrite].operand2] = false;
 	}//*/
+//This should be execute (or should it?--not sure now!)
+//Actually, the way this is called now, this should be correct (i.e., the plPtrs advance,
+//and what just executed is now in the Write position...). So why didn't it do the
+//writeback into register 0?
+#ifdef DSP_DEBUG_IRQ
+WriteLog("--> Pipeline dump [DSP_PC=%08X]...\n", dsp_pc);
+WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]);
+WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]);
+WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]);
+#endif
 	if (pipeline[plPtrWrite].opcode != PIPELINE_STALL)
 	{
 		if (pipeline[plPtrWrite].writebackRegister != 0xFF)
@@ -938,21 +1091,38 @@ void DSPHandleIRQs(void)
 			}
 		}
 
+#ifndef NEW_SCOREBOARD
 		if (affectsScoreboard[pipeline[plPtrWrite].opcode])
 			scoreboard[pipeline[plPtrWrite].operand2] = false;
+#else
+//Yup, sequential MOVEQ # problem fixing (I hope!)...
+		if (affectsScoreboard[pipeline[plPtrWrite].opcode])
+			if (scoreboard[pipeline[plPtrWrite].operand2])
+				scoreboard[pipeline[plPtrWrite].operand2]--;
+#endif
 	}
 
 	dsp_flags |= IMASK;
+//CC only!
+#ifdef DSP_DEBUG_CC
+ctrl2[4] = dsp_flags;
+#endif
+//!!!!!!!!
 	DSPUpdateRegisterBanks();
 #ifdef DSP_DEBUG_IRQ
 //	WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc, dsp_reg[31]);
 	WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)), dsp_reg[31]);
 #endif
 
-	// subqt  #4,r31		; pre-decrement stack pointer 
-	// move   pc,r30		; address of interrupted code 
+	// subqt  #4,r31		; pre-decrement stack pointer
+	// move   pc,r30		; address of interrupted code
 	// store  r30,(r31)     ; store return address
 	dsp_reg[31] -= 4;
+//CC only!
+#ifdef DSP_DEBUG_CC
+regs2[31] -= 4;
+#endif
+//!!!!!!!!
 //This might not come back to the right place if the instruction was MOVEI #. !!! FIX !!!
 //But, then again, JTRM says that it adds two regardless of what the instruction was...
 //It missed the place that it was supposed to come back to, so this is WRONG!
@@ -970,14 +1140,120 @@ void DSPHandleIRQs(void)
 
 //	DSPWriteLong(dsp_reg[31], dsp_pc - 2, DSP);
 	DSPWriteLong(dsp_reg[31], dsp_pc - 2 - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)), DSP);
+//CC only!
+#ifdef DSP_DEBUG_CC
+SET32(ram2, regs2[31] - 0xF1B000, dsp_pc - 2 - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)));
+#endif
+//!!!!!!!!
 
-	// movei  #service_address,r30  ; pointer to ISR entry 
-	// jump  (r30)					; jump to ISR 
+	// movei  #service_address,r30  ; pointer to ISR entry
+	// jump  (r30)					; jump to ISR
 	// nop
 	dsp_pc = dsp_reg[30] = DSP_WORK_RAM_BASE + (which * 0x10);
+//CC only!
+#ifdef DSP_DEBUG_CC
+ctrl2[0] = regs2[30] = dsp_pc;
+#endif
+//!!!!!!!!
 	FlushDSPPipeline();
 }
 
+//
+// Non-pipelined version...
+//
+void DSPHandleIRQsNP(void)
+{
+//CC only!
+#ifdef DSP_DEBUG_CC
+		memcpy(dsp_ram_8, ram1, 0x2000);
+		memcpy(dsp_reg_bank_0, regs1, 32 * 4);
+		memcpy(dsp_reg_bank_1, &regs1[32], 32 * 4);
+		dsp_pc					= ctrl1[0];
+		dsp_acc					= ctrl1[1];
+		dsp_remain				= ctrl1[2];
+		dsp_modulo				= ctrl1[3];
+		dsp_flags				= ctrl1[4];
+		dsp_matrix_control		= ctrl1[5];
+		dsp_pointer_to_matrix	= ctrl1[6];
+		dsp_data_organization	= ctrl1[7];
+		dsp_control				= ctrl1[8];
+		dsp_div_control			= ctrl1[9];
+		IMASKCleared			= ctrl1[10];
+		dsp_flag_z				= ctrl1[11];
+		dsp_flag_n				= ctrl1[12];
+		dsp_flag_c				= ctrl1[13];
+DSPUpdateRegisterBanks();
+#endif
+//!!!!!!!!
+	if (dsp_flags & IMASK) 							// Bail if we're already inside an interrupt
+		return;
+
+	// Get the active interrupt bits (latches) & interrupt mask (enables)
+	uint32 bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F),
+		mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F);
+
+//	WriteLog("dsp: bits=%.2x mask=%.2x\n",bits,mask);
+	bits &= mask;
+
+	if (!bits)										// Bail if nothing is enabled
+		return;
+
+	int which = 0;									// Determine which interrupt
+	if (bits & 0x01)
+		which = 0;
+	if (bits & 0x02)
+		which = 1;
+	if (bits & 0x04)
+		which = 2;
+	if (bits & 0x08)
+		which = 3;
+	if (bits & 0x10)
+		which = 4;
+	if (bits & 0x20)
+		which = 5;
+
+#ifdef DSP_DEBUG_IRQ
+	WriteLog("DSP: Generating interrupt #%i...", which);
+#endif
+
+	dsp_flags |= IMASK;
+//CC only!
+#ifdef DSP_DEBUG_CC
+ctrl1[4] = dsp_flags;
+#endif
+//!!!!!!!!
+	DSPUpdateRegisterBanks();
+#ifdef DSP_DEBUG_IRQ
+	WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc, dsp_reg[31]);
+#endif
+
+	// subqt  #4,r31		; pre-decrement stack pointer
+	// move   pc,r30		; address of interrupted code
+	// store  r30,(r31)     ; store return address
+	dsp_reg[31] -= 4;
+//CC only!
+#ifdef DSP_DEBUG_CC
+regs1[31] -= 4;
+#endif
+//!!!!!!!!
+	DSPWriteLong(dsp_reg[31], dsp_pc - 2, DSP);
+//CC only!
+#ifdef DSP_DEBUG_CC
+SET32(ram1, regs1[31] - 0xF1B000, dsp_pc - 2);
+#endif
+//!!!!!!!!
+
+	// movei  #service_address,r30  ; pointer to ISR entry
+	// jump  (r30)					; jump to ISR
+	// nop
+	dsp_pc = dsp_reg[30] = DSP_WORK_RAM_BASE + (which * 0x10);
+//CC only!
+#ifdef DSP_DEBUG_CC
+ctrl1[0] = regs1[30] = dsp_pc;
+#endif
+//!!!!!!!!
+}
+
 //
 // Set the specified DSP IRQ line to a given state
 //
@@ -986,22 +1262,44 @@ void DSPSetIRQLine(int irqline, int state)
 //NOTE: This doesn't take INT_LAT5 into account. !!! FIX !!!
 	uint32 mask = INT_LAT0 << irqline;
 	dsp_control &= ~mask;							// Clear the latch bit
+//CC only!
+#ifdef DSP_DEBUG_CC
+ctrl1[8] = ctrl2[8] = dsp_control;
+#endif
+//!!!!!!!!
 
 	if (state)
 	{
 		dsp_control |= mask;						// Set the latch bit
 		DSPHandleIRQs();
+//CC only!
+#ifdef DSP_DEBUG_CC
+ctrl1[8] = ctrl2[8] = dsp_control;
+DSPHandleIRQsNP();
+#endif
+//!!!!!!!!
 	}
+
+	// Not sure if this is correct behavior, but according to JTRM,
+	// the IRQ output of JERRY is fed to this IRQ in the GPU...
+// Not sure this is right--DSP interrupts seem to be different from the JERRY interrupts!
+//	GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE);
+}
+
+bool DSPIsRunning(void)
+{
+	return (DSP_RUNNING ? true : false);
 }
 
 void DSPInit(void)
 {
-	memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM");
-	memory_malloc_secure((void **)&dsp_reg_bank_0, 32 * sizeof(int32), "DSP bank 0 regs");
-	memory_malloc_secure((void **)&dsp_reg_bank_1, 32 * sizeof(int32), "DSP bank 1 regs");
+//	memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM");
+//	memory_malloc_secure((void **)&dsp_reg_bank_0, 32 * sizeof(int32), "DSP bank 0 regs");
+//	memory_malloc_secure((void **)&dsp_reg_bank_1, 32 * sizeof(int32), "DSP bank 1 regs");
 
 	dsp_build_branch_condition_table();
 	DSPReset();
+	srand(time(NULL));							// For randomizing local RAM
 }
 
 void DSPReset(void)
@@ -1026,8 +1324,14 @@ void DSPReset(void)
 
 	CLR_ZNC;
 	IMASKCleared = false;
+	FlushDSPPipeline();
 	dsp_reset_stats();
-	memset(dsp_ram_8, 0xFF, 0x2000);
+//	memset(dsp_ram_8, 0xFF, 0x2000);
+	// Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents
+	for(uint32 i=0; i<8192; i+=4)
+	{
+		*((uint32 *)(&dsp_ram_8[i])) = rand();
+	}
 }
 
 void DSPDumpDisassembly(void)
@@ -1036,6 +1340,7 @@ void DSPDumpDisassembly(void)
 
 	WriteLog("\n---[DSP code at 00F1B000]---------------------------\n");
 	uint32 j = 0xF1B000;
+
 	while (j <= 0xF1CFFF)
 	{
 		uint32 oldj = j;
@@ -1049,6 +1354,7 @@ void DSPDumpRegisters(void)
 //Shoud add modulus, etc to dump here...
 	WriteLog("\n---[DSP flags: NCZ %d%d%d, DSP PC: %08X]------------\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_pc);
 	WriteLog("\nRegisters bank 0\n");
+
 	for(int j=0; j<8; j++)
 	{
 		WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n",
@@ -1057,7 +1363,9 @@ void DSPDumpRegisters(void)
 						  (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2],
 						  (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]);
 	}
+
 	WriteLog("Registers bank 1\n");
+
 	for(int j=0; j<8; j++)
 	{
 		WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n",
@@ -1071,38 +1379,46 @@ void DSPDumpRegisters(void)
 void DSPDone(void)
 {
 	int i, j;
-	WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp %s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "was" : "wasn't"));
+	WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp was%s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "" : "n't"));
 	WriteLog("DSP: %sin interrupt handler\n", (dsp_flags & IMASK ? "" : "not "));
 
-	// get the active interrupt bits 
+	// get the active interrupt bits
 	int bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F);
-	// get the interrupt mask 
+	// get the interrupt mask
 	int mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F);
 
-	WriteLog("DSP: pending=%08X enabled=%08X\n", bits, mask);
+	WriteLog("DSP: pending=$%X enabled=$%X (%s%s%s%s%s%s)\n", bits, mask,
+		(mask & 0x01 ? "CPU " : ""), (mask & 0x02 ? "I2S " : ""),
+		(mask & 0x04 ? "Timer0 " : ""), (mask & 0x08 ? "Timer1 " : ""),
+		(mask & 0x10 ? "Ext0 " : ""), (mask & 0x20 ? "Ext1" : ""));
 	WriteLog("\nRegisters bank 0\n");
+
 	for(int j=0; j<8; j++)
 	{
-		WriteLog("\tr%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x\n",
+		WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n",
 						  (j << 2) + 0, dsp_reg_bank_0[(j << 2) + 0],
 						  (j << 2) + 1, dsp_reg_bank_0[(j << 2) + 1],
 						  (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2],
 						  (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]);
 	}
+
 	WriteLog("\nRegisters bank 1\n");
+
 	for (j=0; j<8; j++)
 	{
-		WriteLog("\tr%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x\n",
+		WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n",
 						  (j << 2) + 0, dsp_reg_bank_1[(j << 2) + 0],
 						  (j << 2) + 1, dsp_reg_bank_1[(j << 2) + 1],
 						  (j << 2) + 2, dsp_reg_bank_1[(j << 2) + 2],
 						  (j << 2) + 3, dsp_reg_bank_1[(j << 2) + 3]);
-
 	}
 
+	WriteLog("\n");
+
 	static char buffer[512];
 	j = DSP_WORK_RAM_BASE;
-	while (j <= 0xF1BFFF)
+
+	while (j <= 0xF1CFFF)
 	{
 		uint32 oldj = j;
 		j += dasmjag(JAGUAR_DSP, buffer, j);
@@ -1110,14 +1426,224 @@ void DSPDone(void)
 	}//*/
 
 	WriteLog("DSP opcodes use:\n");
+
 	for (i=0;i<64;i++)
 	{
 		if (dsp_opcode_use[i])
 			WriteLog("\t%s %i\n", dsp_opcode_str[i], dsp_opcode_use[i]);
 	}//*/
 
-	memory_free(dsp_ram_8);
+//	memory_free(dsp_ram_8);
+//	memory_free(dsp_reg_bank_0);
+//	memory_free(dsp_reg_bank_1);
+//	if (dsp_branch_condition_table)
+//		free(dsp_branch_condition_table);
+
+//	if (mirror_table)
+//		free(mirror_table);
+}
+
+
+
+//
+// DSP comparison core...
+//
+#ifdef DSP_DEBUG_CC
+static uint16 lastExec;
+void DSPExecComp(int32 cycles)
+{
+	while (cycles > 0 && DSP_RUNNING)
+	{
+		// Load up vars for non-pipelined core
+		memcpy(dsp_ram_8, ram1, 0x2000);
+		memcpy(dsp_reg_bank_0, regs1, 32 * 4);
+		memcpy(dsp_reg_bank_1, &regs1[32], 32 * 4);
+		dsp_pc					= ctrl1[0];
+		dsp_acc					= ctrl1[1];
+		dsp_remain				= ctrl1[2];
+		dsp_modulo				= ctrl1[3];
+		dsp_flags				= ctrl1[4];
+		dsp_matrix_control		= ctrl1[5];
+		dsp_pointer_to_matrix	= ctrl1[6];
+		dsp_data_organization	= ctrl1[7];
+		dsp_control				= ctrl1[8];
+		dsp_div_control			= ctrl1[9];
+		IMASKCleared			= ctrl1[10];
+		dsp_flag_z				= ctrl1[11];
+		dsp_flag_n				= ctrl1[12];
+		dsp_flag_c				= ctrl1[13];
+DSPUpdateRegisterBanks();
+
+		// Decrement cycles based on non-pipelined core...
+		uint16 instr1 = DSPReadWord(dsp_pc, DSP);
+		cycles -= dsp_opcode_cycles[instr1 >> 10];
+
+//WriteLog("\tAbout to execute non-pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32)count, dsp_pc);
+		DSPExec(1);									// Do *one* instruction
+
+		// Save vars
+		memcpy(ram1, dsp_ram_8, 0x2000);
+		memcpy(regs1, dsp_reg_bank_0, 32 * 4);
+		memcpy(&regs1[32], dsp_reg_bank_1, 32 * 4);
+		ctrl1[0]  = dsp_pc;
+		ctrl1[1]  = dsp_acc;
+		ctrl1[2]  = dsp_remain;
+		ctrl1[3]  = dsp_modulo;
+		ctrl1[4]  = dsp_flags;
+		ctrl1[5]  = dsp_matrix_control;
+		ctrl1[6]  = dsp_pointer_to_matrix;
+		ctrl1[7]  = dsp_data_organization;
+		ctrl1[8]  = dsp_control;
+		ctrl1[9]  = dsp_div_control;
+		ctrl1[10] = IMASKCleared;
+		ctrl1[11] = dsp_flag_z;
+		ctrl1[12] = dsp_flag_n;
+		ctrl1[13] = dsp_flag_c;
+
+		// Load up vars for pipelined core
+		memcpy(dsp_ram_8, ram2, 0x2000);
+		memcpy(dsp_reg_bank_0, regs2, 32 * 4);
+		memcpy(dsp_reg_bank_1, &regs2[32], 32 * 4);
+		dsp_pc					= ctrl2[0];
+		dsp_acc					= ctrl2[1];
+		dsp_remain				= ctrl2[2];
+		dsp_modulo				= ctrl2[3];
+		dsp_flags				= ctrl2[4];
+		dsp_matrix_control		= ctrl2[5];
+		dsp_pointer_to_matrix	= ctrl2[6];
+		dsp_data_organization	= ctrl2[7];
+		dsp_control				= ctrl2[8];
+		dsp_div_control			= ctrl2[9];
+		IMASKCleared			= ctrl2[10];
+		dsp_flag_z				= ctrl2[11];
+		dsp_flag_n				= ctrl2[12];
+		dsp_flag_c				= ctrl2[13];
+DSPUpdateRegisterBanks();
+
+//WriteLog("\tAbout to execute pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32)count, dsp_pc);
+		DSPExecP2(1);								// Do *one* instruction
+
+		// Save vars
+		memcpy(ram2, dsp_ram_8, 0x2000);
+		memcpy(regs2, dsp_reg_bank_0, 32 * 4);
+		memcpy(&regs2[32], dsp_reg_bank_1, 32 * 4);
+		ctrl2[0]  = dsp_pc;
+		ctrl2[1]  = dsp_acc;
+		ctrl2[2]  = dsp_remain;
+		ctrl2[3]  = dsp_modulo;
+		ctrl2[4]  = dsp_flags;
+		ctrl2[5]  = dsp_matrix_control;
+		ctrl2[6]  = dsp_pointer_to_matrix;
+		ctrl2[7]  = dsp_data_organization;
+		ctrl2[8]  = dsp_control;
+		ctrl2[9]  = dsp_div_control;
+		ctrl2[10] = IMASKCleared;
+		ctrl2[11] = dsp_flag_z;
+		ctrl2[12] = dsp_flag_n;
+		ctrl2[13] = dsp_flag_c;
+
+		if (instr1 != lastExec)
+		{
+//			WriteLog("\nCores diverged at instruction tick #%u!\nAttemping to synchronize...\n\n", count);
+
+//			uint32 ppc = ctrl2[0] - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)) - (pipeline[plPtrWrite].opcode == 38 ? 6 : (pipeline[plPtrWrite].opcode == PIPELINE_STALL ? 0 : 2));
+//WriteLog("[DSP_PC1=%08X, DSP_PC2=%08X]\n", ctrl1[0], ppc);
+//			if (ctrl1[0] < ppc)						// P ran ahead of NP
+//How to test this crap???
+//			if (1)
+			{
+		DSPExecP2(1);								// Do one more instruction
+
+		// Save vars
+		memcpy(ram2, dsp_ram_8, 0x2000);
+		memcpy(regs2, dsp_reg_bank_0, 32 * 4);
+		memcpy(&regs2[32], dsp_reg_bank_1, 32 * 4);
+		ctrl2[0]  = dsp_pc;
+		ctrl2[1]  = dsp_acc;
+		ctrl2[2]  = dsp_remain;
+		ctrl2[3]  = dsp_modulo;
+		ctrl2[4]  = dsp_flags;
+		ctrl2[5]  = dsp_matrix_control;
+		ctrl2[6]  = dsp_pointer_to_matrix;
+		ctrl2[7]  = dsp_data_organization;
+		ctrl2[8]  = dsp_control;
+		ctrl2[9]  = dsp_div_control;
+		ctrl2[10] = IMASKCleared;
+		ctrl2[11] = dsp_flag_z;
+		ctrl2[12] = dsp_flag_n;
+		ctrl2[13] = dsp_flag_c;
+			}
+//			else									// NP ran ahead of P
+		if (instr1 != lastExec)						// Must be the other way...
+
+			{
+		// Load up vars for non-pipelined core
+		memcpy(dsp_ram_8, ram1, 0x2000);
+		memcpy(dsp_reg_bank_0, regs1, 32 * 4);
+		memcpy(dsp_reg_bank_1, &regs1[32], 32 * 4);
+		dsp_pc					= ctrl1[0];
+		dsp_acc					= ctrl1[1];
+		dsp_remain				= ctrl1[2];
+		dsp_modulo				= ctrl1[3];
+		dsp_flags				= ctrl1[4];
+		dsp_matrix_control		= ctrl1[5];
+		dsp_pointer_to_matrix	= ctrl1[6];
+		dsp_data_organization	= ctrl1[7];
+		dsp_control				= ctrl1[8];
+		dsp_div_control			= ctrl1[9];
+		IMASKCleared			= ctrl1[10];
+		dsp_flag_z				= ctrl1[11];
+		dsp_flag_n				= ctrl1[12];
+		dsp_flag_c				= ctrl1[13];
+DSPUpdateRegisterBanks();
+
+for(int k=0; k<2; k++)
+{
+		// Decrement cycles based on non-pipelined core...
+		instr1 = DSPReadWord(dsp_pc, DSP);
+		cycles -= dsp_opcode_cycles[instr1 >> 10];
+
+//WriteLog("\tAbout to execute non-pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32)count, dsp_pc);
+		DSPExec(1);									// Do *one* instruction
+}
+
+		// Save vars
+		memcpy(ram1, dsp_ram_8, 0x2000);
+		memcpy(regs1, dsp_reg_bank_0, 32 * 4);
+		memcpy(&regs1[32], dsp_reg_bank_1, 32 * 4);
+		ctrl1[0]  = dsp_pc;
+		ctrl1[1]  = dsp_acc;
+		ctrl1[2]  = dsp_remain;
+		ctrl1[3]  = dsp_modulo;
+		ctrl1[4]  = dsp_flags;
+		ctrl1[5]  = dsp_matrix_control;
+		ctrl1[6]  = dsp_pointer_to_matrix;
+		ctrl1[7]  = dsp_data_organization;
+		ctrl1[8]  = dsp_control;
+		ctrl1[9]  = dsp_div_control;
+		ctrl1[10] = IMASKCleared;
+		ctrl1[11] = dsp_flag_z;
+		ctrl1[12] = dsp_flag_n;
+		ctrl1[13] = dsp_flag_c;
+			}
+		}
+
+		if (instr1 != lastExec)
+		{
+			WriteLog("\nCores diverged at instruction tick #%u!\nStopped!\n\n", count);
+
+			WriteLog("Instruction for non-pipelined core: %04X\n", instr1);
+			WriteLog("Instruction for pipelined core: %04X\n", lastExec);
+
+			log_done();
+			exit(1);
+		}
+
+		count++;
+	}
 }
+#endif
+
 
 //
 // DSP execution core
@@ -1143,6 +1669,30 @@ void DSPExec(int32 cycles)
 
 	while (cycles > 0 && DSP_RUNNING)
 	{
+/*extern uint32 totalFrames;
+//F1B2F6: LOAD   (R14+$04), R24 [NCZ:001, R14+$04=00F20018, R24=FFFFFFFF] -> Jaguar: Unknown word read at 00F20018 by DSP (M68K PC=00E32E)
+//-> 43 + 1 + 24 -> $2B + $01 + $18 -> 101011 00001 11000 -> 1010 1100 0011 1000 -> AC38
+//C470 -> 1100 0100 0111 0000 -> 110001 00011 10000 -> 49, 3, 16 -> STORE R16, (R14+$0C)
+//F1B140:
+if (totalFrames >= 377 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38 && dsp_pc == 0xF1B140)
+{
+	doDSPDis = true;
+	WriteLog("Starting disassembly at frame #%u...\n", totalFrames);
+}
+if (dsp_pc == 0xF1B092)
+	doDSPDis = false;//*/
+/*if (dsp_pc == 0xF1B140)
+	doDSPDis = true;//*/
+
+		if (IMASKCleared)						// If IMASK was cleared,
+		{
+#ifdef DSP_DEBUG_IRQ
+			WriteLog("DSP: Finished interrupt.\n");
+#endif
+			DSPHandleIRQsNP();					// See if any other interrupts are pending!
+			IMASKCleared = false;
+		}
+
 /*if (badWrite)
 {
 	WriteLog("\nDSP: Encountered bad write in Atari Synth module. PC=%08X, R15=%08X\n", dsp_pc, dsp_reg[15]);
@@ -1207,7 +1757,7 @@ if ((dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFE) && !tripwire)
 static void dsp_opcode_jump(void)
 {
 #ifdef DSP_DIS_JUMP
-char * condition[32] =
+const char * condition[32] =
 {	"T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz",
 	"c z", "???", "???", "???", "???", "???", "???", "???", "???",
 	"???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???",
@@ -1242,7 +1792,7 @@ char * condition[32] =
 static void dsp_opcode_jr(void)
 {
 #ifdef DSP_DIS_JR
-char * condition[32] =
+const char * condition[32] =
 {	"T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz",
 	"c z", "???", "???", "???", "???", "???", "???", "???", "???",
 	"???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???",
@@ -1281,7 +1831,7 @@ static void dsp_opcode_add(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADD    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
-	UINT32 res = RN + RM;
+	uint32 res = RN + RM;
 	SET_ZNC_ADD(RN, RM, res);
 	RN = res;
 #ifdef DSP_DIS_ADD
@@ -1296,8 +1846,8 @@ static void dsp_opcode_addc(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADDC   R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
-	UINT32 res = RN + RM + dsp_flag_c;
-	UINT32 carry = dsp_flag_c;
+	uint32 res = RN + RM + dsp_flag_c;
+	uint32 carry = dsp_flag_c;
 //	SET_ZNC_ADD(RN, RM, res); //???BUG??? Yes!
 	SET_ZNC_ADD(RN + carry, RM, res);
 //	SET_ZNC_ADD(RN, RM + carry, res);
@@ -1314,8 +1864,8 @@ static void dsp_opcode_addq(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADDQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 r1 = dsp_convert_zero[IMM_1];
-	UINT32 res = RN + r1;
+	uint32 r1 = dsp_convert_zero[IMM_1];
+	uint32 res = RN + r1;
 	CLR_ZNC; SET_ZNC_ADD(RN, r1, res);
 	RN = res;
 #ifdef DSP_DIS_ADDQ
@@ -1330,7 +1880,7 @@ static void dsp_opcode_sub(void)
 	if (doDSPDis)
 		WriteLog("%06X: SUB    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
-	UINT32 res = RN - RM;
+	uint32 res = RN - RM;
 	SET_ZNC_SUB(RN, RM, res);
 	RN = res;
 #ifdef DSP_DIS_SUB
@@ -1345,8 +1895,8 @@ static void dsp_opcode_subc(void)
 	if (doDSPDis)
 		WriteLog("%06X: SUBC   R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
-	UINT32 res = RN - RM - dsp_flag_c;
-	UINT32 borrow = dsp_flag_c;
+	uint32 res = RN - RM - dsp_flag_c;
+	uint32 borrow = dsp_flag_c;
 	SET_ZNC_SUB(RN - borrow, RM, res);
 	RN = res;
 #ifdef DSP_DIS_SUBC
@@ -1361,8 +1911,8 @@ static void dsp_opcode_subq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SUBQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 r1 = dsp_convert_zero[IMM_1];
-	UINT32 res = RN - r1;
+	uint32 r1 = dsp_convert_zero[IMM_1];
+	uint32 res = RN - r1;
 	SET_ZNC_SUB(RN, r1, res);
 	RN = res;
 #ifdef DSP_DIS_SUBQ
@@ -1377,7 +1927,7 @@ static void dsp_opcode_cmp(void)
 	if (doDSPDis)
 		WriteLog("%06X: CMP    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
-	UINT32 res = RN - RM;
+	uint32 res = RN - RM;
 	SET_ZNC_SUB(RN, RM, res);
 #ifdef DSP_DIS_CMP
 	if (doDSPDis)
@@ -1393,8 +1943,8 @@ static void dsp_opcode_cmpq(void)
 	if (doDSPDis)
 		WriteLog("%06X: CMPQ   #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, sqtable[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3;
-	UINT32 res = RN - r1;
+	uint32 r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3;
+	uint32 res = RN - r1;
 	SET_ZNC_SUB(RN, r1, res);
 #ifdef DSP_DIS_CMPQ
 	if (doDSPDis)
@@ -1448,13 +1998,13 @@ static void dsp_opcode_not(void)
 {
 #ifdef DSP_DIS_NOT
 	if (doDSPDis)
-		WriteLog("%06X: NOT    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
+		WriteLog("%06X: NOT    R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
 	RN = ~RN;
 	SET_ZN(RN);
 #ifdef DSP_DIS_NOT
 	if (doDSPDis)
-		WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
+		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
 }
 
@@ -1469,7 +2019,11 @@ static void dsp_opcode_store_r14_indexed(void)
 	if (doDSPDis)
 		WriteLog("%06X: STORE  R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[14]+(dsp_convert_zero[IMM_1] << 2));
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	DSPWriteLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP);
+#else
 	DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[IMM_1] << 2), RN, DSP);
+#endif
 }
 
 static void dsp_opcode_store_r15_indexed(void)
@@ -1478,7 +2032,11 @@ static void dsp_opcode_store_r15_indexed(void)
 	if (doDSPDis)
 		WriteLog("%06X: STORE  R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[15]+(dsp_convert_zero[IMM_1] << 2));
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	DSPWriteLong((dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP);
+#else
 	DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[IMM_1] << 2), RN, DSP);
+#endif
 }
 
 static void dsp_opcode_load_r14_ri(void)
@@ -1487,7 +2045,11 @@ static void dsp_opcode_load_r14_ri(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM+dsp_reg[14], IMM_2, RN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	RN = DSPReadLong((dsp_reg[14] + RM) & 0xFFFFFFFC, DSP);
+#else
 	RN = DSPReadLong(dsp_reg[14] + RM, DSP);
+#endif
 #ifdef DSP_DIS_LOAD14R
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
@@ -1500,7 +2062,11 @@ static void dsp_opcode_load_r15_ri(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM+dsp_reg[15], IMM_2, RN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	RN = DSPReadLong((dsp_reg[15] + RM) & 0xFFFFFFFC, DSP);
+#else
 	RN = DSPReadLong(dsp_reg[15] + RM, DSP);
+#endif
 #ifdef DSP_DIS_LOAD15R
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
@@ -1543,10 +2109,17 @@ static void dsp_opcode_storew(void)
 	if (doDSPDis)
 		WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF))
+		DSPWriteLong(RM & 0xFFFFFFFE, RN & 0xFFFF, DSP);
+	else
+		JaguarWriteWord(RM & 0xFFFFFFFE, RN, DSP);
+#else
 	if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF))
 		DSPWriteLong(RM, RN & 0xFFFF, DSP);
 	else
 		JaguarWriteWord(RM, RN, DSP);
+#endif
 }
 
 static void dsp_opcode_store(void)
@@ -1555,7 +2128,11 @@ static void dsp_opcode_store(void)
 	if (doDSPDis)
 		WriteLog("%06X: STORE  R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	DSPWriteLong(RM & 0xFFFFFFFC, RN, DSP);
+#else
 	DSPWriteLong(RM, RN, DSP);
+#endif
 }
 
 static void dsp_opcode_loadb(void)
@@ -1580,10 +2157,17 @@ static void dsp_opcode_loadw(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOADW  (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF))
+		RN = DSPReadLong(RM & 0xFFFFFFFE, DSP) & 0xFFFF;
+	else
+		RN = JaguarReadWord(RM & 0xFFFFFFFE, DSP);
+#else
 	if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF))
 		RN = DSPReadLong(RM, DSP) & 0xFFFF;
 	else
 		RN = JaguarReadWord(RM, DSP);
+#endif
 #ifdef DSP_DIS_LOADW
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
@@ -1596,7 +2180,11 @@ static void dsp_opcode_load(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	RN = DSPReadLong(RM & 0xFFFFFFFC, DSP);
+#else
 	RN = DSPReadLong(RM, DSP);
+#endif
 #ifdef DSP_DIS_LOAD
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
@@ -1609,7 +2197,11 @@ static void dsp_opcode_load_r14_indexed(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1] << 2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[IMM_1] << 2, dsp_reg[14]+(dsp_convert_zero[IMM_1] << 2), IMM_2, RN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	RN = DSPReadLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), DSP);
+#else
 	RN = DSPReadLong(dsp_reg[14] + (dsp_convert_zero[IMM_1] << 2), DSP);
+#endif
 #ifdef DSP_DIS_LOAD14I
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
@@ -1622,7 +2214,11 @@ static void dsp_opcode_load_r15_indexed(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1] << 2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[IMM_1] << 2, dsp_reg[15]+(dsp_convert_zero[IMM_1] << 2), IMM_2, RN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	RN = DSPReadLong((dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), DSP);
+#else
 	RN = DSPReadLong(dsp_reg[15] + (dsp_convert_zero[IMM_1] << 2), DSP);
+#endif
 #ifdef DSP_DIS_LOAD15I
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
@@ -1743,7 +2339,7 @@ static void dsp_opcode_bclr(void)
 	if (doDSPDis)
 		WriteLog("%06X: BCLR   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 res = RN & ~(1 << IMM_1);
+	uint32 res = RN & ~(1 << IMM_1);
 	RN = res;
 	SET_ZN(res);
 #ifdef DSP_DIS_BCLR
@@ -1771,7 +2367,7 @@ static void dsp_opcode_bset(void)
 	if (doDSPDis)
 		WriteLog("%06X: BSET   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 res = RN | (1 << IMM_1);
+	uint32 res = RN | (1 << IMM_1);
 	RN = res;
 	SET_ZN(res);
 #ifdef DSP_DIS_BSET
@@ -1819,11 +2415,11 @@ static void dsp_opcode_imacn(void)
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8)(dsp_acc >> 32), (uint32)(dsp_acc & 0xFFFFFFFF));
 #endif
-} 
+}
 
 static void dsp_opcode_mtoi(void)
 {
-	RN = (((INT32)RM >> 8) & 0xFF800000) | (RM & 0x007FFFFF);
+	RN = (((int32)RM >> 8) & 0xFF800000) | (RM & 0x007FFFFF);
 	SET_ZN(RN);
 }
 
@@ -1852,14 +2448,14 @@ static void dsp_opcode_normi(void)
 static void dsp_opcode_mmult(void)
 {
 	int count	= dsp_matrix_control&0x0f;
-	uint32 addr = dsp_pointer_to_matrix; // in the gpu ram
+	uint32 addr = dsp_pointer_to_matrix; // in the dsp ram
 	int64 accum = 0;
 	uint32 res;
 
 	if (!(dsp_matrix_control & 0x10))
 	{
 		for (int i = 0; i < count; i++)
-		{ 
+		{
 			int16 a;
 			if (i&0x01)
 				a=(int16)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff);
@@ -1892,9 +2488,13 @@ static void dsp_opcode_mmult(void)
 
 static void dsp_opcode_abs(void)
 {
+#ifdef DSP_DIS_ABS
+	if (doDSPDis)
+		WriteLog("%06X: ABS    R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
+#endif
 	uint32 _Rn = RN;
 	uint32 res;
-	
+
 	if (_Rn == 0x80000000)
 		dsp_flag_n = 1;
 	else
@@ -1903,6 +2503,10 @@ static void dsp_opcode_abs(void)
 		res = RN = (_Rn & 0x80000000 ? -_Rn : _Rn);
 		CLR_ZN; SET_Z(res);
 	}
+#ifdef DSP_DIS_ABS
+	if (doDSPDis)
+		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
+#endif
 }
 
 static void dsp_opcode_div(void)
@@ -1953,7 +2557,7 @@ static void dsp_opcode_neg(void)
 	if (doDSPDis)
 		WriteLog("%06X: NEG    R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 res = -RN;
+	uint32 res = -RN;
 	SET_ZNC_SUB(0, RN, res);
 	RN = res;
 #ifdef DSP_DIS_NEG
@@ -1968,8 +2572,8 @@ static void dsp_opcode_shlq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SHLQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, 32 - IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	INT32 r1 = 32 - IMM_1;
-	UINT32 res = RN << r1;
+	int32 r1 = 32 - IMM_1;
+	uint32 res = RN << r1;
 	SET_ZN(res); dsp_flag_c = (RN >> 31) & 1;
 	RN = res;
 #ifdef DSP_DIS_SHLQ
@@ -1984,8 +2588,8 @@ static void dsp_opcode_shrq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SHRQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	INT32 r1 = dsp_convert_zero[IMM_1];
-	UINT32 res = RN >> r1;
+	int32 r1 = dsp_convert_zero[IMM_1];
+	uint32 res = RN >> r1;
 	SET_ZN(res); dsp_flag_c = RN & 1;
 	RN = res;
 #ifdef DSP_DIS_SHRQ
@@ -2000,8 +2604,8 @@ static void dsp_opcode_ror(void)
 	if (doDSPDis)
 		WriteLog("%06X: ROR    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN);
 #endif
-	UINT32 r1 = RM & 0x1F;
-	UINT32 res = (RN >> r1) | (RN << (32 - r1));
+	uint32 r1 = RM & 0x1F;
+	uint32 res = (RN >> r1) | (RN << (32 - r1));
 	SET_ZN(res); dsp_flag_c = (RN >> 31) & 1;
 	RN = res;
 #ifdef DSP_DIS_ROR
@@ -2016,9 +2620,9 @@ static void dsp_opcode_rorq(void)
 	if (doDSPDis)
 		WriteLog("%06X: RORQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 r1 = dsp_convert_zero[IMM_1 & 0x1F];
-	UINT32 r2 = RN;
-	UINT32 res = (r2 >> r1) | (r2 << (32 - r1));
+	uint32 r1 = dsp_convert_zero[IMM_1 & 0x1F];
+	uint32 r2 = RN;
+	uint32 res = (r2 >> r1) | (r2 << (32 - r1));
 	RN = res;
 	SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01;
 #ifdef DSP_DIS_RORQ
@@ -2064,7 +2668,7 @@ static void dsp_opcode_sharq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SHARQ  #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN);
 #endif
-	UINT32 res = (INT32)RN >> dsp_convert_zero[IMM_1];
+	uint32 res = (int32)RN >> dsp_convert_zero[IMM_1];
 	SET_ZN(res); dsp_flag_c = RN & 0x01;
 	RN = res;
 #ifdef DSP_DIS_SHARQ
@@ -2110,9 +2714,9 @@ void dsp_opcode_addqmod(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADDQMOD #%u, R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_MOD=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_modulo);
 #endif
-	UINT32 r1 = dsp_convert_zero[IMM_1];
-	UINT32 r2 = RN;
-	UINT32 res = r2 + r1;
+	uint32 r1 = dsp_convert_zero[IMM_1];
+	uint32 r2 = RN;
+	uint32 res = r2 + r1;
 	res = (res & (~dsp_modulo)) | (r2 & dsp_modulo);
 	RN = res;
 	SET_ZNC_ADD(r2, r1, res);
@@ -2122,37 +2726,37 @@ void dsp_opcode_addqmod(void)
 #endif
 }
 
-void dsp_opcode_subqmod(void)	
+void dsp_opcode_subqmod(void)
 {
-	UINT32 r1 = dsp_convert_zero[IMM_1];
-	UINT32 r2 = RN;
-	UINT32 res = r2 - r1;
+	uint32 r1 = dsp_convert_zero[IMM_1];
+	uint32 r2 = RN;
+	uint32 res = r2 - r1;
 	res = (res & (~dsp_modulo)) | (r2 & dsp_modulo);
 	RN = res;
-	
+
 	SET_ZNC_SUB(r2, r1, res);
 }
 
-void dsp_opcode_mirror(void)	
+void dsp_opcode_mirror(void)
 {
-	UINT32 r1 = RN;
+	uint32 r1 = RN;
 	RN = (mirror_table[r1 & 0xFFFF] << 16) | mirror_table[r1 >> 16];
 	SET_ZN(RN);
 }
 
-void dsp_opcode_sat32s(void)		
+void dsp_opcode_sat32s(void)
 {
-	INT32 r2 = (UINT32)RN;
-	INT32 temp = dsp_acc >> 32;
-	UINT32 res = (temp < -1) ? (INT32)0x80000000 : (temp > 0) ? (INT32)0x7FFFFFFF : r2;
+	int32 r2 = (uint32)RN;
+	int32 temp = dsp_acc >> 32;
+	uint32 res = (temp < -1) ? (int32)0x80000000 : (temp > 0) ? (int32)0x7FFFFFFF : r2;
 	RN = res;
 	SET_ZN(res);
 }
 
-void dsp_opcode_sat16s(void)		
+void dsp_opcode_sat16s(void)
 {
-	INT32 r2 = RN;
-	UINT32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2;
+	int32 r2 = RN;
+	uint32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2;
 	RN = res;
 	SET_ZN(res);
 }
@@ -2165,7 +2769,7 @@ static void DSP_abs(void);
 static void DSP_add(void);
 static void DSP_addc(void);
 static void DSP_addq(void);
-static void DSP_addqmod(void);	
+static void DSP_addqmod(void);
 static void DSP_addqt(void);
 static void DSP_and(void);
 static void DSP_bclr(void);
@@ -2187,7 +2791,7 @@ static void DSP_load_r14_i(void);
 static void DSP_load_r14_r(void);
 static void DSP_load_r15_i(void);
 static void DSP_load_r15_r(void);
-static void DSP_mirror(void);	
+static void DSP_mirror(void);
 static void DSP_mmult(void);
 static void DSP_move(void);
 static void DSP_movefa(void);
@@ -2205,8 +2809,8 @@ static void DSP_or(void);
 static void DSP_resmac(void);
 static void DSP_ror(void);
 static void DSP_rorq(void);
-static void DSP_sat16s(void);	
-static void DSP_sat32s(void);	
+static void DSP_sat16s(void);
+static void DSP_sat32s(void);
 static void DSP_sh(void);
 static void DSP_sha(void);
 static void DSP_sharq(void);
@@ -2222,7 +2826,7 @@ static void DSP_store_r15_r(void);
 static void DSP_sub(void);
 static void DSP_subc(void);
 static void DSP_subq(void);
-static void DSP_subqmod(void);	
+static void DSP_subqmod(void);
 static void DSP_subqt(void);
 static void DSP_xor(void);
 
@@ -2272,6 +2876,21 @@ bool readAffected[64][2] =
 	{ true,  true}, { true,  true}, {false, false}, {false,  true}
 };
 
+bool isLoadStore[65] =
+{
+	false, false, false, false, false, false, false, false,
+	false, false, false, false, false, false, false, false,
+
+	false, false, false, false, false, false, false, false,
+	false, false, false, false, false, false, false, false,
+
+	false, false, false, false, false, false, false,  true,
+	 true,  true, false,  true,  true,  true,  true,  true,
+
+	false,  true,  true, false, false, false, false, false,
+	false, false,  true,  true,  true,  true, false, false, false
+};
+
 void FlushDSPPipeline(void)
 {
 	plPtrFetch = 3, plPtrRead = 2, plPtrExec = 1, plPtrWrite = 0;
@@ -2280,7 +2899,7 @@ void FlushDSPPipeline(void)
 		pipeline[i].opcode = PIPELINE_STALL;
 
 	for(int i=0; i<32; i++)
-		scoreboard[i] = false;
+		scoreboard[i] = 0;
 }
 
 //
@@ -2447,7 +3066,7 @@ because the STORE instruction writes back on stage #2 of the pipeline instead of
 If it were done properly, the STORE write back would occur *after* (well, technically,
 during) the execution of the the JUMP that follows it.
 
-!!! FIX !!!
+!!! FIX !!! [DONE]
 
 F1B08A: JR     z, F1B082 [NCZ:001] Branched!
 F1B08A: NOP    [NCZ:001]
@@ -2547,8 +3166,9 @@ F1B016: NOP    [NCZ:001]
 F1B1FC: MOVEI  #$00F1A100, R01 [NCZ:001, R01=00F1A100] -> [NCZ:001, R01=00F1A100]
 */
 
-
-//#define DSP_DEBUG_PL2
+uint32 pcQueue1[0x400];
+uint32 pcQPtr1 = 0;
+static uint32 prevR1;
 //Let's try a 3 stage pipeline....
 //Looks like 3 stage is correct, otherwise bad things happen...
 void DSPExecP2(int32 cycles)
@@ -2558,6 +3178,54 @@ void DSPExecP2(int32 cycles)
 
 	while (cycles > 0 && DSP_RUNNING)
 	{
+/*extern uint32 totalFrames;
+//F1B2F6: LOAD   (R14+$04), R24 [NCZ:001, R14+$04=00F20018, R24=FFFFFFFF] -> Jaguar: Unknown word read at 00F20018 by DSP (M68K PC=00E32E)
+//-> 43 + 1 + 24 -> $2B + $01 + $18 -> 101011 00001 11000 -> 1010 1100 0011 1000 -> AC38
+//C470 -> 1100 0100 0111 0000 -> 110001 00011 10000 -> 49, 3, 16 -> STORE R16, (R14+$0C)
+//F1B140:
+if (totalFrames >= 377 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38 && dsp_pc == 0xF1B140)
+{
+	doDSPDis = true;
+	WriteLog("Starting disassembly at frame #%u...\n", totalFrames);
+}
+if (dsp_pc == 0xF1B092)
+	doDSPDis = false;//*/
+/*if (totalFrames >= 373 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38)
+	doDSPDis = true;//*/
+/*if (totalFrames >= 373 && dsp_pc == 0xF1B0A0)
+	doDSPDis = true;//*/
+/*if (dsp_pc == 0xF1B0A0)
+	doDSPDis = true;//*/
+/*if (dsp_pc == 0xF1B0D2) && dsp_reg[1] == 0x2140C)
+	doDSPDis = true;//*/
+//Two parter... (not sure how to write this)
+//if (dsp_pc == 0xF1B0D2)
+//	prevR1 = dsp_reg[1];
+
+//F1B0D2: ADDQT  #8, R01 [NCZ:000, R01=0002140C] -> [NCZ:000, R01=00021414]
+//F1B0D2: ADDQT  #8, R01 [NCZ:000, R01=0002140C] -> [NCZ:000, R01=00021414]
+
+
+pcQueue1[pcQPtr1++] = dsp_pc;
+pcQPtr1 &= 0x3FF;
+
+#ifdef DSP_DEBUG_PL2
+if ((dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFF) && !doDSPDis)
+{
+	WriteLog("DSP: PC has stepped out of bounds...\n\nBacktrace:\n\n");
+	doDSPDis = true;
+
+	char buffer[512];
+
+	for(int i=0; i<0x400; i++)
+	{
+		dasmjag(JAGUAR_DSP, buffer, pcQueue1[(i + pcQPtr1) & 0x3FF]);
+		WriteLog("\t%08X: %s\n", pcQueue1[(i + pcQPtr1) & 0x3FF], buffer);
+	}
+	WriteLog("\n");
+}//*/
+#endif
+
 		if (IMASKCleared)						// If IMASK was cleared,
 		{
 #ifdef DSP_DEBUG_IRQ
@@ -2570,6 +3238,8 @@ void DSPExecP2(int32 cycles)
 //if (dsp_flags & REGPAGE)
 //	WriteLog("  --> REGPAGE has just been set!\n");
 #ifdef DSP_DEBUG_PL2
+if (doDSPDis)
+{
 WriteLog("DSPExecP: Pipeline status [PC=%08X]...\n", dsp_pc);
 WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]);
 WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]);
@@ -2578,6 +3248,7 @@ WriteLog("  --> Scoreboard: ");
 for(int i=0; i<32; i++)
 	WriteLog("%s ", scoreboard[i] ? "T" : "F");
 WriteLog("\n");
+}
 #endif
 		// Stage 1a: Instruction fetch
 		pipeline[plPtrRead].instruction = DSPReadWord(dsp_pc, DSP);
@@ -2588,29 +3259,40 @@ WriteLog("\n");
 			pipeline[plPtrRead].result = (uint32)DSPReadWord(dsp_pc + 2, DSP)
 				| ((uint32)DSPReadWord(dsp_pc + 4, DSP) << 16);
 #ifdef DSP_DEBUG_PL2
+if (doDSPDis)
+{
 WriteLog("DSPExecP: Fetching instruction (%04X) from DSP_PC = %08X...\n", pipeline[plPtrRead].instruction, dsp_pc);
 WriteLog("DSPExecP: Pipeline status (after stage 1a) [PC=%08X]...\n", dsp_pc);
 WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]);
 WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]);
 WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]);
+}
 #endif
 		// Stage 1b: Read registers
 //Small problem--when say LOAD or STORE (R14/5+$nn) is executed AFTER an instruction that
 //modifies R14/5, we don't check the scoreboard for R14/5 (and we need to!)... !!! FIX !!!
 //Ugly, but [DONE]
+//Another problem: Any sequential combination of LOAD and STORE operations will cause the
+//pipeline to stall, and we don't take care of that here. !!! FIX !!!
 		if ((scoreboard[pipeline[plPtrRead].operand1] && readAffected[pipeline[plPtrRead].opcode][0])
 			|| (scoreboard[pipeline[plPtrRead].operand2] && readAffected[pipeline[plPtrRead].opcode][1])
 			|| ((pipeline[plPtrRead].opcode == 43 || pipeline[plPtrRead].opcode == 58) && scoreboard[14])
-			|| ((pipeline[plPtrRead].opcode == 44 || pipeline[plPtrRead].opcode == 59) && scoreboard[15]))
+			|| ((pipeline[plPtrRead].opcode == 44 || pipeline[plPtrRead].opcode == 59) && scoreboard[15])
+//Not sure that this is the best way to fix the LOAD/STORE problem... But it seems to
+//work--somewhat...
+			|| (isLoadStore[pipeline[plPtrRead].opcode] && isLoadStore[pipeline[plPtrExec].opcode]))
 			// We have a hit in the scoreboard, so we have to stall the pipeline...
 #ifdef DSP_DEBUG_PL2
 {
+if (doDSPDis)
+{
 WriteLog("  --> Stalling pipeline: ");
 if (readAffected[pipeline[plPtrRead].opcode][0])
 	WriteLog("scoreboard[%u] = %s (reg 1) ", pipeline[plPtrRead].operand1, scoreboard[pipeline[plPtrRead].operand1] ? "true" : "false");
 if (readAffected[pipeline[plPtrRead].opcode][1])
 	WriteLog("scoreboard[%u] = %s (reg 2)", pipeline[plPtrRead].operand2, scoreboard[pipeline[plPtrRead].operand2] ? "true" : "false");
 WriteLog("\n");
+}
 #endif
 			pipeline[plPtrRead].opcode = PIPELINE_STALL;
 #ifdef DSP_DEBUG_PL2
@@ -2624,47 +3306,84 @@ WriteLog("\n");
 
 			// Shouldn't we be more selective with the register scoreboarding?
 			// Yes, we should. !!! FIX !!! Kinda [DONE]
+#ifndef NEW_SCOREBOARD
 			scoreboard[pipeline[plPtrRead].operand2] = affectsScoreboard[pipeline[plPtrRead].opcode];
+#else
+//Hopefully this will fix the dual MOVEQ # problem...
+			scoreboard[pipeline[plPtrRead].operand2] += (affectsScoreboard[pipeline[plPtrRead].opcode] ? 1 : 0);
+#endif
 
 //Advance PC here??? Yes.
 			dsp_pc += (pipeline[plPtrRead].opcode == 38 ? 6 : 2);
 		}
 
 #ifdef DSP_DEBUG_PL2
+if (doDSPDis)
+{
 WriteLog("DSPExecP: Pipeline status (after stage 1b) [PC=%08X]...\n", dsp_pc);
 WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]);
 WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]);
 WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]);
+}
 #endif
 		// Stage 2: Execute
 		if (pipeline[plPtrExec].opcode != PIPELINE_STALL)
 		{
 #ifdef DSP_DEBUG_PL2
+if (doDSPDis)
+	WriteLog("\t[inst=%02u][R28=%08X, alt R28=%08X, REGPAGE=%s]\n", pipeline[plPtrExec].opcode, dsp_reg[28], dsp_alternate_reg[28], (dsp_flags & REGPAGE ? "set" : "not set"));
+
+if (doDSPDis)
+{
 WriteLog("DSPExecP: About to execute opcode %s...\n", dsp_opcode_str[pipeline[plPtrExec].opcode]);
+}
+#endif
+//CC only!
+#ifdef DSP_DEBUG_CC
+lastExec = pipeline[plPtrExec].instruction;
+//WriteLog("[lastExec = %04X]\n", lastExec);
 #endif
+			cycles -= dsp_opcode_cycles[pipeline[plPtrExec].opcode];
+			dsp_opcode_use[pipeline[plPtrExec].opcode]++;
 			DSPOpcode[pipeline[plPtrExec].opcode]();
 //WriteLog("    --> Returned from execute. DSP_PC: %08X\n", dsp_pc);
-			dsp_opcode_use[pipeline[plPtrExec].opcode]++;
-			cycles -= dsp_opcode_cycles[pipeline[plPtrExec].opcode];
 		}
 		else
 {
-			cycles--;
+//Let's not, until we do the stalling correctly...
+//But, we gotta while we're doing the comparison core...!
+//Or do we?			cycles--;
+//Really, the whole thing is wrong. When the pipeline is correctly stuffed, most instructions
+//will execute in one clock cycle (others, like DIV, will likely not). So, the challenge is
+//to model this clock cycle behavior correctly...
+//Also, the pipeline stalls too much--mostly because the transparent writebacks at stage 3
+//don't affect the reads at stage 1...
 #ifdef DSP_DEBUG_STALL
-WriteLog("[STALL...]\n");
+if (doDSPDis)
+	WriteLog("[STALL... DSP_PC = %08X]\n", dsp_pc);
 #endif
 }
 
 #ifdef DSP_DEBUG_PL2
+if (doDSPDis)
+{
 WriteLog("DSPExecP: Pipeline status (after stage 2) [PC=%08X]...\n", dsp_pc);
 WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]);
 WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]);
 WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]);
 WriteLog("\n");
+}
 #endif
 		// Stage 3: Write back register/memory address
 		if (pipeline[plPtrWrite].opcode != PIPELINE_STALL)
 		{
+/*if (pipeline[plPtrWrite].writebackRegister == 3
+	&& (pipeline[plPtrWrite].result < 0xF14000 || pipeline[plPtrWrite].result > 0xF1CFFF)
+	&& !doDSPDis)
+{
+	WriteLog("DSP: Register R03 has stepped out of bounds...\n\n");
+	doDSPDis = true;
+}//*/
 			if (pipeline[plPtrWrite].writebackRegister != 0xFF)
 			{
 				if (pipeline[plPtrWrite].writebackRegister != 0xFE)
@@ -2680,8 +3399,15 @@ WriteLog("\n");
 				}
 			}
 
+#ifndef NEW_SCOREBOARD
 			if (affectsScoreboard[pipeline[plPtrWrite].opcode])
 				scoreboard[pipeline[plPtrWrite].operand2] = false;
+#else
+//Yup, sequential MOVEQ # problem fixing (I hope!)...
+			if (affectsScoreboard[pipeline[plPtrWrite].opcode])
+				if (scoreboard[pipeline[plPtrWrite].operand2])
+					scoreboard[pipeline[plPtrWrite].operand2]--;
+#endif
 		}
 
 		// Push instructions through the pipeline...
@@ -2822,10 +3548,10 @@ static void DSP_abs(void)
 {
 #ifdef DSP_DIS_ABS
 	if (doDSPDis)
-		WriteLog("%06X: ABS    R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
+		WriteLog("%06X: ABS    R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
 	uint32 _Rn = PRN;
-	
+
 	if (_Rn == 0x80000000)
 		dsp_flag_n = 1;
 	else
@@ -2846,7 +3572,7 @@ static void DSP_add(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADD    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
-	UINT32 res = PRN + PRM;
+	uint32 res = PRN + PRM;
 	SET_ZNC_ADD(PRN, PRM, res);
 	PRES = res;
 #ifdef DSP_DIS_ADD
@@ -2861,8 +3587,8 @@ static void DSP_addc(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADDC   R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
-	UINT32 res = PRN + PRM + dsp_flag_c;
-	UINT32 carry = dsp_flag_c;
+	uint32 res = PRN + PRM + dsp_flag_c;
+	uint32 carry = dsp_flag_c;
 //	SET_ZNC_ADD(PRN, PRM, res); //???BUG??? Yes!
 	SET_ZNC_ADD(PRN + carry, PRM, res);
 //	SET_ZNC_ADD(PRN, PRM + carry, res);
@@ -2879,8 +3605,8 @@ static void DSP_addq(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADDQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	UINT32 r1 = dsp_convert_zero[PIMM1];
-	UINT32 res = PRN + r1;
+	uint32 r1 = dsp_convert_zero[PIMM1];
+	uint32 res = PRN + r1;
 	CLR_ZNC; SET_ZNC_ADD(PRN, r1, res);
 	PRES = res;
 #ifdef DSP_DIS_ADDQ
@@ -2895,9 +3621,9 @@ static void DSP_addqmod(void)
 	if (doDSPDis)
 		WriteLog("%06X: ADDQMOD #%u, R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_MOD=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_modulo);
 #endif
-	UINT32 r1 = dsp_convert_zero[PIMM1];
-	UINT32 r2 = PRN;
-	UINT32 res = r2 + r1;
+	uint32 r1 = dsp_convert_zero[PIMM1];
+	uint32 r2 = PRN;
+	uint32 res = r2 + r1;
 	res = (res & (~dsp_modulo)) | (r2 & dsp_modulo);
 	PRES = res;
 	SET_ZNC_ADD(r2, r1, res);
@@ -2972,7 +3698,7 @@ static void DSP_btst(void)
 	NO_WRITEBACK;
 #ifdef DSP_DIS_BTST
 	if (doDSPDis)
-		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
+		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
 }
 
@@ -2982,7 +3708,7 @@ static void DSP_cmp(void)
 	if (doDSPDis)
 		WriteLog("%06X: CMP    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
-	UINT32 res = PRN - PRM;
+	uint32 res = PRN - PRM;
 	SET_ZNC_SUB(PRN, PRM, res);
 	NO_WRITEBACK;
 #ifdef DSP_DIS_CMP
@@ -2999,8 +3725,8 @@ static void DSP_cmpq(void)
 	if (doDSPDis)
 		WriteLog("%06X: CMPQ   #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, sqtable[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	UINT32 r1 = sqtable[PIMM1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3;
-	UINT32 res = PRN - r1;
+	uint32 r1 = sqtable[PIMM1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3;
+	uint32 res = PRN - r1;
 	SET_ZNC_SUB(PRN, r1, res);
 	NO_WRITEBACK;
 #ifdef DSP_DIS_CMPQ
@@ -3048,7 +3774,7 @@ static void DSP_imacn(void)
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8)(dsp_acc >> 32), (uint32)(dsp_acc & 0xFFFFFFFF));
 #endif
-} 
+}
 
 static void DSP_imult(void)
 {
@@ -3098,13 +3824,14 @@ static void DSP_illegal(void)
 static void DSP_jr(void)
 {
 #ifdef DSP_DIS_JR
-char * condition[32] =
+const char * condition[32] =
 {	"T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz",
 	"c z", "???", "???", "???", "???", "???", "???", "???", "???",
 	"???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???",
 	"???", "???", "???", "F" };
 	if (doDSPDis)
-		WriteLog("%06X: JR     %s, %06X [NCZ:%u%u%u] ", DSP_PPC, condition[PIMM2], dsp_pc+((PIMM1 & 0x10 ? 0xFFFFFFF0 | PIMM1 : PIMM1) * 2), dsp_flag_n, dsp_flag_c, dsp_flag_z);
+//How come this is always off by 2???
+		WriteLog("%06X: JR     %s, %06X [NCZ:%u%u%u] ", DSP_PPC, condition[PIMM2], DSP_PPC+((PIMM1 & 0x10 ? 0xFFFFFFF0 | PIMM1 : PIMM1) * 2)+2, dsp_flag_n, dsp_flag_c, dsp_flag_z);
 #endif
 	// KLUDGE: Used by BRANCH_CONDITION macro
 	uint32 jaguar_flags = (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z;
@@ -3123,7 +3850,7 @@ char * condition[32] =
 		// Now that we've branched, we have to make sure that the following instruction
 		// is executed atomically with this one and then flush the pipeline before setting
 		// the new PC.
-		
+
 		// Step 1: Handle writebacks at stage 3 of pipeline
 /*		if (pipeline[plPtrWrite].opcode != PIPELINE_STALL)
 		{
@@ -3150,8 +3877,15 @@ char * condition[32] =
 				}
 			}
 
+#ifndef NEW_SCOREBOARD
 			if (affectsScoreboard[pipeline[plPtrWrite].opcode])
 				scoreboard[pipeline[plPtrWrite].operand2] = false;
+#else
+//Yup, sequential MOVEQ # problem fixing (I hope!)...
+			if (affectsScoreboard[pipeline[plPtrWrite].opcode])
+				if (scoreboard[pipeline[plPtrWrite].operand2])
+					scoreboard[pipeline[plPtrWrite].operand2]--;
+#endif
 		}
 
 		// Step 2: Push instruction through pipeline & execute following instruction
@@ -3175,6 +3909,7 @@ char * condition[32] =
 			pipeline[plPtrExec].reg2 = dsp_reg[pipeline[plPtrExec].operand2];
 			pipeline[plPtrExec].writebackRegister = pipeline[plPtrExec].operand2;	// Set it to RN
 		}//*/
+	dsp_pc += 2;	// For DSP_DIS_* accuracy
 		DSPOpcode[pipeline[plPtrExec].opcode]();
 		dsp_opcode_use[pipeline[plPtrExec].opcode]++;
 		pipeline[plPtrWrite] = pipeline[plPtrExec];
@@ -3199,7 +3934,7 @@ char * condition[32] =
 static void DSP_jump(void)
 {
 #ifdef DSP_DIS_JUMP
-char * condition[32] =
+const char * condition[32] =
 {	"T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz",
 	"c z", "???", "???", "???", "???", "???", "???", "???", "???",
 	"???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???",
@@ -3220,7 +3955,7 @@ char * condition[32] =
 		// Now that we've branched, we have to make sure that the following instruction
 		// is executed atomically with this one and then flush the pipeline before setting
 		// the new PC.
-		
+
 		// Step 1: Handle writebacks at stage 3 of pipeline
 /*		if (pipeline[plPtrWrite].opcode != PIPELINE_STALL)
 		{
@@ -3247,8 +3982,15 @@ char * condition[32] =
 				}
 			}
 
+#ifndef NEW_SCOREBOARD
 			if (affectsScoreboard[pipeline[plPtrWrite].opcode])
 				scoreboard[pipeline[plPtrWrite].operand2] = false;
+#else
+//Yup, sequential MOVEQ # problem fixing (I hope!)...
+			if (affectsScoreboard[pipeline[plPtrWrite].opcode])
+				if (scoreboard[pipeline[plPtrWrite].operand2])
+					scoreboard[pipeline[plPtrWrite].operand2]--;
+#endif
 		}
 
 		// Step 2: Push instruction through pipeline & execute following instruction
@@ -3273,6 +4015,7 @@ char * condition[32] =
 			pipeline[plPtrExec].reg2 = dsp_reg[pipeline[plPtrExec].operand2];
 			pipeline[plPtrExec].writebackRegister = pipeline[plPtrExec].operand2;	// Set it to RN
 		}//*/
+	dsp_pc += 2;	// For DSP_DIS_* accuracy
 		DSPOpcode[pipeline[plPtrExec].opcode]();
 		dsp_opcode_use[pipeline[plPtrExec].opcode]++;
 		pipeline[plPtrWrite] = pipeline[plPtrExec];
@@ -3299,7 +4042,11 @@ static void DSP_load(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	PRES = DSPReadLong(PRM & 0xFFFFFFFC, DSP);
+#else
 	PRES = DSPReadLong(PRM, DSP);
+#endif
 #ifdef DSP_DIS_LOAD
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
@@ -3328,10 +4075,17 @@ static void DSP_loadw(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOADW  (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF))
+		PRES = DSPReadLong(PRM & 0xFFFFFFFE, DSP) & 0xFFFF;
+	else
+		PRES = JaguarReadWord(PRM & 0xFFFFFFFE, DSP);
+#else
 	if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF))
 		PRES = DSPReadLong(PRM, DSP) & 0xFFFF;
 	else
 		PRES = JaguarReadWord(PRM, DSP);
+#endif
 #ifdef DSP_DIS_LOADW
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
@@ -3344,7 +4098,11 @@ static void DSP_load_r14_i(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[14]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	PRES = DSPReadLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2), DSP);
+#else
 	PRES = DSPReadLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), DSP);
+#endif
 #ifdef DSP_DIS_LOAD14I
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
@@ -3357,7 +4115,11 @@ static void DSP_load_r14_r(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[14], PIMM2, PRES);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	PRES = DSPReadLong((dsp_reg[14] + PRM) & 0xFFFFFFFC, DSP);
+#else
 	PRES = DSPReadLong(dsp_reg[14] + PRM, DSP);
+#endif
 #ifdef DSP_DIS_LOAD14R
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
@@ -3370,7 +4132,11 @@ static void DSP_load_r15_i(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[15]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	PRES = DSPReadLong((dsp_reg[15] &0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2), DSP);
+#else
 	PRES = DSPReadLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), DSP);
+#endif
 #ifdef DSP_DIS_LOAD15I
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
@@ -3383,16 +4149,20 @@ static void DSP_load_r15_r(void)
 	if (doDSPDis)
 		WriteLog("%06X: LOAD   (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[15], PIMM2, PRN);
 #endif
+#ifdef DSP_CORRECT_ALIGNMENT
+	PRES = DSPReadLong((dsp_reg[15] + PRM) & 0xFFFFFFFC, DSP);
+#else
 	PRES = DSPReadLong(dsp_reg[15] + PRM, DSP);
+#endif
 #ifdef DSP_DIS_LOAD15R
 	if (doDSPDis)
 		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
 #endif
 }
 
-static void DSP_mirror(void)	
+static void DSP_mirror(void)
 {
-	UINT32 r1 = PRN;
+	uint32 r1 = PRN;
 	PRES = (mirror_table[r1 & 0xFFFF] << 16) | mirror_table[r1 >> 16];
 	SET_ZN(PRES);
 }
@@ -3400,14 +4170,14 @@ static void DSP_mirror(void)
 static void DSP_mmult(void)
 {
 	int count	= dsp_matrix_control&0x0f;
-	uint32 addr = dsp_pointer_to_matrix; // in the gpu ram
+	uint32 addr = dsp_pointer_to_matrix; // in the dsp ram
 	int64 accum = 0;
 	uint32 res;
 
 	if (!(dsp_matrix_control & 0x10))
 	{
 		for (int i = 0; i < count; i++)
-		{ 
+		{
 			int16 a;
 			if (i&0x01)
 				a=(int16)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff);
@@ -3485,8 +4255,18 @@ static void DSP_movei(void)
 
 static void DSP_movepc(void)
 {
-//Need to fix this to take into account pipelining effects... !!! FIX !!!
-	PRES = dsp_pc - 2;
+#ifdef DSP_DIS_MOVEPC
+	if (doDSPDis)
+		WriteLog("%06X: MOVE   PC, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
+#endif
+//Need to fix this to take into account pipelining effects... !!! FIX !!! [DONE]
+//	PRES = dsp_pc - 2;
+//Account for pipeline effects...
+	PRES = dsp_pc - 2 - (pipeline[plPtrRead].opcode == 38 ? 6 : (pipeline[plPtrRead].opcode == PIPELINE_STALL ? 0 : 2));
+#ifdef DSP_DIS_MOVEPC
+	if (doDSPDis)
+		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
+#endif
 }
 
 static void DSP_moveq(void)
@@ -3521,7 +4301,7 @@ static void DSP_moveta(void)
 
 static void DSP_mtoi(void)
 {
-	PRES = (((INT32)PRM >> 8) & 0xFF800000) | (PRM & 0x007FFFFF);
+	PRES = (((int32)PRM >> 8) & 0xFF800000) | (PRM & 0x007FFFFF);
 	SET_ZN(PRES);
 }
 
@@ -3545,7 +4325,7 @@ static void DSP_neg(void)
 	if (doDSPDis)
 		WriteLog("%06X: NEG    R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	UINT32 res = -PRN;
+	uint32 res = -PRN;
 	SET_ZNC_SUB(0, PRN, res);
 	PRES = res;
 #ifdef DSP_DIS_NEG
@@ -3589,13 +4369,13 @@ static void DSP_not(void)
 {
 #ifdef DSP_DIS_NOT
 	if (doDSPDis)
-		WriteLog("%06X: NOT    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
+		WriteLog("%06X: NOT    R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
 	PRES = ~PRN;
 	SET_ZN(PRES);
 #ifdef DSP_DIS_NOT
 	if (doDSPDis)
-		WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES);
+		WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES);
 #endif
 }
 
@@ -3632,8 +4412,8 @@ static void DSP_ror(void)
 	if (doDSPDis)
 		WriteLog("%06X: ROR    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
-	UINT32 r1 = PRM & 0x1F;
-	UINT32 res = (PRN >> r1) | (PRN << (32 - r1));
+	uint32 r1 = PRM & 0x1F;
+	uint32 res = (PRN >> r1) | (PRN << (32 - r1));
 	SET_ZN(res); dsp_flag_c = (PRN >> 31) & 1;
 	PRES = res;
 #ifdef DSP_DIS_ROR
@@ -3648,9 +4428,9 @@ static void DSP_rorq(void)
 	if (doDSPDis)
 		WriteLog("%06X: RORQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	UINT32 r1 = dsp_convert_zero[PIMM1 & 0x1F];
-	UINT32 r2 = PRN;
-	UINT32 res = (r2 >> r1) | (r2 << (32 - r1));
+	uint32 r1 = dsp_convert_zero[PIMM1 & 0x1F];
+	uint32 r2 = PRN;
+	uint32 res = (r2 >> r1) | (r2 << (32 - r1));
 	PRES = res;
 	SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01;
 #ifdef DSP_DIS_RORQ
@@ -3659,19 +4439,19 @@ static void DSP_rorq(void)
 #endif
 }
 
-static void DSP_sat16s(void)		
+static void DSP_sat16s(void)
 {
-	INT32 r2 = PRN;
-	UINT32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2;
+	int32 r2 = PRN;
+	uint32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2;
 	PRES = res;
 	SET_ZN(res);
 }
 
-static void DSP_sat32s(void)		
+static void DSP_sat32s(void)
 {
-	INT32 r2 = (UINT32)PRN;
-	INT32 temp = dsp_acc >> 32;
-	UINT32 res = (temp < -1) ? (INT32)0x80000000 : (temp > 0) ? (INT32)0x7FFFFFFF : r2;
+	int32 r2 = (uint32)PRN;
+	int32 temp = dsp_acc >> 32;
+	uint32 res = (temp < -1) ? (int32)0x80000000 : (temp > 0) ? (int32)0x7FFFFFFF : r2;
 	PRES = res;
 	SET_ZN(res);
 }
@@ -3762,7 +4542,7 @@ static void DSP_sharq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SHARQ  #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	UINT32 res = (INT32)PRN >> dsp_convert_zero[PIMM1];
+	uint32 res = (int32)PRN >> dsp_convert_zero[PIMM1];
 	SET_ZN(res); dsp_flag_c = PRN & 0x01;
 	PRES = res;
 #ifdef DSP_DIS_SHARQ
@@ -3777,8 +4557,8 @@ static void DSP_shlq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SHLQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, 32 - PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	INT32 r1 = 32 - PIMM1;
-	UINT32 res = PRN << r1;
+	int32 r1 = 32 - PIMM1;
+	uint32 res = PRN << r1;
 	SET_ZN(res); dsp_flag_c = (PRN >> 31) & 1;
 	PRES = res;
 #ifdef DSP_DIS_SHLQ
@@ -3793,8 +4573,8 @@ static void DSP_shrq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SHRQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	INT32 r1 = dsp_convert_zero[PIMM1];
-	UINT32 res = PRN >> r1;
+	int32 r1 = dsp_convert_zero[PIMM1];
+	uint32 res = PRN >> r1;
 	SET_ZN(res); dsp_flag_c = PRN & 1;
 	PRES = res;
 #ifdef DSP_DIS_SHRQ
@@ -3811,7 +4591,11 @@ static void DSP_store(void)
 #endif
 //	DSPWriteLong(PRM, PRN, DSP);
 //	NO_WRITEBACK;
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	pipeline[plPtrExec].address = PRM & 0xFFFFFFFC;
+#else
 	pipeline[plPtrExec].address = PRM;
+#endif
 	pipeline[plPtrExec].value = PRN;
 	pipeline[plPtrExec].type = TYPE_DWORD;
 	WRITEBACK_ADDR;
@@ -3857,7 +4641,11 @@ static void DSP_storew(void)
 //		JaguarWriteWord(PRM, PRN, DSP);
 //
 //	NO_WRITEBACK;
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	pipeline[plPtrExec].address = PRM & 0xFFFFFFFE;
+#else
 	pipeline[plPtrExec].address = PRM;
+#endif
 
 	if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF))
 	{
@@ -3880,7 +4668,11 @@ static void DSP_store_r14_i(void)
 #endif
 //	DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP);
 //	NO_WRITEBACK;
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	pipeline[plPtrExec].address = (dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2);
+#else
 	pipeline[plPtrExec].address = dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2);
+#endif
 	pipeline[plPtrExec].value = PRN;
 	pipeline[plPtrExec].type = TYPE_DWORD;
 	WRITEBACK_ADDR;
@@ -3890,7 +4682,11 @@ static void DSP_store_r14_r(void)
 {
 //	DSPWriteLong(dsp_reg[14] + PRM, PRN, DSP);
 //	NO_WRITEBACK;
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	pipeline[plPtrExec].address = (dsp_reg[14] + PRM) & 0xFFFFFFFC;
+#else
 	pipeline[plPtrExec].address = dsp_reg[14] + PRM;
+#endif
 	pipeline[plPtrExec].value = PRN;
 	pipeline[plPtrExec].type = TYPE_DWORD;
 	WRITEBACK_ADDR;
@@ -3904,7 +4700,11 @@ static void DSP_store_r15_i(void)
 #endif
 //	DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP);
 //	NO_WRITEBACK;
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	pipeline[plPtrExec].address = (dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2);
+#else
 	pipeline[plPtrExec].address = dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2);
+#endif
 	pipeline[plPtrExec].value = PRN;
 	pipeline[plPtrExec].type = TYPE_DWORD;
 	WRITEBACK_ADDR;
@@ -3914,7 +4714,11 @@ static void DSP_store_r15_r(void)
 {
 //	DSPWriteLong(dsp_reg[15] + PRM, PRN, DSP);
 //	NO_WRITEBACK;
+#ifdef DSP_CORRECT_ALIGNMENT_STORE
+	pipeline[plPtrExec].address = (dsp_reg[15] + PRM) & 0xFFFFFFFC;
+#else
 	pipeline[plPtrExec].address = dsp_reg[15] + PRM;
+#endif
 	pipeline[plPtrExec].value = PRN;
 	pipeline[plPtrExec].type = TYPE_DWORD;
 	WRITEBACK_ADDR;
@@ -3926,7 +4730,7 @@ static void DSP_sub(void)
 	if (doDSPDis)
 		WriteLog("%06X: SUB    R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
-	UINT32 res = PRN - PRM;
+	uint32 res = PRN - PRM;
 	SET_ZNC_SUB(PRN, PRM, res);
 	PRES = res;
 #ifdef DSP_DIS_SUB
@@ -3941,8 +4745,8 @@ static void DSP_subc(void)
 	if (doDSPDis)
 		WriteLog("%06X: SUBC   R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN);
 #endif
-	UINT32 res = PRN - PRM - dsp_flag_c;
-	UINT32 borrow = dsp_flag_c;
+	uint32 res = PRN - PRM - dsp_flag_c;
+	uint32 borrow = dsp_flag_c;
 	SET_ZNC_SUB(PRN - borrow, PRM, res);
 	PRES = res;
 #ifdef DSP_DIS_SUBC
@@ -3957,8 +4761,8 @@ static void DSP_subq(void)
 	if (doDSPDis)
 		WriteLog("%06X: SUBQ   #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN);
 #endif
-	UINT32 r1 = dsp_convert_zero[PIMM1];
-	UINT32 res = PRN - r1;
+	uint32 r1 = dsp_convert_zero[PIMM1];
+	uint32 res = PRN - r1;
 	SET_ZNC_SUB(PRN, r1, res);
 	PRES = res;
 #ifdef DSP_DIS_SUBQ
@@ -3967,11 +4771,11 @@ static void DSP_subq(void)
 #endif
 }
 
-static void DSP_subqmod(void)	
+static void DSP_subqmod(void)
 {
-	UINT32 r1 = dsp_convert_zero[PIMM1];
-	UINT32 r2 = PRN;
-	UINT32 res = r2 - r1;
+	uint32 r1 = dsp_convert_zero[PIMM1];
+	uint32 r2 = PRN;
+	uint32 res = r2 - r1;
 	res = (res & (~dsp_modulo)) | (r2 & dsp_modulo);
 	PRES = res;
 	SET_ZNC_SUB(r2, r1, res);