X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fdsp.cpp;h=7a0553f292b6c432a8daaa80b56c51daf88e7ef5;hb=6f25f63a18153bc2adc49c5f9a3862c2760716df;hp=55b2077245331c1eded5b5c5da0294def195c54b;hpb=bbbe81acc03d62c5d4776d2acef59607c162cc8b;p=virtualjaguar diff --git a/src/dsp.cpp b/src/dsp.cpp index 55b2077..7a0553f 100644 --- a/src/dsp.cpp +++ b/src/dsp.cpp @@ -1,19 +1,49 @@ // // DSP core // -// by Cal2 +// Originally by David Raingeard // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) -// Extensive cleanups/rewrites by James L. Hammons +// Extensive cleanups/rewrites by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// JLH 11/26/2011 Added fixes for LOAD/STORE alignment issues // -#include // Used only for SDL_GetTicks... #include "dsp.h" -#define DSP_DEBUG -#define DSP_DEBUG_IRQ +#include // Used only for SDL_GetTicks... +#include +#include +#include "dac.h" +#include "gpu.h" +#include "jagdasm.h" +#include "jaguar.h" +#include "jerry.h" +#include "log.h" +#include "m68000/m68kinterface.h" +//#include "memory.h" + + +// Seems alignment in loads & stores was off... +#define DSP_CORRECT_ALIGNMENT +//#define DSP_CORRECT_ALIGNMENT_STORE + +//#define DSP_DEBUG +//#define DSP_DEBUG_IRQ +//#define DSP_DEBUG_PL2 +//#define DSP_DEBUG_STALL +//#define DSP_DEBUG_CC +#define NEW_SCOREBOARD // Disassembly definitions +#if 0 +#define DSP_DIS_ABS #define DSP_DIS_ADD #define DSP_DIS_ADDC #define DSP_DIS_ADDQ @@ -42,6 +72,7 @@ #define DSP_DIS_MOVEI #define DSP_DIS_MOVEQ #define DSP_DIS_MOVEFA +#define DSP_DIS_MOVEPC // Pipeline only! #define DSP_DIS_MOVETA #define DSP_DIS_MULT #define DSP_DIS_NEG @@ -65,9 +96,9 @@ #define DSP_DIS_SUBQT #define DSP_DIS_XOR //*/ -//bool doDSPDis = false; -bool doDSPDis = true; - +bool doDSPDis = false; +//bool doDSPDis = true; +#endif /* No dis yet: @@ -110,6 +141,57 @@ dsp opcodes use: + load_r14_ri 1229448 */ +// Pipeline structures + +const bool affectsScoreboard[64] = +{ + true, true, true, true, + true, true, true, true, + true, true, true, true, + true, false, true, true, + + true, true, false, true, + false, true, true, true, + true, true, true, true, + true, true, false, false, + + true, true, true, true, + false, true, true, true, + true, true, true, true, + true, false, false, false, + + true, false, false, true, + false, false, true, true, + true, false, true, true, + false, false, false, true +}; + +struct PipelineStage +{ + uint16 instruction; + uint8 opcode, operand1, operand2; + uint32 reg1, reg2, areg1, areg2; + uint32 result; + uint8 writebackRegister; + // General memory store... + uint32 address; + uint32 value; + uint8 type; +}; + +#define TYPE_BYTE 0 +#define TYPE_WORD 1 +#define TYPE_DWORD 2 +#define PIPELINE_STALL 64 // Set to # of opcodes + 1 +#ifndef NEW_SCOREBOARD +bool scoreboard[32]; +#else +uint8 scoreboard[32]; +#endif +uint8 plPtrFetch, plPtrRead, plPtrExec, plPtrWrite; +PipelineStage pipeline[4]; +bool IMASKCleared = false; + // DSP flags (old--have to get rid of this crap) #define CINT0FLAG 0x00200 @@ -165,7 +247,7 @@ static void dsp_opcode_abs(void); static void dsp_opcode_add(void); static void dsp_opcode_addc(void); static void dsp_opcode_addq(void); -static void dsp_opcode_addqmod(void); +static void dsp_opcode_addqmod(void); static void dsp_opcode_addqt(void); static void dsp_opcode_and(void); static void dsp_opcode_bclr(void); @@ -186,7 +268,7 @@ static void dsp_opcode_load_r14_indexed(void); static void dsp_opcode_load_r14_ri(void); static void dsp_opcode_load_r15_indexed(void); static void dsp_opcode_load_r15_ri(void); -static void dsp_opcode_mirror(void); +static void dsp_opcode_mirror(void); static void dsp_opcode_mmult(void); static void dsp_opcode_move(void); static void dsp_opcode_movei(void); @@ -205,8 +287,8 @@ static void dsp_opcode_resmac(void); static void dsp_opcode_ror(void); static void dsp_opcode_rorq(void); static void dsp_opcode_xor(void); -static void dsp_opcode_sat16s(void); -static void dsp_opcode_sat32s(void); +static void dsp_opcode_sat16s(void); +static void dsp_opcode_sat32s(void); static void dsp_opcode_sh(void); static void dsp_opcode_sha(void); static void dsp_opcode_sharq(void); @@ -222,31 +304,38 @@ static void dsp_opcode_store_r15_ri(void); static void dsp_opcode_sub(void); static void dsp_opcode_subc(void); static void dsp_opcode_subq(void); -static void dsp_opcode_subqmod(void); +static void dsp_opcode_subqmod(void); static void dsp_opcode_subqt(void); uint8 dsp_opcode_cycles[64] = { - 3, 3, 3, 3, - 3, 3, 3, 3, - 3, 3, 3, 3, - 3, 3, 3, 3, - 3, 3, 1, 3, - 1, 18, 3, 3, - 3, 3, 3, 3, - 3, 3, 3, 3, - 3, 3, 2, 2, - 2, 2, 3, 4, - 5, 4, 5, 6, - 6, 1, 1, 1, - 1, 2, 2, 2, - 1, 1, 9, 3, - 3, 1, 6, 6, - 2, 2, 3, 3 -}; + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 1, 3, 1, 18, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 2, 2, 2, 2, 3, 4, + 5, 4, 5, 6, 6, 1, 1, 1, + 1, 2, 2, 2, 1, 1, 9, 3, + 3, 1, 6, 6, 2, 2, 3, 3 +};//*/ +//Here's a QnD kludge... +//This is wrong, wrong, WRONG, but it seems to work for the time being... +//(That is, it fixes Flip Out which relies on GPU timing rather than semaphores. Bad developers! Bad!) +//What's needed here is a way to take pipeline effects into account (including pipeline stalls!)... +/*uint8 dsp_opcode_cycles[64] = +{ + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 9, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 2, + 2, 2, 2, 3, 3, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 4, 1, + 1, 1, 3, 3, 1, 1, 1, 1 +};//*/ void (* dsp_opcode[64])() = -{ +{ dsp_opcode_add, dsp_opcode_addc, dsp_opcode_addq, dsp_opcode_addqt, dsp_opcode_sub, dsp_opcode_subc, dsp_opcode_subq, dsp_opcode_subqt, dsp_opcode_neg, dsp_opcode_and, dsp_opcode_or, dsp_opcode_xor, @@ -265,10 +354,10 @@ void (* dsp_opcode[64])() = dsp_opcode_store_r14_ri, dsp_opcode_store_r15_ri, dsp_opcode_nop, dsp_opcode_addqmod, }; -uint32 dsp_opcode_use[64]; +uint32 dsp_opcode_use[65]; -char * dsp_opcode_str[65]= -{ +const char * dsp_opcode_str[65]= +{ "add", "addc", "addq", "addqt", "sub", "subc", "subq", "subqt", "neg", "and", "or", "xor", @@ -298,9 +387,9 @@ static uint32 dsp_pointer_to_matrix; static uint32 dsp_data_organization; uint32 dsp_control; static uint32 dsp_div_control; -static uint8 dsp_flag_z, dsp_flag_n, dsp_flag_c; -static uint32 * dsp_reg, * dsp_alternate_reg; -static uint32 * dsp_reg_bank_0, * dsp_reg_bank_1; +static uint8 dsp_flag_z, dsp_flag_n, dsp_flag_c; +static uint32 * dsp_reg = NULL, * dsp_alternate_reg = NULL; +static uint32 dsp_reg_bank_0[32], dsp_reg_bank_1[32]; static uint32 dsp_opcode_first_parameter; static uint32 dsp_opcode_second_parameter; @@ -318,17 +407,20 @@ static uint32 dsp_opcode_second_parameter; #define CLR_ZN (dsp_flag_z = dsp_flag_n = 0) #define CLR_ZNC (dsp_flag_z = dsp_flag_n = dsp_flag_c = 0) #define SET_Z(r) (dsp_flag_z = ((r) == 0)) -#define SET_N(r) (dsp_flag_n = (((UINT32)(r) >> 31) & 0x01)) -#define SET_C_ADD(a,b) (dsp_flag_c = ((UINT32)(b) > (UINT32)(~(a)))) -#define SET_C_SUB(a,b) (dsp_flag_c = ((UINT32)(b) > (UINT32)(a))) +#define SET_N(r) (dsp_flag_n = (((uint32)(r) >> 31) & 0x01)) +#define SET_C_ADD(a,b) (dsp_flag_c = ((uint32)(b) > (uint32)(~(a)))) +#define SET_C_SUB(a,b) (dsp_flag_c = ((uint32)(b) > (uint32)(a))) #define SET_ZN(r) SET_N(r); SET_Z(r) #define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) #define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b) -uint32 dsp_convert_zero[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; -uint8 * dsp_branch_condition_table = NULL; -static uint16 * mirror_table = NULL; -static uint8 * dsp_ram_8 = NULL; +uint32 dsp_convert_zero[32] = { + 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +}; +uint8 dsp_branch_condition_table[32 * 8]; +static uint16 mirror_table[65536]; +static uint8 dsp_ram_8[0x2000]; #define BRANCH_CONDITION(x) dsp_branch_condition_table[(x) + ((jaguar_flags & 7) << 5)] @@ -337,6 +429,14 @@ static uint32 dsp_releaseTimeSlice_flag = 0; FILE * dsp_fp; +#ifdef DSP_DEBUG_CC +// Comparison core vars (used only for core comparison! :-) +static uint64 count = 0; +static uint8 ram1[0x2000], ram2[0x2000]; +static uint32 regs1[64], regs2[64]; +static uint32 ctrl1[14], ctrl2[14]; +#endif + // Private function prototypes void DSPDumpRegisters(void); @@ -346,11 +446,11 @@ void FlushDSPPipeline(void); void dsp_reset_stats(void) { - for(int i=0; i<64; i++) + for(int i=0; i<65; i++) dsp_opcode_use[i] = 0; } -void dsp_releaseTimeslice(void) +void DSPReleaseTimeslice(void) { //This does absolutely nothing!!! !!! FIX !!! dsp_releaseTimeSlice_flag = 1; @@ -358,49 +458,39 @@ void dsp_releaseTimeslice(void) void dsp_build_branch_condition_table(void) { - // Allocate the mirror table - if (!mirror_table) - mirror_table = (uint16 *)malloc(65536 * sizeof(mirror_table[0])); - // Fill in the mirror table - if (mirror_table) - for(int i=0; i<65536; i++) - mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002) | - ((i >> 11) & 0x0004) | ((i >> 9) & 0x0008) | - ((i >> 7) & 0x0010) | ((i >> 5) & 0x0020) | - ((i >> 3) & 0x0040) | ((i >> 1) & 0x0080) | - ((i << 1) & 0x0100) | ((i << 3) & 0x0200) | - ((i << 5) & 0x0400) | ((i << 7) & 0x0800) | - ((i << 9) & 0x1000) | ((i << 11) & 0x2000) | - ((i << 13) & 0x4000) | ((i << 15) & 0x8000); - - if (!dsp_branch_condition_table) - { - dsp_branch_condition_table = (uint8 *)malloc(32 * 8 * sizeof(dsp_branch_condition_table[0])); - - // Fill in the condition table - if (dsp_branch_condition_table) + for(int i=0; i<65536; i++) + { + mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002) + | ((i >> 11) & 0x0004) | ((i >> 9) & 0x0008) + | ((i >> 7) & 0x0010) | ((i >> 5) & 0x0020) + | ((i >> 3) & 0x0040) | ((i >> 1) & 0x0080) + | ((i << 1) & 0x0100) | ((i << 3) & 0x0200) + | ((i << 5) & 0x0400) | ((i << 7) & 0x0800) + | ((i << 9) & 0x1000) | ((i << 11) & 0x2000) + | ((i << 13) & 0x4000) | ((i << 15) & 0x8000); + } + + // Fill in the condition table + for(int i=0; i<8; i++) + { + for(int j=0; j<32; j++) { - for(int i=0; i<8; i++) - { - for(int j=0; j<32; j++) - { - int result = 1; - if (j & 1) - if (i & ZERO_FLAG) - result = 0; - if (j & 2) - if (!(i & ZERO_FLAG)) - result = 0; - if (j & 4) - if (i & (CARRY_FLAG << (j >> 4))) - result = 0; - if (j & 8) - if (!(i & (CARRY_FLAG << (j >> 4)))) - result = 0; - dsp_branch_condition_table[i * 32 + j] = result; - } - } + int result = 1; + + if ((j & 1) && (i & ZERO_FLAG)) + result = 0; + + if ((j & 2) && (!(i & ZERO_FLAG))) + result = 0; + + if ((j & 4) && (i & (CARRY_FLAG << (j >> 4)))) + result = 0; + + if ((j & 8) && (!(i & (CARRY_FLAG << (j >> 4))))) + result = 0; + + dsp_branch_condition_table[i * 32 + j] = result; } } } @@ -439,7 +529,7 @@ uint8 DSPReadByte(uint32 offset, uint32 who/*=UNKNOWN*/) } return JaguarReadByte(offset, who); -} +} uint16 DSPReadWord(uint32 offset, uint32 who/*=UNKNOWN*/) { @@ -464,12 +554,12 @@ uint16 DSPReadWord(uint32 offset, uint32 who/*=UNKNOWN*/) if (offset==0xF1B2C2) return(0x0000); } */ - // pour permettre à wolfenstein 3d de tourner sans le dsp + // pour permettre � wolfenstein 3d de tourner sans le dsp /* if ((offset==0xF1B0D0)||(offset==0xF1B0D2)) return(0); */ - // pour permettre à nba jam de tourner sans le dsp + // pour permettre � nba jam de tourner sans le dsp /* if (jaguar_mainRom_crc32==0x4faddb18) { if (offset==0xf1b2c0) return(0); @@ -534,12 +624,9 @@ uint32 DSPReadLong(uint32 offset, uint32 who/*=UNKNOWN*/) offset &= 0x3F; switch (offset) { - case 0x00: /*dsp_flag_c?(dsp_flag_c=1):(dsp_flag_c=0); - dsp_flag_z?(dsp_flag_z=1):(dsp_flag_z=0); - dsp_flag_n?(dsp_flag_n=1):(dsp_flag_n=0);*/ - - dsp_flags = (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; - return dsp_flags & 0xFFFFC1FF; + case 0x00: + dsp_flags = (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; + return dsp_flags & 0xFFFFC1FF; case 0x04: return dsp_matrix_control; case 0x08: return dsp_pointer_to_matrix; case 0x0C: return dsp_data_organization; @@ -570,7 +657,7 @@ void DSPWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) /* if (dsp_in_exec == 0) { m68k_end_timeslice(); - gpu_releaseTimeslice(); + dsp_releaseTimeslice(); }*/ return; } @@ -578,7 +665,7 @@ void DSPWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) { uint32 reg = offset & 0x1C; int bytenum = offset & 0x03; - + if ((reg >= 0x1C) && (reg <= 0x1F)) dsp_div_control = (dsp_div_control & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); else @@ -586,7 +673,7 @@ void DSPWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) //This looks funky. !!! FIX !!! uint32 old_data = DSPReadLong(offset&0xFFFFFFC, who); bytenum = 3 - bytenum; // convention motorola !!! - old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); + old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); DSPWriteLong(offset & 0xFFFFFFC, old_data, who); } return; @@ -608,6 +695,10 @@ void DSPWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) // WriteLog("dsp: writing %.4x at 0x%.8x\n",data,offset); if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000)) { +/*if (offset == 0xF1B2F4) +{ + WriteLog("DSP: %s is writing %04X at location 0xF1B2F4 (DSP_PC: %08X)...\n", whoName[who], data, dsp_pc); +}//*/ offset -= DSP_WORK_RAM_BASE; dsp_ram_8[offset] = data >> 8; dsp_ram_8[offset+1] = data & 0xFF; @@ -616,8 +707,14 @@ void DSPWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) { // WriteLog("dsp: writing %.4x at 0x%.8x\n",data,offset+DSP_WORK_RAM_BASE); m68k_end_timeslice(); - gpu_releaseTimeslice(); + dsp_releaseTimeslice(); }*/ +//CC only! +#ifdef DSP_DEBUG_CC +SET16(ram1, offset, data), +SET16(ram2, offset, data); +#endif +//!!!!!!!! return; } else if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20)) @@ -625,19 +722,22 @@ void DSPWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) if ((offset & 0x1C) == 0x1C) { if (offset & 0x03) - dsp_div_control = (dsp_div_control&0xffff0000)|(data&0xffff); + dsp_div_control = (dsp_div_control & 0xFFFF0000) | (data & 0xFFFF); else - dsp_div_control = (dsp_div_control&0xffff)|((data&0xffff)<<16); + dsp_div_control = (dsp_div_control & 0xFFFF) | ((data & 0xFFFF) << 16); } else { - uint32 old_data = DSPReadLong(offset & 0xffffffc, who); + uint32 old_data = DSPReadLong(offset & 0xFFFFFFC, who); + if (offset & 0x03) - old_data = (old_data&0xffff0000)|(data&0xffff); + old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF); else - old_data = (old_data&0xffff)|((data&0xffff)<<16); - DSPWriteLong(offset & 0xffffffc, old_data, who); + old_data = (old_data & 0xFFFF) | ((data & 0xFFFF) << 16); + + DSPWriteLong(offset & 0xFFFFFFC, old_data, who); } + return; } @@ -664,6 +764,12 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) }//*/ offset -= DSP_WORK_RAM_BASE; SET32(dsp_ram_8, offset, data); +//CC only! +#ifdef DSP_DEBUG_CC +SET32(ram1, offset, data), +SET32(ram2, offset, data); +#endif +//!!!!!!!! return; } else if (offset >= DSP_CONTROL_RAM_BASE && offset <= (DSP_CONTROL_RAM_BASE + 0x1F)) @@ -674,17 +780,62 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) case 0x00: { #ifdef DSP_DEBUG - WriteLog("DSP: Writing %08X to DSP_FLAGS by %s...\n", data, whoName[who]); + WriteLog("DSP: Writing %08X to DSP_FLAGS by %s (REGPAGE is %sset)...\n", data, whoName[who], (dsp_flags & REGPAGE ? "" : "not ")); #endif - bool IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); - dsp_flags = data; +// bool IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); + IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); + // NOTE: According to the JTRM, writing a 1 to IMASK has no effect; only the + // IRQ logic can set it. So we mask it out here to prevent problems... + dsp_flags = data & (~IMASK); dsp_flag_z = dsp_flags & 0x01; dsp_flag_c = (dsp_flags >> 1) & 0x01; dsp_flag_n = (dsp_flags >> 2) & 0x01; DSPUpdateRegisterBanks(); dsp_control &= ~((dsp_flags & CINT04FLAGS) >> 3); dsp_control &= ~((dsp_flags & CINT5FLAG) >> 1); - if (IMASKCleared) // If IMASK was cleared, + +// NB: This is just a wild hairy-assed guess as to what the playback frequency is. +// It can be timed to anything really, anything that writes to L/RTXD at a regular +// interval. Most things seem to use either the I2S interrupt or the TIMER 0 +// interrupt, so that's what we check for here. Just know that this approach +// can be easily fooled! +// Note also that if both interrupts are enabled, the I2S freq will win. :-P + +// Further Note: +// The impetus for this "fix" was Cybermorph, which sets the SCLK to 7 which is an +// audio frequency > 48 KHz. However, it stuffs the L/RTXD registers using TIMER0. +// So, while this works, it's a by-product of the lame way in which audio is currently +// handled. Hopefully, once we run the DSP in the host audio IRQ, this problem will +// go away of its own accord. :-P +// Or does it? It seems the I2S interrupt isn't on with Cybermorph, so something +// weird is going on here... +// Maybe it works like this: It acknowledges the 1st interrupt, but never clears it. +// So subsequent interrupts come into the chip, but they're never serviced but the +// I2S subsystem keeps going. +// After some testing on real hardware, it seems that if you enable TIMER0 and EXTERNAL +// IRQs on J_INT ($F10020), you don't have to run an I2S interrupt on the DSP. Also, +// It seems that it's only stable for values of SCLK <= 9. + +// All of the preceeding is moot now; we run the DSP in the host audio IRQ. This means +// that we don't actually need this stuff anymore. :-D +#if 0 + if (data & INT_ENA1) // I2S interrupt + { + int freq = GetCalculatedFrequency(); +//This happens too often to be useful... +// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq); + DACSetNewFrequency(freq); + } + else if (data & INT_ENA2) // TIMER 0 interrupt + { + int freq = JERRYGetPIT1Frequency(); +//This happens too often to be useful... +// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq); + DACSetNewFrequency(freq); + } +#endif + +/* if (IMASKCleared) // If IMASK was cleared, #ifdef DSP_DEBUG_IRQ { WriteLog("DSP: Finished interrupt.\n"); @@ -692,6 +843,29 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) DSPHandleIRQs(); // see if any other interrupts need servicing! #ifdef DSP_DEBUG_IRQ } +#endif//*/ +#if 0 + if (/*4-8, 16*/data & 0x101F0) + WriteLog("DSP: %s is enabling interrupts %s%s%s%s%s%s\n", whoName[who], + (data & 0x010 ? "CPU " : ""), (data & 0x020 ? "I2S " : ""), + (data & 0x040 ? "TIMER0 " : ""), (data & 0x080 ? "TIMER1 " : ""), + (data & 0x100 ? "EXT0 " : ""), (data & 0x10000 ? "EXT1" : "")); +/*if (data & 0x00020) // CD BIOS DSP code... +{ +//001AC1BA: movea.l #$1AC200, A0 +//001AC1C0: move.l #$1AC68C, D0 + char buffer[512]; + + WriteLog("\n---[DSP code at 00F1B97C]---------------------------\n"); + uint32 j = 0xF1B97C;//0x1AC200; + while (j <= 0xF1BE08)//0x1AC68C) + { + uint32 oldj = j; + j += dasmjag(JAGUAR_DSP, buffer, j); +// WriteLog("\t%08X: %s\n", oldj+0xD6F77C, buffer); + WriteLog("\t%08X: %s\n", oldj, buffer); + } +}//*/ #endif break; } @@ -699,7 +873,7 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) dsp_matrix_control = data; break; case 0x08: - // According to JTRM, only lines 2-11 are adressable, the rest being + // According to JTRM, only lines 2-11 are addressable, the rest being // hardwired to $F1Bxxx. dsp_pointer_to_matrix = 0xF1B000 | (data & 0x000FFC); break; @@ -711,21 +885,34 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) #ifdef DSP_DEBUG WriteLog("DSP: Setting DSP PC to %08X by %s%s\n", dsp_pc, whoName[who], (DSP_RUNNING ? " (DSP is RUNNING!)" : ""));//*/ #endif +//CC only! +#ifdef DSP_DEBUG_CC +if (who != DSP) + ctrl1[0] = ctrl2[0] = data; +#endif +//!!!!!!!! break; case 0x14: - { + { +//#ifdef DSP_DEBUG +WriteLog("Write to DSP CTRL by %s: %08X (DSP PC=$%08X)\n", whoName[who], data, dsp_pc); +//#endif + bool wasRunning = DSP_RUNNING; // uint32 dsp_was_running = DSP_RUNNING; // Check for DSP -> CPU interrupt if (data & CPUINT) { -// WriteLog("DSP: DSP -> CPU interrupt\n"); +#ifdef DSP_DEBUG + WriteLog("DSP: DSP -> CPU interrupt\n"); +#endif // This was WRONG -// Why do we check for a valid handler at 64? Isn't that the Jag programmer's responsibility? - if (JERRYIRQEnabled(IRQ2_DSP) && jaguar_interrupt_handler_is_valid(64)) +// Why do we check for a valid handler at 64? Isn't that the Jag programmer's responsibility? (YES) +#warning "!!! DSP IRQs that go to the 68K have to be routed thru TOM !!! FIX !!!" + if (JERRYIRQEnabled(IRQ2_DSP))// && jaguar_interrupt_handler_is_valid(64)) { JERRYSetPendingIRQ(IRQ2_DSP); - dsp_releaseTimeslice(); - m68k_set_irq(7); // Set 68000 NMI... + DSPReleaseTimeslice(); + m68k_set_irq(2); // Set 68000 IPL 2... } data &= ~CPUINT; } @@ -736,7 +923,7 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) WriteLog("DSP: CPU -> DSP interrupt\n"); #endif m68k_end_timeslice(); - gpu_releaseTimeslice(); + DSPReleaseTimeslice(); DSPSetIRQLine(DSPIRQ_CPU, ASSERT_LINE); data &= ~DSPINT0; } @@ -749,6 +936,12 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) // Protect writes to VERSION and the interrupt latches... uint32 mask = VERSION | INT_LAT0 | INT_LAT1 | INT_LAT2 | INT_LAT3 | INT_LAT4 | INT_LAT5; dsp_control = (dsp_control & mask) | (data & ~mask); +//CC only! +#ifdef DSP_DEBUG_CC +if (who != DSP) + ctrl1[8] = ctrl2[8] = dsp_control; +#endif +//!!!!!!!! // if dsp wasn't running but is now running // execute a few cycles @@ -764,23 +957,23 @@ void DSPWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/) DSPExec(1); #endif #ifdef DSP_DEBUG -WriteLog("Write to DSP CTRL: %08X ", data); if (DSP_RUNNING) WriteLog(" --> Starting to run at %08X by %s...", dsp_pc, whoName[who]); else WriteLog(" --> Stopped by %s! (DSP PC: %08X)", whoName[who], dsp_pc); WriteLog("\n"); #endif // DSP_DEBUG -//This isn't exactly right either--we don't know if it was the M68K or the GPU writing here... +//This isn't exactly right either--we don't know if it was the M68K or the DSP writing here... // !!! FIX !!! [DONE] if (DSP_RUNNING) { if (who == M68K) m68k_end_timeslice(); - else if (who == GPU) - gpu_releaseTimeslice(); + else if (who == DSP) + DSPReleaseTimeslice(); - FlushDSPPipeline(); + if (!wasRunning) + FlushDSPPipeline(); //DSPDumpDisassembly(); } break; @@ -822,7 +1015,7 @@ void DSPUpdateRegisterBanks(void) } // -// Check for an handle any asserted DSP IRQs +// Check for and handle any asserted DSP IRQs // void DSPHandleIRQs(void) { @@ -839,7 +1032,7 @@ void DSPHandleIRQs(void) if (!bits) // Bail if nothing is enabled return; - int which = 0; // Determine which interrupt + int which = 0; // Determine which interrupt if (bits & 0x01) which = 0; if (bits & 0x02) @@ -854,24 +1047,213 @@ void DSPHandleIRQs(void) which = 5; #ifdef DSP_DEBUG_IRQ - WriteLog("DSP: Generating interrupt #%i...\n", which); + WriteLog("DSP: Generating interrupt #%i...", which); #endif +//temp... !!!!! +//if (which == 0) doDSPDis = true; + + // NOTE: Since the actual Jaguar hardware injects the code sequence below + // directly into the pipeline, it has the side effect of ensuring that the + // instruction interrupted also gets to do its writeback. We simulate that + // behavior here. +/* if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; + }//*/ +//This should be execute (or should it?--not sure now!) +//Actually, the way this is called now, this should be correct (i.e., the plPtrs advance, +//and what just executed is now in the Write position...). So why didn't it do the +//writeback into register 0? +#ifdef DSP_DEBUG_IRQ +WriteLog("--> Pipeline dump [DSP_PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +#endif + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } + +#ifndef NEW_SCOREBOARD + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif + } + dsp_flags |= IMASK; +//CC only! +#ifdef DSP_DEBUG_CC +ctrl2[4] = dsp_flags; +#endif +//!!!!!!!! DSPUpdateRegisterBanks(); +#ifdef DSP_DEBUG_IRQ +// WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc, dsp_reg[31]); + WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)), dsp_reg[31]); +#endif - // subqt #4,r31 ; pre-decrement stack pointer - // move pc,r30 ; address of interrupted code + // subqt #4,r31 ; pre-decrement stack pointer + // move pc,r30 ; address of interrupted code // store r30,(r31) ; store return address dsp_reg[31] -= 4; - DSPWriteLong(dsp_reg[31], dsp_pc - 2, DSP); +//CC only! +#ifdef DSP_DEBUG_CC +regs2[31] -= 4; +#endif +//!!!!!!!! +//This might not come back to the right place if the instruction was MOVEI #. !!! FIX !!! +//But, then again, JTRM says that it adds two regardless of what the instruction was... +//It missed the place that it was supposed to come back to, so this is WRONG! +// +// Look at the pipeline when an interrupt occurs (instructions of foo, bar, baz): +// +// R -> baz (<- PC points here) +// E -> bar (when it should point here!) +// W -> foo +// +// 'Foo' just completed executing as per above. PC is pointing to the instruction 'baz' +// which means (assuming they're all 2 bytes long) that the code below will come back on +// instruction 'baz' instead of 'bar' which is the next instruction to execute in the +// instruction stream... + +// DSPWriteLong(dsp_reg[31], dsp_pc - 2, DSP); + DSPWriteLong(dsp_reg[31], dsp_pc - 2 - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)), DSP); +//CC only! +#ifdef DSP_DEBUG_CC +SET32(ram2, regs2[31] - 0xF1B000, dsp_pc - 2 - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2))); +#endif +//!!!!!!!! - // movei #service_address,r30 ; pointer to ISR entry - // jump (r30) ; jump to ISR + // movei #service_address,r30 ; pointer to ISR entry + // jump (r30) ; jump to ISR // nop dsp_pc = dsp_reg[30] = DSP_WORK_RAM_BASE + (which * 0x10); +//CC only! +#ifdef DSP_DEBUG_CC +ctrl2[0] = regs2[30] = dsp_pc; +#endif +//!!!!!!!! FlushDSPPipeline(); } +// +// Non-pipelined version... +// +void DSPHandleIRQsNP(void) +{ +//CC only! +#ifdef DSP_DEBUG_CC + memcpy(dsp_ram_8, ram1, 0x2000); + memcpy(dsp_reg_bank_0, regs1, 32 * 4); + memcpy(dsp_reg_bank_1, ®s1[32], 32 * 4); + dsp_pc = ctrl1[0]; + dsp_acc = ctrl1[1]; + dsp_remain = ctrl1[2]; + dsp_modulo = ctrl1[3]; + dsp_flags = ctrl1[4]; + dsp_matrix_control = ctrl1[5]; + dsp_pointer_to_matrix = ctrl1[6]; + dsp_data_organization = ctrl1[7]; + dsp_control = ctrl1[8]; + dsp_div_control = ctrl1[9]; + IMASKCleared = ctrl1[10]; + dsp_flag_z = ctrl1[11]; + dsp_flag_n = ctrl1[12]; + dsp_flag_c = ctrl1[13]; +DSPUpdateRegisterBanks(); +#endif +//!!!!!!!! + if (dsp_flags & IMASK) // Bail if we're already inside an interrupt + return; + + // Get the active interrupt bits (latches) & interrupt mask (enables) + uint32 bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F), + mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F); + +// WriteLog("dsp: bits=%.2x mask=%.2x\n",bits,mask); + bits &= mask; + + if (!bits) // Bail if nothing is enabled + return; + + int which = 0; // Determine which interrupt + if (bits & 0x01) + which = 0; + if (bits & 0x02) + which = 1; + if (bits & 0x04) + which = 2; + if (bits & 0x08) + which = 3; + if (bits & 0x10) + which = 4; + if (bits & 0x20) + which = 5; + +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Generating interrupt #%i...", which); +#endif + + dsp_flags |= IMASK; +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[4] = dsp_flags; +#endif +//!!!!!!!! + DSPUpdateRegisterBanks(); +#ifdef DSP_DEBUG_IRQ + WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc, dsp_reg[31]); +#endif + + // subqt #4,r31 ; pre-decrement stack pointer + // move pc,r30 ; address of interrupted code + // store r30,(r31) ; store return address + dsp_reg[31] -= 4; +//CC only! +#ifdef DSP_DEBUG_CC +regs1[31] -= 4; +#endif +//!!!!!!!! + DSPWriteLong(dsp_reg[31], dsp_pc - 2, DSP); +//CC only! +#ifdef DSP_DEBUG_CC +SET32(ram1, regs1[31] - 0xF1B000, dsp_pc - 2); +#endif +//!!!!!!!! + + // movei #service_address,r30 ; pointer to ISR entry + // jump (r30) ; jump to ISR + // nop + dsp_pc = dsp_reg[30] = DSP_WORK_RAM_BASE + (which * 0x10); +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[0] = regs1[30] = dsp_pc; +#endif +//!!!!!!!! +} + // // Set the specified DSP IRQ line to a given state // @@ -880,22 +1262,44 @@ void DSPSetIRQLine(int irqline, int state) //NOTE: This doesn't take INT_LAT5 into account. !!! FIX !!! uint32 mask = INT_LAT0 << irqline; dsp_control &= ~mask; // Clear the latch bit +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[8] = ctrl2[8] = dsp_control; +#endif +//!!!!!!!! if (state) { dsp_control |= mask; // Set the latch bit DSPHandleIRQs(); +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[8] = ctrl2[8] = dsp_control; +DSPHandleIRQsNP(); +#endif +//!!!!!!!! } + + // Not sure if this is correct behavior, but according to JTRM, + // the IRQ output of JERRY is fed to this IRQ in the GPU... +// Not sure this is right--DSP interrupts seem to be different from the JERRY interrupts! +// GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE); +} + +bool DSPIsRunning(void) +{ + return (DSP_RUNNING ? true : false); } void DSPInit(void) { - memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM"); - memory_malloc_secure((void **)&dsp_reg_bank_0, 32 * sizeof(int32), "DSP bank 0 regs"); - memory_malloc_secure((void **)&dsp_reg_bank_1, 32 * sizeof(int32), "DSP bank 1 regs"); +// memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM"); +// memory_malloc_secure((void **)&dsp_reg_bank_0, 32 * sizeof(int32), "DSP bank 0 regs"); +// memory_malloc_secure((void **)&dsp_reg_bank_1, 32 * sizeof(int32), "DSP bank 1 regs"); dsp_build_branch_condition_table(); DSPReset(); + srand(time(NULL)); // For randomizing local RAM } void DSPReset(void) @@ -919,9 +1323,15 @@ void DSPReset(void) dsp_reg[i] = dsp_alternate_reg[i] = 0x00000000; CLR_ZNC; - + IMASKCleared = false; + FlushDSPPipeline(); dsp_reset_stats(); - memset(dsp_ram_8, 0xFF, 0x2000); +// memset(dsp_ram_8, 0xFF, 0x2000); + // Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents + for(uint32 i=0; i<8192; i+=4) + { + *((uint32 *)(&dsp_ram_8[i])) = rand(); + } } void DSPDumpDisassembly(void) @@ -930,6 +1340,7 @@ void DSPDumpDisassembly(void) WriteLog("\n---[DSP code at 00F1B000]---------------------------\n"); uint32 j = 0xF1B000; + while (j <= 0xF1CFFF) { uint32 oldj = j; @@ -943,6 +1354,7 @@ void DSPDumpRegisters(void) //Shoud add modulus, etc to dump here... WriteLog("\n---[DSP flags: NCZ %d%d%d, DSP PC: %08X]------------\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_pc); WriteLog("\nRegisters bank 0\n"); + for(int j=0; j<8; j++) { WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", @@ -951,7 +1363,9 @@ void DSPDumpRegisters(void) (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2], (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]); } + WriteLog("Registers bank 1\n"); + for(int j=0; j<8; j++) { WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", @@ -965,38 +1379,46 @@ void DSPDumpRegisters(void) void DSPDone(void) { int i, j; - WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp %s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "was" : "wasn't")); + WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp was%s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "" : "n't")); WriteLog("DSP: %sin interrupt handler\n", (dsp_flags & IMASK ? "" : "not ")); - // get the active interrupt bits + // get the active interrupt bits int bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F); - // get the interrupt mask + // get the interrupt mask int mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F); - WriteLog("DSP: pending=%08X enabled=%08X\n", bits, mask); + WriteLog("DSP: pending=$%X enabled=$%X (%s%s%s%s%s%s)\n", bits, mask, + (mask & 0x01 ? "CPU " : ""), (mask & 0x02 ? "I2S " : ""), + (mask & 0x04 ? "Timer0 " : ""), (mask & 0x08 ? "Timer1 " : ""), + (mask & 0x10 ? "Ext0 " : ""), (mask & 0x20 ? "Ext1" : "")); WriteLog("\nRegisters bank 0\n"); + for(int j=0; j<8; j++) { - WriteLog("\tr%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x\n", + WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n", (j << 2) + 0, dsp_reg_bank_0[(j << 2) + 0], (j << 2) + 1, dsp_reg_bank_0[(j << 2) + 1], (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2], (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]); } + WriteLog("\nRegisters bank 1\n"); + for (j=0; j<8; j++) { - WriteLog("\tr%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x r%2i=0x%.8x\n", + WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n", (j << 2) + 0, dsp_reg_bank_1[(j << 2) + 0], (j << 2) + 1, dsp_reg_bank_1[(j << 2) + 1], (j << 2) + 2, dsp_reg_bank_1[(j << 2) + 2], (j << 2) + 3, dsp_reg_bank_1[(j << 2) + 3]); - } + WriteLog("\n"); + static char buffer[512]; j = DSP_WORK_RAM_BASE; - while (j <= 0xF1BFFF) + + while (j <= 0xF1CFFF) { uint32 oldj = j; j += dasmjag(JAGUAR_DSP, buffer, j); @@ -1004,20 +1426,230 @@ void DSPDone(void) }//*/ WriteLog("DSP opcodes use:\n"); + for (i=0;i<64;i++) { if (dsp_opcode_use[i]) WriteLog("\t%s %i\n", dsp_opcode_str[i], dsp_opcode_use[i]); }//*/ - memory_free(dsp_ram_8); +// memory_free(dsp_ram_8); +// memory_free(dsp_reg_bank_0); +// memory_free(dsp_reg_bank_1); +// if (dsp_branch_condition_table) +// free(dsp_branch_condition_table); + +// if (mirror_table) +// free(mirror_table); +} + + + +// +// DSP comparison core... +// +#ifdef DSP_DEBUG_CC +static uint16 lastExec; +void DSPExecComp(int32 cycles) +{ + while (cycles > 0 && DSP_RUNNING) + { + // Load up vars for non-pipelined core + memcpy(dsp_ram_8, ram1, 0x2000); + memcpy(dsp_reg_bank_0, regs1, 32 * 4); + memcpy(dsp_reg_bank_1, ®s1[32], 32 * 4); + dsp_pc = ctrl1[0]; + dsp_acc = ctrl1[1]; + dsp_remain = ctrl1[2]; + dsp_modulo = ctrl1[3]; + dsp_flags = ctrl1[4]; + dsp_matrix_control = ctrl1[5]; + dsp_pointer_to_matrix = ctrl1[6]; + dsp_data_organization = ctrl1[7]; + dsp_control = ctrl1[8]; + dsp_div_control = ctrl1[9]; + IMASKCleared = ctrl1[10]; + dsp_flag_z = ctrl1[11]; + dsp_flag_n = ctrl1[12]; + dsp_flag_c = ctrl1[13]; +DSPUpdateRegisterBanks(); + + // Decrement cycles based on non-pipelined core... + uint16 instr1 = DSPReadWord(dsp_pc, DSP); + cycles -= dsp_opcode_cycles[instr1 >> 10]; + +//WriteLog("\tAbout to execute non-pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32)count, dsp_pc); + DSPExec(1); // Do *one* instruction + + // Save vars + memcpy(ram1, dsp_ram_8, 0x2000); + memcpy(regs1, dsp_reg_bank_0, 32 * 4); + memcpy(®s1[32], dsp_reg_bank_1, 32 * 4); + ctrl1[0] = dsp_pc; + ctrl1[1] = dsp_acc; + ctrl1[2] = dsp_remain; + ctrl1[3] = dsp_modulo; + ctrl1[4] = dsp_flags; + ctrl1[5] = dsp_matrix_control; + ctrl1[6] = dsp_pointer_to_matrix; + ctrl1[7] = dsp_data_organization; + ctrl1[8] = dsp_control; + ctrl1[9] = dsp_div_control; + ctrl1[10] = IMASKCleared; + ctrl1[11] = dsp_flag_z; + ctrl1[12] = dsp_flag_n; + ctrl1[13] = dsp_flag_c; + + // Load up vars for pipelined core + memcpy(dsp_ram_8, ram2, 0x2000); + memcpy(dsp_reg_bank_0, regs2, 32 * 4); + memcpy(dsp_reg_bank_1, ®s2[32], 32 * 4); + dsp_pc = ctrl2[0]; + dsp_acc = ctrl2[1]; + dsp_remain = ctrl2[2]; + dsp_modulo = ctrl2[3]; + dsp_flags = ctrl2[4]; + dsp_matrix_control = ctrl2[5]; + dsp_pointer_to_matrix = ctrl2[6]; + dsp_data_organization = ctrl2[7]; + dsp_control = ctrl2[8]; + dsp_div_control = ctrl2[9]; + IMASKCleared = ctrl2[10]; + dsp_flag_z = ctrl2[11]; + dsp_flag_n = ctrl2[12]; + dsp_flag_c = ctrl2[13]; +DSPUpdateRegisterBanks(); + +//WriteLog("\tAbout to execute pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32)count, dsp_pc); + DSPExecP2(1); // Do *one* instruction + + // Save vars + memcpy(ram2, dsp_ram_8, 0x2000); + memcpy(regs2, dsp_reg_bank_0, 32 * 4); + memcpy(®s2[32], dsp_reg_bank_1, 32 * 4); + ctrl2[0] = dsp_pc; + ctrl2[1] = dsp_acc; + ctrl2[2] = dsp_remain; + ctrl2[3] = dsp_modulo; + ctrl2[4] = dsp_flags; + ctrl2[5] = dsp_matrix_control; + ctrl2[6] = dsp_pointer_to_matrix; + ctrl2[7] = dsp_data_organization; + ctrl2[8] = dsp_control; + ctrl2[9] = dsp_div_control; + ctrl2[10] = IMASKCleared; + ctrl2[11] = dsp_flag_z; + ctrl2[12] = dsp_flag_n; + ctrl2[13] = dsp_flag_c; + + if (instr1 != lastExec) + { +// WriteLog("\nCores diverged at instruction tick #%u!\nAttemping to synchronize...\n\n", count); + +// uint32 ppc = ctrl2[0] - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)) - (pipeline[plPtrWrite].opcode == 38 ? 6 : (pipeline[plPtrWrite].opcode == PIPELINE_STALL ? 0 : 2)); +//WriteLog("[DSP_PC1=%08X, DSP_PC2=%08X]\n", ctrl1[0], ppc); +// if (ctrl1[0] < ppc) // P ran ahead of NP +//How to test this crap??? +// if (1) + { + DSPExecP2(1); // Do one more instruction + + // Save vars + memcpy(ram2, dsp_ram_8, 0x2000); + memcpy(regs2, dsp_reg_bank_0, 32 * 4); + memcpy(®s2[32], dsp_reg_bank_1, 32 * 4); + ctrl2[0] = dsp_pc; + ctrl2[1] = dsp_acc; + ctrl2[2] = dsp_remain; + ctrl2[3] = dsp_modulo; + ctrl2[4] = dsp_flags; + ctrl2[5] = dsp_matrix_control; + ctrl2[6] = dsp_pointer_to_matrix; + ctrl2[7] = dsp_data_organization; + ctrl2[8] = dsp_control; + ctrl2[9] = dsp_div_control; + ctrl2[10] = IMASKCleared; + ctrl2[11] = dsp_flag_z; + ctrl2[12] = dsp_flag_n; + ctrl2[13] = dsp_flag_c; + } +// else // NP ran ahead of P + if (instr1 != lastExec) // Must be the other way... + + { + // Load up vars for non-pipelined core + memcpy(dsp_ram_8, ram1, 0x2000); + memcpy(dsp_reg_bank_0, regs1, 32 * 4); + memcpy(dsp_reg_bank_1, ®s1[32], 32 * 4); + dsp_pc = ctrl1[0]; + dsp_acc = ctrl1[1]; + dsp_remain = ctrl1[2]; + dsp_modulo = ctrl1[3]; + dsp_flags = ctrl1[4]; + dsp_matrix_control = ctrl1[5]; + dsp_pointer_to_matrix = ctrl1[6]; + dsp_data_organization = ctrl1[7]; + dsp_control = ctrl1[8]; + dsp_div_control = ctrl1[9]; + IMASKCleared = ctrl1[10]; + dsp_flag_z = ctrl1[11]; + dsp_flag_n = ctrl1[12]; + dsp_flag_c = ctrl1[13]; +DSPUpdateRegisterBanks(); + +for(int k=0; k<2; k++) +{ + // Decrement cycles based on non-pipelined core... + instr1 = DSPReadWord(dsp_pc, DSP); + cycles -= dsp_opcode_cycles[instr1 >> 10]; + +//WriteLog("\tAbout to execute non-pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32)count, dsp_pc); + DSPExec(1); // Do *one* instruction +} + + // Save vars + memcpy(ram1, dsp_ram_8, 0x2000); + memcpy(regs1, dsp_reg_bank_0, 32 * 4); + memcpy(®s1[32], dsp_reg_bank_1, 32 * 4); + ctrl1[0] = dsp_pc; + ctrl1[1] = dsp_acc; + ctrl1[2] = dsp_remain; + ctrl1[3] = dsp_modulo; + ctrl1[4] = dsp_flags; + ctrl1[5] = dsp_matrix_control; + ctrl1[6] = dsp_pointer_to_matrix; + ctrl1[7] = dsp_data_organization; + ctrl1[8] = dsp_control; + ctrl1[9] = dsp_div_control; + ctrl1[10] = IMASKCleared; + ctrl1[11] = dsp_flag_z; + ctrl1[12] = dsp_flag_n; + ctrl1[13] = dsp_flag_c; + } + } + + if (instr1 != lastExec) + { + WriteLog("\nCores diverged at instruction tick #%u!\nStopped!\n\n", count); + + WriteLog("Instruction for non-pipelined core: %04X\n", instr1); + WriteLog("Instruction for pipelined core: %04X\n", lastExec); + + log_done(); + exit(1); + } + + count++; + } } +#endif + // // DSP execution core // -static bool R20Set = false, tripwire = false; -static uint32 pcQueue[32], ptrPCQ = 0; +//static bool R20Set = false, tripwire = false; +//static uint32 pcQueue[32], ptrPCQ = 0; void DSPExec(int32 cycles) { /*HACKS!!! -> if (cycles != 1 && jaguar_mainRom_crc32 == 0xba74c3ed) @@ -1037,6 +1669,30 @@ void DSPExec(int32 cycles) while (cycles > 0 && DSP_RUNNING) { +/*extern uint32 totalFrames; +//F1B2F6: LOAD (R14+$04), R24 [NCZ:001, R14+$04=00F20018, R24=FFFFFFFF] -> Jaguar: Unknown word read at 00F20018 by DSP (M68K PC=00E32E) +//-> 43 + 1 + 24 -> $2B + $01 + $18 -> 101011 00001 11000 -> 1010 1100 0011 1000 -> AC38 +//C470 -> 1100 0100 0111 0000 -> 110001 00011 10000 -> 49, 3, 16 -> STORE R16, (R14+$0C) +//F1B140: +if (totalFrames >= 377 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38 && dsp_pc == 0xF1B140) +{ + doDSPDis = true; + WriteLog("Starting disassembly at frame #%u...\n", totalFrames); +} +if (dsp_pc == 0xF1B092) + doDSPDis = false;//*/ +/*if (dsp_pc == 0xF1B140) + doDSPDis = true;//*/ + + if (IMASKCleared) // If IMASK was cleared, + { +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Finished interrupt.\n"); +#endif + DSPHandleIRQsNP(); // See if any other interrupts are pending! + IMASKCleared = false; + } + /*if (badWrite) { WriteLog("\nDSP: Encountered bad write in Atari Synth module. PC=%08X, R15=%08X\n", dsp_pc, dsp_reg[15]); @@ -1101,7 +1757,7 @@ if ((dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFE) && !tripwire) static void dsp_opcode_jump(void) { #ifdef DSP_DIS_JUMP -char * condition[32] = +const char * condition[32] = { "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", "c z", "???", "???", "???", "???", "???", "???", "???", "???", "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", @@ -1136,7 +1792,7 @@ char * condition[32] = static void dsp_opcode_jr(void) { #ifdef DSP_DIS_JR -char * condition[32] = +const char * condition[32] = { "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", "c z", "???", "???", "???", "???", "???", "???", "???", "???", "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", @@ -1175,7 +1831,7 @@ static void dsp_opcode_add(void) if (doDSPDis) WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif - UINT32 res = RN + RM; + uint32 res = RN + RM; SET_ZNC_ADD(RN, RM, res); RN = res; #ifdef DSP_DIS_ADD @@ -1190,8 +1846,8 @@ static void dsp_opcode_addc(void) if (doDSPDis) WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif - UINT32 res = RN + RM + dsp_flag_c; - UINT32 carry = dsp_flag_c; + uint32 res = RN + RM + dsp_flag_c; + uint32 carry = dsp_flag_c; // SET_ZNC_ADD(RN, RM, res); //???BUG??? Yes! SET_ZNC_ADD(RN + carry, RM, res); // SET_ZNC_ADD(RN, RM + carry, res); @@ -1208,8 +1864,8 @@ static void dsp_opcode_addq(void) if (doDSPDis) WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 r1 = dsp_convert_zero[IMM_1]; - UINT32 res = RN + r1; + uint32 r1 = dsp_convert_zero[IMM_1]; + uint32 res = RN + r1; CLR_ZNC; SET_ZNC_ADD(RN, r1, res); RN = res; #ifdef DSP_DIS_ADDQ @@ -1224,7 +1880,7 @@ static void dsp_opcode_sub(void) if (doDSPDis) WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif - UINT32 res = RN - RM; + uint32 res = RN - RM; SET_ZNC_SUB(RN, RM, res); RN = res; #ifdef DSP_DIS_SUB @@ -1239,8 +1895,8 @@ static void dsp_opcode_subc(void) if (doDSPDis) WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif - UINT32 res = RN - RM - dsp_flag_c; - UINT32 borrow = dsp_flag_c; + uint32 res = RN - RM - dsp_flag_c; + uint32 borrow = dsp_flag_c; SET_ZNC_SUB(RN - borrow, RM, res); RN = res; #ifdef DSP_DIS_SUBC @@ -1255,8 +1911,8 @@ static void dsp_opcode_subq(void) if (doDSPDis) WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 r1 = dsp_convert_zero[IMM_1]; - UINT32 res = RN - r1; + uint32 r1 = dsp_convert_zero[IMM_1]; + uint32 res = RN - r1; SET_ZNC_SUB(RN, r1, res); RN = res; #ifdef DSP_DIS_SUBQ @@ -1271,7 +1927,7 @@ static void dsp_opcode_cmp(void) if (doDSPDis) WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif - UINT32 res = RN - RM; + uint32 res = RN - RM; SET_ZNC_SUB(RN, RM, res); #ifdef DSP_DIS_CMP if (doDSPDis) @@ -1287,8 +1943,8 @@ static void dsp_opcode_cmpq(void) if (doDSPDis) WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, sqtable[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; - UINT32 res = RN - r1; + uint32 r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; + uint32 res = RN - r1; SET_ZNC_SUB(RN, r1, res); #ifdef DSP_DIS_CMPQ if (doDSPDis) @@ -1342,13 +1998,13 @@ static void dsp_opcode_not(void) { #ifdef DSP_DIS_NOT if (doDSPDis) - WriteLog("%06X: NOT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); + WriteLog("%06X: NOT R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif RN = ~RN; SET_ZN(RN); #ifdef DSP_DIS_NOT if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif } @@ -1363,7 +2019,11 @@ static void dsp_opcode_store_r14_indexed(void) if (doDSPDis) WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[14]+(dsp_convert_zero[IMM_1] << 2)); #endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + DSPWriteLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#else DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#endif } static void dsp_opcode_store_r15_indexed(void) @@ -1372,7 +2032,11 @@ static void dsp_opcode_store_r15_indexed(void) if (doDSPDis) WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[15]+(dsp_convert_zero[IMM_1] << 2)); #endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + DSPWriteLong((dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#else DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#endif } static void dsp_opcode_load_r14_ri(void) @@ -1381,7 +2045,11 @@ static void dsp_opcode_load_r14_ri(void) if (doDSPDis) WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM+dsp_reg[14], IMM_2, RN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[14] + RM) & 0xFFFFFFFC, DSP); +#else RN = DSPReadLong(dsp_reg[14] + RM, DSP); +#endif #ifdef DSP_DIS_LOAD14R if (doDSPDis) WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); @@ -1394,7 +2062,11 @@ static void dsp_opcode_load_r15_ri(void) if (doDSPDis) WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM+dsp_reg[15], IMM_2, RN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[15] + RM) & 0xFFFFFFFC, DSP); +#else RN = DSPReadLong(dsp_reg[15] + RM, DSP); +#endif #ifdef DSP_DIS_LOAD15R if (doDSPDis) WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); @@ -1437,10 +2109,17 @@ static void dsp_opcode_storew(void) if (doDSPDis) WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM); #endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + DSPWriteLong(RM & 0xFFFFFFFE, RN & 0xFFFF, DSP); + else + JaguarWriteWord(RM & 0xFFFFFFFE, RN, DSP); +#else if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) DSPWriteLong(RM, RN & 0xFFFF, DSP); else JaguarWriteWord(RM, RN, DSP); +#endif } static void dsp_opcode_store(void) @@ -1449,7 +2128,11 @@ static void dsp_opcode_store(void) if (doDSPDis) WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM); #endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + DSPWriteLong(RM & 0xFFFFFFFC, RN, DSP); +#else DSPWriteLong(RM, RN, DSP); +#endif } static void dsp_opcode_loadb(void) @@ -1474,10 +2157,17 @@ static void dsp_opcode_loadw(void) if (doDSPDis) WriteLog("%06X: LOADW (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + RN = DSPReadLong(RM & 0xFFFFFFFE, DSP) & 0xFFFF; + else + RN = JaguarReadWord(RM & 0xFFFFFFFE, DSP); +#else if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) RN = DSPReadLong(RM, DSP) & 0xFFFF; else RN = JaguarReadWord(RM, DSP); +#endif #ifdef DSP_DIS_LOADW if (doDSPDis) WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); @@ -1490,7 +2180,11 @@ static void dsp_opcode_load(void) if (doDSPDis) WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong(RM & 0xFFFFFFFC, DSP); +#else RN = DSPReadLong(RM, DSP); +#endif #ifdef DSP_DIS_LOAD if (doDSPDis) WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); @@ -1503,7 +2197,11 @@ static void dsp_opcode_load_r14_indexed(void) if (doDSPDis) WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1] << 2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[IMM_1] << 2, dsp_reg[14]+(dsp_convert_zero[IMM_1] << 2), IMM_2, RN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), DSP); +#else RN = DSPReadLong(dsp_reg[14] + (dsp_convert_zero[IMM_1] << 2), DSP); +#endif #ifdef DSP_DIS_LOAD14I if (doDSPDis) WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); @@ -1516,7 +2214,11 @@ static void dsp_opcode_load_r15_indexed(void) if (doDSPDis) WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1] << 2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[IMM_1] << 2, dsp_reg[15]+(dsp_convert_zero[IMM_1] << 2), IMM_2, RN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), DSP); +#else RN = DSPReadLong(dsp_reg[15] + (dsp_convert_zero[IMM_1] << 2), DSP); +#endif #ifdef DSP_DIS_LOAD15I if (doDSPDis) WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); @@ -1637,7 +2339,7 @@ static void dsp_opcode_bclr(void) if (doDSPDis) WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 res = RN & ~(1 << IMM_1); + uint32 res = RN & ~(1 << IMM_1); RN = res; SET_ZN(res); #ifdef DSP_DIS_BCLR @@ -1665,7 +2367,7 @@ static void dsp_opcode_bset(void) if (doDSPDis) WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 res = RN | (1 << IMM_1); + uint32 res = RN | (1 << IMM_1); RN = res; SET_ZN(res); #ifdef DSP_DIS_BSET @@ -1713,11 +2415,11 @@ static void dsp_opcode_imacn(void) if (doDSPDis) WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8)(dsp_acc >> 32), (uint32)(dsp_acc & 0xFFFFFFFF)); #endif -} +} static void dsp_opcode_mtoi(void) { - RN = (((INT32)RM >> 8) & 0xFF800000) | (RM & 0x007FFFFF); + RN = (((int32)RM >> 8) & 0xFF800000) | (RM & 0x007FFFFF); SET_ZN(RN); } @@ -1746,14 +2448,14 @@ static void dsp_opcode_normi(void) static void dsp_opcode_mmult(void) { int count = dsp_matrix_control&0x0f; - uint32 addr = dsp_pointer_to_matrix; // in the gpu ram + uint32 addr = dsp_pointer_to_matrix; // in the dsp ram int64 accum = 0; uint32 res; if (!(dsp_matrix_control & 0x10)) { for (int i = 0; i < count; i++) - { + { int16 a; if (i&0x01) a=(int16)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff); @@ -1786,9 +2488,13 @@ static void dsp_opcode_mmult(void) static void dsp_opcode_abs(void) { +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("%06X: ABS R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif uint32 _Rn = RN; uint32 res; - + if (_Rn == 0x80000000) dsp_flag_n = 1; else @@ -1797,6 +2503,10 @@ static void dsp_opcode_abs(void) res = RN = (_Rn & 0x80000000 ? -_Rn : _Rn); CLR_ZN; SET_Z(res); } +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif } static void dsp_opcode_div(void) @@ -1847,7 +2557,7 @@ static void dsp_opcode_neg(void) if (doDSPDis) WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 res = -RN; + uint32 res = -RN; SET_ZNC_SUB(0, RN, res); RN = res; #ifdef DSP_DIS_NEG @@ -1862,8 +2572,8 @@ static void dsp_opcode_shlq(void) if (doDSPDis) WriteLog("%06X: SHLQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, 32 - IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - INT32 r1 = 32 - IMM_1; - UINT32 res = RN << r1; + int32 r1 = 32 - IMM_1; + uint32 res = RN << r1; SET_ZN(res); dsp_flag_c = (RN >> 31) & 1; RN = res; #ifdef DSP_DIS_SHLQ @@ -1878,8 +2588,8 @@ static void dsp_opcode_shrq(void) if (doDSPDis) WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - INT32 r1 = dsp_convert_zero[IMM_1]; - UINT32 res = RN >> r1; + int32 r1 = dsp_convert_zero[IMM_1]; + uint32 res = RN >> r1; SET_ZN(res); dsp_flag_c = RN & 1; RN = res; #ifdef DSP_DIS_SHRQ @@ -1894,8 +2604,8 @@ static void dsp_opcode_ror(void) if (doDSPDis) WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); #endif - UINT32 r1 = RM & 0x1F; - UINT32 res = (RN >> r1) | (RN << (32 - r1)); + uint32 r1 = RM & 0x1F; + uint32 res = (RN >> r1) | (RN << (32 - r1)); SET_ZN(res); dsp_flag_c = (RN >> 31) & 1; RN = res; #ifdef DSP_DIS_ROR @@ -1910,9 +2620,9 @@ static void dsp_opcode_rorq(void) if (doDSPDis) WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 r1 = dsp_convert_zero[IMM_1 & 0x1F]; - UINT32 r2 = RN; - UINT32 res = (r2 >> r1) | (r2 << (32 - r1)); + uint32 r1 = dsp_convert_zero[IMM_1 & 0x1F]; + uint32 r2 = RN; + uint32 res = (r2 >> r1) | (r2 << (32 - r1)); RN = res; SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01; #ifdef DSP_DIS_RORQ @@ -1958,7 +2668,7 @@ static void dsp_opcode_sharq(void) if (doDSPDis) WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); #endif - UINT32 res = (INT32)RN >> dsp_convert_zero[IMM_1]; + uint32 res = (int32)RN >> dsp_convert_zero[IMM_1]; SET_ZN(res); dsp_flag_c = RN & 0x01; RN = res; #ifdef DSP_DIS_SHARQ @@ -2004,9 +2714,9 @@ void dsp_opcode_addqmod(void) if (doDSPDis) WriteLog("%06X: ADDQMOD #%u, R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_MOD=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_modulo); #endif - UINT32 r1 = dsp_convert_zero[IMM_1]; - UINT32 r2 = RN; - UINT32 res = r2 + r1; + uint32 r1 = dsp_convert_zero[IMM_1]; + uint32 r2 = RN; + uint32 res = r2 + r1; res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); RN = res; SET_ZNC_ADD(r2, r1, res); @@ -2016,37 +2726,37 @@ void dsp_opcode_addqmod(void) #endif } -void dsp_opcode_subqmod(void) +void dsp_opcode_subqmod(void) { - UINT32 r1 = dsp_convert_zero[IMM_1]; - UINT32 r2 = RN; - UINT32 res = r2 - r1; + uint32 r1 = dsp_convert_zero[IMM_1]; + uint32 r2 = RN; + uint32 res = r2 - r1; res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); RN = res; - + SET_ZNC_SUB(r2, r1, res); } -void dsp_opcode_mirror(void) +void dsp_opcode_mirror(void) { - UINT32 r1 = RN; + uint32 r1 = RN; RN = (mirror_table[r1 & 0xFFFF] << 16) | mirror_table[r1 >> 16]; SET_ZN(RN); } -void dsp_opcode_sat32s(void) +void dsp_opcode_sat32s(void) { - INT32 r2 = (UINT32)RN; - INT32 temp = dsp_acc >> 32; - UINT32 res = (temp < -1) ? (INT32)0x80000000 : (temp > 0) ? (INT32)0x7FFFFFFF : r2; + int32 r2 = (uint32)RN; + int32 temp = dsp_acc >> 32; + uint32 res = (temp < -1) ? (int32)0x80000000 : (temp > 0) ? (int32)0x7FFFFFFF : r2; RN = res; SET_ZN(res); } -void dsp_opcode_sat16s(void) +void dsp_opcode_sat16s(void) { - INT32 r2 = RN; - UINT32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2; + int32 r2 = RN; + uint32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2; RN = res; SET_ZN(res); } @@ -2059,7 +2769,7 @@ static void DSP_abs(void); static void DSP_add(void); static void DSP_addc(void); static void DSP_addq(void); -static void DSP_addqmod(void); +static void DSP_addqmod(void); static void DSP_addqt(void); static void DSP_and(void); static void DSP_bclr(void); @@ -2081,7 +2791,7 @@ static void DSP_load_r14_i(void); static void DSP_load_r14_r(void); static void DSP_load_r15_i(void); static void DSP_load_r15_r(void); -static void DSP_mirror(void); +static void DSP_mirror(void); static void DSP_mmult(void); static void DSP_move(void); static void DSP_movefa(void); @@ -2099,8 +2809,8 @@ static void DSP_or(void); static void DSP_resmac(void); static void DSP_ror(void); static void DSP_rorq(void); -static void DSP_sat16s(void); -static void DSP_sat32s(void); +static void DSP_sat16s(void); +static void DSP_sat32s(void); static void DSP_sh(void); static void DSP_sha(void); static void DSP_sharq(void); @@ -2116,12 +2826,12 @@ static void DSP_store_r15_r(void); static void DSP_sub(void); static void DSP_subc(void); static void DSP_subq(void); -static void DSP_subqmod(void); +static void DSP_subqmod(void); static void DSP_subqt(void); static void DSP_xor(void); void (* DSPOpcode[64])() = -{ +{ DSP_add, DSP_addc, DSP_addq, DSP_addqt, DSP_sub, DSP_subc, DSP_subq, DSP_subqt, DSP_neg, DSP_and, DSP_or, DSP_xor, @@ -2166,48 +2876,21 @@ bool readAffected[64][2] = { true, true}, { true, true}, {false, false}, {false, true} }; -bool affectsScoreboard[64] = +bool isLoadStore[65] = { - true, true, true, true, - true, true, true, true, - true, true, true, true, - true, false, true, true, + false, false, false, false, false, false, false, false, + false, false, false, false, false, false, false, false, - true, true, false, true, - false, true, true, true, - true, true, true, true, - true, true, false, false, + false, false, false, false, false, false, false, false, + false, false, false, false, false, false, false, false, - true, true, true, true, - false, true, true, true, - true, true, true, true, - true, false, false, false, - - true, false, false, true, - false, false, true, true, - true, false, true, true, - false, false, false, true -}; - -// Pipeline structures + false, false, false, false, false, false, false, true, + true, true, false, true, true, true, true, true, -struct PipelineStage -{ - uint16 instruction; - uint8 opcode, operand1, operand2; - uint32 reg1, reg2, areg1, areg2; - uint32 result; - uint8 writebackRegister; + false, true, true, false, false, false, false, false, + false, false, true, true, true, true, false, false, false }; -bool scoreboard[32]; - -uint8 plPtrFetch, plPtrRead, plPtrExec, plPtrWrite; - -#define PIPELINE_STALL 64 // Set to # of opcodes + 1 - -PipelineStage pipeline[4]; - void FlushDSPPipeline(void) { plPtrFetch = 3, plPtrRead = 2, plPtrExec = 1, plPtrWrite = 0; @@ -2216,13 +2899,13 @@ void FlushDSPPipeline(void) pipeline[i].opcode = PIPELINE_STALL; for(int i=0; i<32; i++) - scoreboard[i] = false; + scoreboard[i] = 0; } // // New pipelined DSP execution core // -void DSPExecP(int32 cycles) +/*void DSPExecP(int32 cycles) { // bool inhibitFetch = false; @@ -2263,8 +2946,7 @@ WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipel // Stage 2: Read registers //Ok, stalls here depend on whether or not the instruction reads two registers or not //and *which* register (1 or 2) is the one being read... !!! FIX !!! - if ((/*scoreboard[pipeline[plPtrRead].operand1] - ||*/ scoreboard[pipeline[plPtrRead].operand2]) + if (scoreboard[pipeline[plPtrRead].operand2]) && pipeline[plPtrRead].opcode != PIPELINE_STALL) // We have a hit in the scoreboard, so we have to stall the pipeline... { @@ -2283,26 +2965,12 @@ WriteLog(" --> Stalling pipeline: scoreboard = %s\n", scoreboard[pipeline[plPtr if (pipeline[plPtrRead].opcode != PIPELINE_STALL) // Shouldn't we be more selective with the register scoreboarding? // Yes, we should. !!! FIX !!! -// scoreboard[pipeline[plPtrRead].operand1] - /*=*/ scoreboard[pipeline[plPtrRead].operand2] = true; + scoreboard[pipeline[plPtrRead].operand2] = true; //Advance PC here??? Yes. // dsp_pc += (pipeline[plPtrRead].opcode == 38 ? 6 : 2); //This is a mangling of the pipeline stages, but what else to do??? dsp_pc += (pipeline[plPtrFetch].opcode == 38 ? 6 : 2); } -/* -DSPExecP: Pipeline status (after stage 1)... - F -> 52, 00, 00; r1=00000000, r2= 00000000, res=00000000, wb=0 - R -> 38, 00, 00; r1=00000000, r2= 00000000, res=00F1B034, wb=0 - E -> 64, 00, 00; r1=00000000, r2= 00000000, res=00000000, wb=0 - W -> 64, 00, 00; r1=00000000, r2= 00000000, res=00000000, wb=0 - --> Stalling pipeline: scoreboard = true -DSPExecP: Pipeline status (after stage 2)... - F -> 52, 00, 00; r1=00000000, r2= 00000000, res=00000000, wb=0 - R -> 64, 00, 00; r1=00000000, r2= 00000000, res=00F1B034, wb=0 - E -> 64, 00, 00; r1=00000000, r2= 00000000, res=00000000, wb=0 - W -> 64, 00, 00; r1=00000000, r2= 00000000, res=00000000, wb=0 */ - WriteLog("DSPExecP: Pipeline status (after stage 2)...\n"); WriteLog("\tF -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrFetch].opcode, pipeline[plPtrFetch].operand1, pipeline[plPtrFetch].operand2, pipeline[plPtrFetch].reg1, pipeline[plPtrFetch].reg2, pipeline[plPtrFetch].result, pipeline[plPtrFetch].writebackRegister); @@ -2343,12 +3011,166 @@ WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipel } dsp_in_exec--; -} +}*/ + + +//Problems: JR and any other instruction that relies on DSP_PC is getting WRONG values! +//!!! FIX !!! +// Should be fixed now. Another problem is figuring how to do the sequence following +// a branch followed with the JR & JUMP instructions... +// +// There are two conflicting problems: + +/* +F1B236: LOAD (R31), R03 [NCZ:000, R31=00F1CFDC, R03=00F14000] -> [NCZ:000, R03=00F1B084] +F1B238: BCLR #3, R00 [NCZ:000, R00=00004039] -> [NCZ:000, R00=00004031] +F1B23A: ADDQ #2, R03 [NCZ:000, R03=00F1B084] -> [NCZ:000, R03=00F1B086] +F1B23C: SUBQ #1, R17 [NCZ:000, R17=00000040] -> [NCZ:000, R17=0000003F] +F1B23E: MOVEI #$00F1CFE0, R31 [NCZ:000, R31=00F1CFDC] -> [NCZ:000, R31=00F1CFE0] +F1B244: JR z, F1B254 [NCZ:000] Branch NOT taken. +F1B246: BSET #10, R00 [NCZ:000, R00=00004031] -> [NCZ:000, R00=00004431] +F1B248: MOVEI #$00F1A100, R01 [NCZ:000, R01=00F1A148] -> [NCZ:000, R01=00F1A100] +F1B24E: STORE R00, (R01) [NCZ:000, R00=00004431, R01=00F1A100] +DSP: Writing 00004431 to DSP_FLAGS by DSP... +DSP: Finished interrupt. +; Without pipeline effects, the value in R03 is erroneously read from bank 1 instead of +; bank 0 (where is was prepared)! +F1B250: JUMP T, (R03) [NCZ:001, R03=00000000] Branched! +F1B252: NOP [NCZ:001] +*/ + +// The other is when you see this at the end of an IRQ: + +/* +JUMP T, (R29) ; R29 = Previous stack + 2 +STORE R28, (R30) ; R28 = Modified flags register, R30 = $F1A100 + +; Actually, this is OK if we do the atomic JUMP/JR operation correctly: +; 1) The STORE goes through the pipeline and is executed/written back +; 2) The pipeline is flushed +; 3) The DSP_PC is set to the new address +; 4) Execution resumes + +JUMP T, (R25) ; Oops! Because of pipeline effects R25 has the value from + ; bank 0 instead of the current bank 1 and so goes astray! +*/ + +//One other thing: Since these stages are supposed to happen simulaneously, try executing +//them in reverse order to see if that reduces pipeline stalls from late writebacks... +/* +Small problem here: The return address when INT0 comes up is $F1B088, but when INT1 +follows it, the JUMP out of the previous interrupt is bypassed immediately--this is +because the STORE instruction writes back on stage #2 of the pipeline instead of stage #3... +If it were done properly, the STORE write back would occur *after* (well, technically, +during) the execution of the the JUMP that follows it. + +!!! FIX !!! [DONE] + +F1B08A: JR z, F1B082 [NCZ:001] Branched! +F1B08A: NOP [NCZ:001] +[STALL...] +F1B080: MOVEI #$00F1B178, R00 [NCZ:001, R00=00F1B178] -> [NCZ:001, R00=00F1B178] +[STALL...] +[STALL...] +F1B086: LOAD (R00), R01 [NCZ:001, R00=00F1B178, R01=00000000] -> [NCZ:001, R01=00000000] +[STALL...] +[STALL...] +F1B088: OR R01, R01 [NCZ:001, R01=00000000, R01=00000000] -> [NCZ:001, R01=00000000, R01=00000000] +F1B08A: JR z, F1B082 [NCZ:001] Branched! +F1B08A: NOP [NCZ:001] +[STALL...] +F1B080: MOVEI #$00F1B178, R00 [NCZ:001, R00=00F1B178] -> [NCZ:001, R00=00F1B178] +[STALL...] +[STALL...] +Write to DSP CTRL: 00002301 --> Starting to run at 00F1B088 by M68K... +DSP: CPU -> DSP interrupt +DSP: Generating interrupt #0... [PC will return to 00F1B088, R31 = 00F1CFE0] +Write to DSP CTRL: 00000001 --> Starting to run at 00F1B000 by M68K... +[STALL...] +F1B000: MOVEI #$00F1B0D4, R30 [NCZ:001, R30=00F1B000] -> [NCZ:001, R30=00F1B0D4] +[STALL...] +[STALL...] +F1B006: JUMP T, (R30) [NCZ:001, R30=00F1B0D4] Branched! +F1B006: NOP [NCZ:001] +[STALL...] +F1B0D4: MOVEI #$00F1A100, R01 [NCZ:001, R01=00F1A100] -> [NCZ:001, R01=00F1A100] +[STALL...] +[STALL...] +F1B0DA: LOAD (R01), R00 [NCZ:001, R01=00F1A100, R00=00004431] -> [NCZ:001, R00=00004039] +F1B0DC: MOVEI #$00F1B0C8, R01 [NCZ:001, R01=00F1A100] -> [NCZ:001, R01=00F1B0C8] +[STALL...] +[STALL...] +F1B0E2: LOAD (R01), R02 [NCZ:001, R01=00F1B0C8, R02=00000000] -> [NCZ:001, R02=00000001] +F1B0E4: MOVEI #$00F1B0CC, R01 [NCZ:001, R01=00F1B0C8] -> [NCZ:001, R01=00F1B0CC] +[STALL...] +[STALL...] +F1B0EA: LOAD (R01), R03 [NCZ:001, R01=00F1B0CC, R03=00F1B086] -> [NCZ:001, R03=00000064] +F1B0EC: MOVEI #$00F1B0D0, R01 [NCZ:001, R01=00F1B0CC] -> [NCZ:001, R01=00F1B0D0] +[STALL...] +[STALL...] +F1B0F2: LOAD (R01), R04 [NCZ:001, R01=00F1B0D0, R04=00000000] -> [NCZ:001, R04=00000008] +F1B0F4: MOVEI #$00F1B0BC, R01 [NCZ:001, R01=00F1B0D0] -> [NCZ:001, R01=00F1B0BC] +[STALL...] +[STALL...] +F1B0FA: ADD R04, R01 [NCZ:001, R04=00000008, R01=00F1B0BC] -> [NCZ:000, R04=00000008, R01=00F1B0C4] +[STALL...] +[STALL...] +F1B0FC: LOAD (R01), R01 [NCZ:000, R01=00F1B0C4, R01=00F1B0C4] -> [NCZ:000, R01=00F1B12E] +[STALL...] +[STALL...] +F1B0FE: JUMP T, (R01) [NCZ:000, R01=00F1B12E] Branched! +F1B0FE: NOP [NCZ:000] +[STALL...] +F1B12E: MOVE R02, R08 [NCZ:000, R02=00000001, R08=00000000] -> [NCZ:000, R02=00000001, R08=00000001] +[STALL...] +[STALL...] +F1B132: MOVEI #$00F1B102, R01 [NCZ:000, R01=00F1B12E] -> [NCZ:000, R01=00F1B102] +[STALL...] +[STALL...] +F1B138: JUMP T, (R01) [NCZ:000, R01=00F1B102] Branched! +F1B138: NOP [NCZ:000] +[STALL...] +F1B102: MOVEI #$00F1B0C8, R01 [NCZ:000, R01=00F1B102] -> [NCZ:000, R01=00F1B0C8] +[STALL...] +[STALL...] +F1B108: STORE R08, (R01) [NCZ:000, R08=00000000, R01=00F1B0C8] +F1B10A: MOVEI #$00F1B0D0, R01 [NCZ:000, R01=00F1B0C8] -> [NCZ:000, R01=00F1B0D0] +F1B110: MOVEQ #0, R04 [NCZ:000, R04=00000008] -> [NCZ:000, R04=00000000] +[STALL...] +[STALL...] +F1B112: STORE R04, (R01) [NCZ:000, R04=00000000, R01=00F1B0D0] +F1B114: BCLR #3, R00 [NCZ:000, R00=00004039] -> [NCZ:000, R00=00004031] +[STALL...] +[STALL...] +F1B116: BSET #9, R00 [NCZ:000, R00=00004031] -> [NCZ:000, R00=00004231] +F1B118: LOAD (R31), R04 [NCZ:000, R31=00F1CFDC, R04=00000000] -> [NCZ:000, R04=00F1B086] +F1B11A: MOVEI #$00F1CFE0, R31 [NCZ:000, R31=00F1CFDC] -> [NCZ:000, R31=00F1CFE0] +[STALL...] +F1B120: ADDQ #2, R04 [NCZ:000, R04=00F1B086] -> [NCZ:000, R04=00F1B088] +F1B122: MOVEI #$00F1A100, R01 [NCZ:000, R01=00F1B0D0] -> [NCZ:000, R01=00F1A100] +[STALL...] +[STALL...] +F1B128: STORE R00, (R01) [NCZ:000, R00=00004231, R01=00F1A100] +DSP: Writing 00004231 to DSP_FLAGS by DSP (REGPAGE is set)... +DSP: Finished interrupt. +DSP: Generating interrupt #1... [PC will return to 00F1B12A, R31 = 00F1CFE0] +[STALL...] +F1B010: MOVEI #$00F1B1FC, R30 [NCZ:001, R30=00F1B010] -> [NCZ:001, R30=00F1B1FC] +[STALL...] +[STALL...] +F1B016: JUMP T, (R30) [NCZ:001, R30=00F1B1FC] Branched! +F1B016: NOP [NCZ:001] +[STALL...] +F1B1FC: MOVEI #$00F1A100, R01 [NCZ:001, R01=00F1A100] -> [NCZ:001, R01=00F1A100] +*/ -#define DSP_DEBUG_PL2 +uint32 pcQueue1[0x400]; +uint32 pcQPtr1 = 0; +static uint32 prevR1; //Let's try a 3 stage pipeline.... +//Looks like 3 stage is correct, otherwise bad things happen... void DSPExecP2(int32 cycles) { dsp_releaseTimeSlice_flag = 0; @@ -2356,15 +3178,77 @@ void DSPExecP2(int32 cycles) while (cycles > 0 && DSP_RUNNING) { +/*extern uint32 totalFrames; +//F1B2F6: LOAD (R14+$04), R24 [NCZ:001, R14+$04=00F20018, R24=FFFFFFFF] -> Jaguar: Unknown word read at 00F20018 by DSP (M68K PC=00E32E) +//-> 43 + 1 + 24 -> $2B + $01 + $18 -> 101011 00001 11000 -> 1010 1100 0011 1000 -> AC38 +//C470 -> 1100 0100 0111 0000 -> 110001 00011 10000 -> 49, 3, 16 -> STORE R16, (R14+$0C) +//F1B140: +if (totalFrames >= 377 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38 && dsp_pc == 0xF1B140) +{ + doDSPDis = true; + WriteLog("Starting disassembly at frame #%u...\n", totalFrames); +} +if (dsp_pc == 0xF1B092) + doDSPDis = false;//*/ +/*if (totalFrames >= 373 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38) + doDSPDis = true;//*/ +/*if (totalFrames >= 373 && dsp_pc == 0xF1B0A0) + doDSPDis = true;//*/ +/*if (dsp_pc == 0xF1B0A0) + doDSPDis = true;//*/ +/*if (dsp_pc == 0xF1B0D2) && dsp_reg[1] == 0x2140C) + doDSPDis = true;//*/ +//Two parter... (not sure how to write this) +//if (dsp_pc == 0xF1B0D2) +// prevR1 = dsp_reg[1]; + +//F1B0D2: ADDQT #8, R01 [NCZ:000, R01=0002140C] -> [NCZ:000, R01=00021414] +//F1B0D2: ADDQT #8, R01 [NCZ:000, R01=0002140C] -> [NCZ:000, R01=00021414] + + +pcQueue1[pcQPtr1++] = dsp_pc; +pcQPtr1 &= 0x3FF; + #ifdef DSP_DEBUG_PL2 -WriteLog("DSPExecP: Pipeline status...\n"); -WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); -WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); -WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); +if ((dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFF) && !doDSPDis) +{ + WriteLog("DSP: PC has stepped out of bounds...\n\nBacktrace:\n\n"); + doDSPDis = true; + + char buffer[512]; + + for(int i=0; i<0x400; i++) + { + dasmjag(JAGUAR_DSP, buffer, pcQueue1[(i + pcQPtr1) & 0x3FF]); + WriteLog("\t%08X: %s\n", pcQueue1[(i + pcQPtr1) & 0x3FF], buffer); + } + WriteLog("\n"); +}//*/ +#endif + + if (IMASKCleared) // If IMASK was cleared, + { +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Finished interrupt.\n"); +#endif + DSPHandleIRQs(); // See if any other interrupts are pending! + IMASKCleared = false; + } + +//if (dsp_flags & REGPAGE) +// WriteLog(" --> REGPAGE has just been set!\n"); +#ifdef DSP_DEBUG_PL2 +if (doDSPDis) +{ +WriteLog("DSPExecP: Pipeline status [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); WriteLog(" --> Scoreboard: "); for(int i=0; i<32; i++) WriteLog("%s ", scoreboard[i] ? "T" : "F"); WriteLog("\n"); +} #endif // Stage 1a: Instruction fetch pipeline[plPtrRead].instruction = DSPReadWord(dsp_pc, DSP); @@ -2375,18 +3259,40 @@ WriteLog("\n"); pipeline[plPtrRead].result = (uint32)DSPReadWord(dsp_pc + 2, DSP) | ((uint32)DSPReadWord(dsp_pc + 4, DSP) << 16); #ifdef DSP_DEBUG_PL2 +if (doDSPDis) +{ WriteLog("DSPExecP: Fetching instruction (%04X) from DSP_PC = %08X...\n", pipeline[plPtrRead].instruction, dsp_pc); -WriteLog("DSPExecP: Pipeline status (after stage 1a)...\n"); -WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); -WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); -WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); +WriteLog("DSPExecP: Pipeline status (after stage 1a) [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +} #endif // Stage 1b: Read registers - if (scoreboard[pipeline[plPtrRead].operand2]) +//Small problem--when say LOAD or STORE (R14/5+$nn) is executed AFTER an instruction that +//modifies R14/5, we don't check the scoreboard for R14/5 (and we need to!)... !!! FIX !!! +//Ugly, but [DONE] +//Another problem: Any sequential combination of LOAD and STORE operations will cause the +//pipeline to stall, and we don't take care of that here. !!! FIX !!! + if ((scoreboard[pipeline[plPtrRead].operand1] && readAffected[pipeline[plPtrRead].opcode][0]) + || (scoreboard[pipeline[plPtrRead].operand2] && readAffected[pipeline[plPtrRead].opcode][1]) + || ((pipeline[plPtrRead].opcode == 43 || pipeline[plPtrRead].opcode == 58) && scoreboard[14]) + || ((pipeline[plPtrRead].opcode == 44 || pipeline[plPtrRead].opcode == 59) && scoreboard[15]) +//Not sure that this is the best way to fix the LOAD/STORE problem... But it seems to +//work--somewhat... + || (isLoadStore[pipeline[plPtrRead].opcode] && isLoadStore[pipeline[plPtrExec].opcode])) // We have a hit in the scoreboard, so we have to stall the pipeline... #ifdef DSP_DEBUG_PL2 { -WriteLog(" --> Stalling pipeline: scoreboard[%u] = %s\n", pipeline[plPtrRead].operand2, scoreboard[pipeline[plPtrRead].operand2] ? "true" : "false"); +if (doDSPDis) +{ +WriteLog(" --> Stalling pipeline: "); +if (readAffected[pipeline[plPtrRead].opcode][0]) + WriteLog("scoreboard[%u] = %s (reg 1) ", pipeline[plPtrRead].operand1, scoreboard[pipeline[plPtrRead].operand1] ? "true" : "false"); +if (readAffected[pipeline[plPtrRead].opcode][1]) + WriteLog("scoreboard[%u] = %s (reg 2)", pipeline[plPtrRead].operand2, scoreboard[pipeline[plPtrRead].operand2] ? "true" : "false"); +WriteLog("\n"); +} #endif pipeline[plPtrRead].opcode = PIPELINE_STALL; #ifdef DSP_DEBUG_PL2 @@ -2399,47 +3305,109 @@ WriteLog(" --> Stalling pipeline: scoreboard[%u] = %s\n", pipeline[plPtrRead].o pipeline[plPtrRead].writebackRegister = pipeline[plPtrRead].operand2; // Set it to RN // Shouldn't we be more selective with the register scoreboarding? - // Yes, we should. !!! FIX !!! [Kinda DONE] + // Yes, we should. !!! FIX !!! Kinda [DONE] +#ifndef NEW_SCOREBOARD scoreboard[pipeline[plPtrRead].operand2] = affectsScoreboard[pipeline[plPtrRead].opcode]; +#else +//Hopefully this will fix the dual MOVEQ # problem... + scoreboard[pipeline[plPtrRead].operand2] += (affectsScoreboard[pipeline[plPtrRead].opcode] ? 1 : 0); +#endif //Advance PC here??? Yes. dsp_pc += (pipeline[plPtrRead].opcode == 38 ? 6 : 2); } #ifdef DSP_DEBUG_PL2 -WriteLog("DSPExecP: Pipeline status (after stage 1b)...\n"); -WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); -WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); -WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); +if (doDSPDis) +{ +WriteLog("DSPExecP: Pipeline status (after stage 1b) [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +} #endif // Stage 2: Execute if (pipeline[plPtrExec].opcode != PIPELINE_STALL) { #ifdef DSP_DEBUG_PL2 +if (doDSPDis) + WriteLog("\t[inst=%02u][R28=%08X, alt R28=%08X, REGPAGE=%s]\n", pipeline[plPtrExec].opcode, dsp_reg[28], dsp_alternate_reg[28], (dsp_flags & REGPAGE ? "set" : "not set")); + +if (doDSPDis) +{ WriteLog("DSPExecP: About to execute opcode %s...\n", dsp_opcode_str[pipeline[plPtrExec].opcode]); +} +#endif +//CC only! +#ifdef DSP_DEBUG_CC +lastExec = pipeline[plPtrExec].instruction; +//WriteLog("[lastExec = %04X]\n", lastExec); #endif - DSPOpcode[pipeline[plPtrExec].opcode](); - dsp_opcode_use[pipeline[plPtrExec].opcode]++; cycles -= dsp_opcode_cycles[pipeline[plPtrExec].opcode]; + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + DSPOpcode[pipeline[plPtrExec].opcode](); +//WriteLog(" --> Returned from execute. DSP_PC: %08X\n", dsp_pc); } else - cycles--; +{ +//Let's not, until we do the stalling correctly... +//But, we gotta while we're doing the comparison core...! +//Or do we? cycles--; +//Really, the whole thing is wrong. When the pipeline is correctly stuffed, most instructions +//will execute in one clock cycle (others, like DIV, will likely not). So, the challenge is +//to model this clock cycle behavior correctly... +//Also, the pipeline stalls too much--mostly because the transparent writebacks at stage 3 +//don't affect the reads at stage 1... +#ifdef DSP_DEBUG_STALL +if (doDSPDis) + WriteLog("[STALL... DSP_PC = %08X]\n", dsp_pc); +#endif +} #ifdef DSP_DEBUG_PL2 -WriteLog("DSPExecP: Pipeline status (after stage 2)...\n"); -WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); -WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); -WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); +if (doDSPDis) +{ +WriteLog("DSPExecP: Pipeline status (after stage 2) [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); WriteLog("\n"); +} #endif - // Stage 3: Write back register + // Stage 3: Write back register/memory address if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) { +/*if (pipeline[plPtrWrite].writebackRegister == 3 + && (pipeline[plPtrWrite].result < 0xF14000 || pipeline[plPtrWrite].result > 0xF1CFFF) + && !doDSPDis) +{ + WriteLog("DSP: Register R03 has stepped out of bounds...\n\n"); + doDSPDis = true; +}//*/ if (pipeline[plPtrWrite].writebackRegister != 0xFF) - dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } +#ifndef NEW_SCOREBOARD if (affectsScoreboard[pipeline[plPtrWrite].opcode]) scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif } // Push instructions through the pipeline... @@ -2452,10 +3420,9 @@ WriteLog("\n"); } -//Problems: JR and any other instruction that relies on DSP_PC is getting WRONG values! -//!!! FIX !!! -#define DSP_DEBUG_PL3 +/* +//#define DSP_DEBUG_PL3 //Let's try a 2 stage pipeline.... void DSPExecP3(int32 cycles) { @@ -2464,6 +3431,8 @@ void DSPExecP3(int32 cycles) while (cycles > 0 && DSP_RUNNING) { +//if (dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFF) +// doDSPDis = true; #ifdef DSP_DEBUG_PL3 WriteLog("DSPExecP: Pipeline status...\n"); WriteLog("\tF/R -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); @@ -2491,7 +3460,7 @@ WriteLog("\tE/W -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", if ((scoreboard[pipeline[plPtrRead].operand1] && readAffected[pipeline[plPtrRead].opcode][0]) || (scoreboard[pipeline[plPtrRead].operand2] && readAffected[pipeline[plPtrRead].opcode][1])) // We have a hit in the scoreboard, so we have to stall the pipeline... -#if 1//def DSP_DEBUG_PL3 +#ifdef DSP_DEBUG_PL3 { WriteLog(" --> Stalling pipeline: "); if (readAffected[pipeline[plPtrRead].opcode][0]) @@ -2501,7 +3470,7 @@ if (readAffected[pipeline[plPtrRead].opcode][1]) WriteLog("\n"); #endif pipeline[plPtrRead].opcode = PIPELINE_STALL; -#if 1//def DSP_DEBUG_PL3 +#ifdef DSP_DEBUG_PL3 } #endif else @@ -2555,11 +3524,10 @@ WriteLog("\n"); // Push instructions through the pipeline... plPtrRead = (++plPtrRead) & 0x03; plPtrExec = (++plPtrExec) & 0x03; -// plPtrWrite = (++plPtrWrite) & 0x03; } dsp_in_exec--; -} +}*/ // // DSP pipelined opcode handlers @@ -2572,11 +3540,18 @@ WriteLog("\n"); #define PRES pipeline[plPtrExec].result #define PWBR pipeline[plPtrExec].writebackRegister #define NO_WRITEBACK pipeline[plPtrExec].writebackRegister = 0xFF +//#define DSP_PPC dsp_pc - (pipeline[plPtrRead].opcode == 38 ? 6 : 2) - (pipeline[plPtrExec].opcode == 38 ? 6 : 2) +#define DSP_PPC dsp_pc - (pipeline[plPtrRead].opcode == 38 ? 6 : (pipeline[plPtrRead].opcode == PIPELINE_STALL ? 0 : 2)) - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)) +#define WRITEBACK_ADDR pipeline[plPtrExec].writebackRegister = 0xFE static void DSP_abs(void) { +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("%06X: ABS R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif uint32 _Rn = PRN; - + if (_Rn == 0x80000000) dsp_flag_n = 1; else @@ -2585,20 +3560,24 @@ static void DSP_abs(void) PRES = (_Rn & 0x80000000 ? -_Rn : _Rn); CLR_ZN; SET_Z(PRES); } +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif } static void DSP_add(void) { #ifdef DSP_DIS_ADD if (doDSPDis) - WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif - UINT32 res = PRN + PRM; + uint32 res = PRN + PRM; SET_ZNC_ADD(PRN, PRM, res); PRES = res; #ifdef DSP_DIS_ADD if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -2606,17 +3585,17 @@ static void DSP_addc(void) { #ifdef DSP_DIS_ADDC if (doDSPDis) - WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif - UINT32 res = PRN + PRM + dsp_flag_c; - UINT32 carry = dsp_flag_c; + uint32 res = PRN + PRM + dsp_flag_c; + uint32 carry = dsp_flag_c; // SET_ZNC_ADD(PRN, PRM, res); //???BUG??? Yes! SET_ZNC_ADD(PRN + carry, PRM, res); // SET_ZNC_ADD(PRN, PRM + carry, res); PRES = res; #ifdef DSP_DIS_ADDC if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -2624,15 +3603,15 @@ static void DSP_addq(void) { #ifdef DSP_DIS_ADDQ if (doDSPDis) - WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - UINT32 r1 = dsp_convert_zero[PIMM1]; - UINT32 res = PRN + r1; + uint32 r1 = dsp_convert_zero[PIMM1]; + uint32 res = PRN + r1; CLR_ZNC; SET_ZNC_ADD(PRN, r1, res); PRES = res; #ifdef DSP_DIS_ADDQ if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2640,17 +3619,17 @@ static void DSP_addqmod(void) { #ifdef DSP_DIS_ADDQMOD if (doDSPDis) - WriteLog("%06X: ADDQMOD #%u, R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_MOD=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_modulo); + WriteLog("%06X: ADDQMOD #%u, R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_MOD=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_modulo); #endif - UINT32 r1 = dsp_convert_zero[PIMM1]; - UINT32 r2 = PRN; - UINT32 res = r2 + r1; + uint32 r1 = dsp_convert_zero[PIMM1]; + uint32 r2 = PRN; + uint32 res = r2 + r1; res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); PRES = res; SET_ZNC_ADD(r2, r1, res); #ifdef DSP_DIS_ADDQMOD if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2658,12 +3637,12 @@ static void DSP_addqt(void) { #ifdef DSP_DIS_ADDQT if (doDSPDis) - WriteLog("%06X: ADDQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: ADDQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif PRES = PRN + dsp_convert_zero[PIMM1]; #ifdef DSP_DIS_ADDQT if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2671,13 +3650,13 @@ static void DSP_and(void) { #ifdef DSP_DIS_AND if (doDSPDis) - WriteLog("%06X: AND R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: AND R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif PRES = PRN & PRM; SET_ZN(PRES); #ifdef DSP_DIS_AND if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -2685,13 +3664,13 @@ static void DSP_bclr(void) { #ifdef DSP_DIS_BCLR if (doDSPDis) - WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif PRES = PRN & ~(1 << PIMM1); SET_ZN(PRES); #ifdef DSP_DIS_BCLR if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2699,13 +3678,13 @@ static void DSP_bset(void) { #ifdef DSP_DIS_BSET if (doDSPDis) - WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif PRES = PRN | (1 << PIMM1); SET_ZN(PRES); #ifdef DSP_DIS_BSET if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2713,7 +3692,7 @@ static void DSP_btst(void) { #ifdef DSP_DIS_BTST if (doDSPDis) - WriteLog("%06X: BTST #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: BTST #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif dsp_flag_z = (~PRN >> PIMM1) & 1; NO_WRITEBACK; @@ -2727,9 +3706,9 @@ static void DSP_cmp(void) { #ifdef DSP_DIS_CMP if (doDSPDis) - WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif - UINT32 res = PRN - PRM; + uint32 res = PRN - PRM; SET_ZNC_SUB(PRN, PRM, res); NO_WRITEBACK; #ifdef DSP_DIS_CMP @@ -2744,10 +3723,10 @@ static void DSP_cmpq(void) { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1 }; #ifdef DSP_DIS_CMPQ if (doDSPDis) - WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, sqtable[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, sqtable[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - UINT32 r1 = sqtable[PIMM1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; - UINT32 res = PRN - r1; + uint32 r1 = sqtable[PIMM1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; + uint32 res = PRN - r1; SET_ZNC_SUB(PRN, r1, res); NO_WRITEBACK; #ifdef DSP_DIS_CMPQ @@ -2785,7 +3764,7 @@ static void DSP_imacn(void) { #ifdef DSP_DIS_IMACN if (doDSPDis) - WriteLog("%06X: IMACN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: IMACN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif int32 res = (int16)PRM * (int16)PRN; dsp_acc += (int64)res; @@ -2795,19 +3774,19 @@ static void DSP_imacn(void) if (doDSPDis) WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8)(dsp_acc >> 32), (uint32)(dsp_acc & 0xFFFFFFFF)); #endif -} +} static void DSP_imult(void) { #ifdef DSP_DIS_IMULT if (doDSPDis) - WriteLog("%06X: IMULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: IMULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif PRES = (int16)PRN * (int16)PRM; SET_ZN(PRES); #ifdef DSP_DIS_IMULT if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -2815,7 +3794,7 @@ static void DSP_imultn(void) { #ifdef DSP_DIS_IMULTN if (doDSPDis) - WriteLog("%06X: IMULTN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: IMULTN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif // This is OK, since this multiply won't overflow 32 bits... int32 res = (int32)((int16)PRN * (int16)PRM); @@ -2832,7 +3811,7 @@ static void DSP_illegal(void) { #ifdef DSP_DIS_ILLEGAL if (doDSPDis) - WriteLog("%06X: ILLEGAL [NCZ:%u%u%u]\n", dsp_pc-2, dsp_flag_n, dsp_flag_c, dsp_flag_z); + WriteLog("%06X: ILLEGAL [NCZ:%u%u%u]\n", DSP_PPC, dsp_flag_n, dsp_flag_c, dsp_flag_z); #endif NO_WRITEBACK; } @@ -2840,16 +3819,19 @@ static void DSP_illegal(void) // There is a problem here with interrupt handlers the JUMP and JR instructions that // can cause trouble because an interrupt can occur *before* the instruction following the // jump can execute... !!! FIX !!! +// This can probably be solved by judicious coding in the pipeline execution core... +// And should be fixed now... static void DSP_jr(void) { #ifdef DSP_DIS_JR -char * condition[32] = +const char * condition[32] = { "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", "c z", "???", "???", "???", "???", "???", "???", "???", "???", "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", "???", "???", "???", "F" }; if (doDSPDis) - WriteLog("%06X: JR %s, %06X [NCZ:%u%u%u] ", dsp_pc-2, condition[PIMM2], dsp_pc+((PIMM1 & 0x10 ? 0xFFFFFFF0 | PIMM1 : PIMM1) * 2), dsp_flag_n, dsp_flag_c, dsp_flag_z); +//How come this is always off by 2??? + WriteLog("%06X: JR %s, %06X [NCZ:%u%u%u] ", DSP_PPC, condition[PIMM2], DSP_PPC+((PIMM1 & 0x10 ? 0xFFFFFFF0 | PIMM1 : PIMM1) * 2)+2, dsp_flag_n, dsp_flag_c, dsp_flag_z); #endif // KLUDGE: Used by BRANCH_CONDITION macro uint32 jaguar_flags = (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; @@ -2861,28 +3843,104 @@ char * condition[32] = WriteLog("Branched!\n"); #endif int32 offset = (PIMM1 & 0x10 ? 0xFFFFFFF0 | PIMM1 : PIMM1); // Sign extend PIMM1 - int32 delayed_pc = dsp_pc + (offset * 2); -// DSPExec(1); - dsp_pc = delayed_pc; +//Account for pipeline effects... + uint32 newPC = dsp_pc + (offset * 2) - (pipeline[plPtrRead].opcode == 38 ? 6 : (pipeline[plPtrRead].opcode == PIPELINE_STALL ? 0 : 2)); +//WriteLog(" --> Old PC: %08X, new PC: %08X\n", dsp_pc, newPC); + + // Now that we've branched, we have to make sure that the following instruction + // is executed atomically with this one and then flush the pipeline before setting + // the new PC. + + // Step 1: Handle writebacks at stage 3 of pipeline +/* if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; + }//*/ + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } + +#ifndef NEW_SCOREBOARD + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif + } + + // Step 2: Push instruction through pipeline & execute following instruction + // NOTE: By putting our following instruction at stage 3 of the pipeline, + // we effectively handle the final push of the instruction through the + // pipeline when the new PC takes effect (since when we return, the + // pipeline code will be executing the writeback stage. If we reverse + // the execution order of the pipeline stages, this will no longer be + // the case!)... + pipeline[plPtrExec] = pipeline[plPtrRead]; +//This is BAD. We need to get that next opcode and execute it! +//NOTE: The problem is here because of a bad stall. Once those are fixed, we can probably +// remove this crap. + if (pipeline[plPtrExec].opcode == PIPELINE_STALL) + { + uint16 instruction = DSPReadWord(dsp_pc, DSP); + pipeline[plPtrExec].opcode = instruction >> 10; + pipeline[plPtrExec].operand1 = (instruction >> 5) & 0x1F; + pipeline[plPtrExec].operand2 = instruction & 0x1F; + pipeline[plPtrExec].reg1 = dsp_reg[pipeline[plPtrExec].operand1]; + pipeline[plPtrExec].reg2 = dsp_reg[pipeline[plPtrExec].operand2]; + pipeline[plPtrExec].writebackRegister = pipeline[plPtrExec].operand2; // Set it to RN + }//*/ + dsp_pc += 2; // For DSP_DIS_* accuracy + DSPOpcode[pipeline[plPtrExec].opcode](); + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + pipeline[plPtrWrite] = pipeline[plPtrExec]; + + // Step 3: Flush pipeline & set new PC + pipeline[plPtrRead].opcode = pipeline[plPtrExec].opcode = PIPELINE_STALL; + dsp_pc = newPC; } -#ifdef DSP_DIS_JR else +#ifdef DSP_DIS_JR + { if (doDSPDis) WriteLog("Branch NOT taken.\n"); #endif - NO_WRITEBACK; + NO_WRITEBACK; +#ifdef DSP_DIS_JR + } +#endif +// WriteLog(" --> DSP_PC: %08X\n", dsp_pc); } static void DSP_jump(void) { #ifdef DSP_DIS_JUMP -char * condition[32] = +const char * condition[32] = { "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", "c z", "???", "???", "???", "???", "???", "???", "???", "???", "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", "???", "???", "???", "F" }; if (doDSPDis) - WriteLog("%06X: JUMP %s, (R%02u) [NCZ:%u%u%u, R%02u=%08X] ", dsp_pc-2, condition[PIMM2], PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM); + WriteLog("%06X: JUMP %s, (R%02u) [NCZ:%u%u%u, R%02u=%08X] ", DSP_PPC, condition[PIMM2], PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM); #endif // KLUDGE: Used by BRANCH_CONDITION macro uint32 jaguar_flags = (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; @@ -2893,29 +3951,105 @@ char * condition[32] = if (doDSPDis) WriteLog("Branched!\n"); #endif -// uint32 delayed_pc = PRM; -// DSPExec(1); -// dsp_pc = delayed_pc; - dsp_pc = PRM; + uint32 PCSave = PRM; + // Now that we've branched, we have to make sure that the following instruction + // is executed atomically with this one and then flush the pipeline before setting + // the new PC. + + // Step 1: Handle writebacks at stage 3 of pipeline +/* if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; + }//*/ + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } + +#ifndef NEW_SCOREBOARD + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif + } + + // Step 2: Push instruction through pipeline & execute following instruction + // NOTE: By putting our following instruction at stage 3 of the pipeline, + // we effectively handle the final push of the instruction through the + // pipeline when the new PC takes effect (since when we return, the + // pipeline code will be executing the writeback stage. If we reverse + // the execution order of the pipeline stages, this will no longer be + // the case!)... + pipeline[plPtrExec] = pipeline[plPtrRead]; +//This is BAD. We need to get that next opcode and execute it! +//Also, same problem in JR! +//NOTE: The problem is here because of a bad stall. Once those are fixed, we can probably +// remove this crap. + if (pipeline[plPtrExec].opcode == PIPELINE_STALL) + { + uint16 instruction = DSPReadWord(dsp_pc, DSP); + pipeline[plPtrExec].opcode = instruction >> 10; + pipeline[plPtrExec].operand1 = (instruction >> 5) & 0x1F; + pipeline[plPtrExec].operand2 = instruction & 0x1F; + pipeline[plPtrExec].reg1 = dsp_reg[pipeline[plPtrExec].operand1]; + pipeline[plPtrExec].reg2 = dsp_reg[pipeline[plPtrExec].operand2]; + pipeline[plPtrExec].writebackRegister = pipeline[plPtrExec].operand2; // Set it to RN + }//*/ + dsp_pc += 2; // For DSP_DIS_* accuracy + DSPOpcode[pipeline[plPtrExec].opcode](); + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + pipeline[plPtrWrite] = pipeline[plPtrExec]; + + // Step 3: Flush pipeline & set new PC + pipeline[plPtrRead].opcode = pipeline[plPtrExec].opcode = PIPELINE_STALL; + dsp_pc = PCSave; } -#ifdef DSP_DIS_JUMP else +#ifdef DSP_DIS_JUMP + { if (doDSPDis) WriteLog("Branch NOT taken.\n"); #endif - NO_WRITEBACK; + NO_WRITEBACK; +#ifdef DSP_DIS_JUMP + } +#endif } static void DSP_load(void) { #ifdef DSP_DIS_LOAD if (doDSPDis) - WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong(PRM & 0xFFFFFFFC, DSP); +#else PRES = DSPReadLong(PRM, DSP); +#endif #ifdef DSP_DIS_LOAD if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2923,7 +4057,7 @@ static void DSP_loadb(void) { #ifdef DSP_DIS_LOADB if (doDSPDis) - WriteLog("%06X: LOADB (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: LOADB (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) PRES = DSPReadLong(PRM, DSP) & 0xFF; @@ -2931,7 +4065,7 @@ static void DSP_loadb(void) PRES = JaguarReadByte(PRM, DSP); #ifdef DSP_DIS_LOADB if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2939,15 +4073,22 @@ static void DSP_loadw(void) { #ifdef DSP_DIS_LOADW if (doDSPDis) - WriteLog("%06X: LOADW (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: LOADW (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + PRES = DSPReadLong(PRM & 0xFFFFFFFE, DSP) & 0xFFFF; + else + PRES = JaguarReadWord(PRM & 0xFFFFFFFE, DSP); +#else if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) PRES = DSPReadLong(PRM, DSP) & 0xFFFF; else PRES = JaguarReadWord(PRM, DSP); +#endif #ifdef DSP_DIS_LOADW if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2955,12 +4096,16 @@ static void DSP_load_r14_i(void) { #ifdef DSP_DIS_LOAD14I if (doDSPDis) - WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[14]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN); + WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[14]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2), DSP); +#else PRES = DSPReadLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), DSP); +#endif #ifdef DSP_DIS_LOAD14I if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2968,12 +4113,16 @@ static void DSP_load_r14_r(void) { #ifdef DSP_DIS_LOAD14R if (doDSPDis) - WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[14], PIMM2, PRN); + WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[14], PIMM2, PRES); #endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[14] + PRM) & 0xFFFFFFFC, DSP); +#else PRES = DSPReadLong(dsp_reg[14] + PRM, DSP); +#endif #ifdef DSP_DIS_LOAD14R if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2981,12 +4130,16 @@ static void DSP_load_r15_i(void) { #ifdef DSP_DIS_LOAD15I if (doDSPDis) - WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[15]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN); + WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[15]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[15] &0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2), DSP); +#else PRES = DSPReadLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), DSP); +#endif #ifdef DSP_DIS_LOAD15I if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -2994,18 +4147,22 @@ static void DSP_load_r15_r(void) { #ifdef DSP_DIS_LOAD15R if (doDSPDis) - WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[15], PIMM2, PRN); + WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[15], PIMM2, PRN); #endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[15] + PRM) & 0xFFFFFFFC, DSP); +#else PRES = DSPReadLong(dsp_reg[15] + PRM, DSP); +#endif #ifdef DSP_DIS_LOAD15R if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } -static void DSP_mirror(void) +static void DSP_mirror(void) { - UINT32 r1 = PRN; + uint32 r1 = PRN; PRES = (mirror_table[r1 & 0xFFFF] << 16) | mirror_table[r1 >> 16]; SET_ZN(PRES); } @@ -3013,14 +4170,14 @@ static void DSP_mirror(void) static void DSP_mmult(void) { int count = dsp_matrix_control&0x0f; - uint32 addr = dsp_pointer_to_matrix; // in the gpu ram + uint32 addr = dsp_pointer_to_matrix; // in the dsp ram int64 accum = 0; uint32 res; if (!(dsp_matrix_control & 0x10)) { for (int i = 0; i < count; i++) - { + { int16 a; if (i&0x01) a=(int16)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff); @@ -3056,12 +4213,12 @@ static void DSP_move(void) { #ifdef DSP_DIS_MOVE if (doDSPDis) - WriteLog("%06X: MOVE R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: MOVE R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif PRES = PRM; #ifdef DSP_DIS_MOVE if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -3069,8 +4226,8 @@ static void DSP_movefa(void) { #ifdef DSP_DIS_MOVEFA if (doDSPDis) -// WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, ALTERNATE_RM, PIMM2, PRN); - WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, dsp_alternate_reg[PIMM1], PIMM2, PRN); +// WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, ALTERNATE_RM, PIMM2, PRN); + WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, dsp_alternate_reg[PIMM1], PIMM2, PRN); #endif // PRES = ALTERNATE_RM; PRES = dsp_alternate_reg[PIMM1]; @@ -3085,7 +4242,7 @@ static void DSP_movei(void) { #ifdef DSP_DIS_MOVEI if (doDSPDis) - WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, PRES, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PRES, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif // // This instruction is followed by 32-bit value in LSW / MSW format... // PRES = (uint32)DSPReadWord(dsp_pc, DSP) | ((uint32)DSPReadWord(dsp_pc + 2, DSP) << 16); @@ -3098,20 +4255,30 @@ static void DSP_movei(void) static void DSP_movepc(void) { -//Need to fix this to take into account pipelining effects... !!! FIX !!! - PRES = dsp_pc - 2; +#ifdef DSP_DIS_MOVEPC + if (doDSPDis) + WriteLog("%06X: MOVE PC, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif +//Need to fix this to take into account pipelining effects... !!! FIX !!! [DONE] +// PRES = dsp_pc - 2; +//Account for pipeline effects... + PRES = dsp_pc - 2 - (pipeline[plPtrRead].opcode == 38 ? 6 : (pipeline[plPtrRead].opcode == PIPELINE_STALL ? 0 : 2)); +#ifdef DSP_DIS_MOVEPC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif } static void DSP_moveq(void) { #ifdef DSP_DIS_MOVEQ if (doDSPDis) - WriteLog("%06X: MOVEQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: MOVEQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif PRES = PIMM1; #ifdef DSP_DIS_MOVEQ if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -3119,8 +4286,8 @@ static void DSP_moveta(void) { #ifdef DSP_DIS_MOVETA if (doDSPDis) -// WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, ALTERNATE_RN); - WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, dsp_alternate_reg[PIMM2]); +// WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, ALTERNATE_RN); + WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, dsp_alternate_reg[PIMM2]); #endif // ALTERNATE_RN = PRM; dsp_alternate_reg[PIMM2] = PRM; @@ -3134,7 +4301,7 @@ static void DSP_moveta(void) static void DSP_mtoi(void) { - PRES = (((INT32)PRM >> 8) & 0xFF800000) | (PRM & 0x007FFFFF); + PRES = (((int32)PRM >> 8) & 0xFF800000) | (PRM & 0x007FFFFF); SET_ZN(PRES); } @@ -3142,13 +4309,13 @@ static void DSP_mult(void) { #ifdef DSP_DIS_MULT if (doDSPDis) - WriteLog("%06X: MULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: MULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif PRES = (uint16)PRM * (uint16)PRN; SET_ZN(PRES); #ifdef DSP_DIS_MULT if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -3156,14 +4323,14 @@ static void DSP_neg(void) { #ifdef DSP_DIS_NEG if (doDSPDis) - WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - UINT32 res = -PRN; + uint32 res = -PRN; SET_ZNC_SUB(0, PRN, res); PRES = res; #ifdef DSP_DIS_NEG if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -3171,7 +4338,7 @@ static void DSP_nop(void) { #ifdef DSP_DIS_NOP if (doDSPDis) - WriteLog("%06X: NOP [NCZ:%u%u%u]\n", dsp_pc-2, dsp_flag_n, dsp_flag_c, dsp_flag_z); + WriteLog("%06X: NOP [NCZ:%u%u%u]\n", DSP_PPC, dsp_flag_n, dsp_flag_c, dsp_flag_z); #endif NO_WRITEBACK; } @@ -3202,13 +4369,13 @@ static void DSP_not(void) { #ifdef DSP_DIS_NOT if (doDSPDis) - WriteLog("%06X: NOT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: NOT R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif PRES = ~PRN; SET_ZN(PRES); #ifdef DSP_DIS_NOT if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -3216,13 +4383,13 @@ static void DSP_or(void) { #ifdef DSP_DIS_OR if (doDSPDis) - WriteLog("%06X: OR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: OR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif PRES = PRN | PRM; SET_ZN(PRES); #ifdef DSP_DIS_OR if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -3230,7 +4397,7 @@ static void DSP_resmac(void) { #ifdef DSP_DIS_RESMAC if (doDSPDis) - WriteLog("%06X: RESMAC R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_ACC=%02X%08X] -> ", dsp_pc-2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, (uint8)(dsp_acc >> 32), (uint32)(dsp_acc & 0xFFFFFFFF)); + WriteLog("%06X: RESMAC R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_ACC=%02X%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, (uint8)(dsp_acc >> 32), (uint32)(dsp_acc & 0xFFFFFFFF)); #endif PRES = (uint32)dsp_acc; #ifdef DSP_DIS_RESMAC @@ -3243,15 +4410,15 @@ static void DSP_ror(void) { #ifdef DSP_DIS_ROR if (doDSPDis) - WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif - UINT32 r1 = PRM & 0x1F; - UINT32 res = (PRN >> r1) | (PRN << (32 - r1)); + uint32 r1 = PRM & 0x1F; + uint32 res = (PRN >> r1) | (PRN << (32 - r1)); SET_ZN(res); dsp_flag_c = (PRN >> 31) & 1; PRES = res; #ifdef DSP_DIS_ROR if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -3259,32 +4426,32 @@ static void DSP_rorq(void) { #ifdef DSP_DIS_RORQ if (doDSPDis) - WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - UINT32 r1 = dsp_convert_zero[PIMM1 & 0x1F]; - UINT32 r2 = PRN; - UINT32 res = (r2 >> r1) | (r2 << (32 - r1)); + uint32 r1 = dsp_convert_zero[PIMM1 & 0x1F]; + uint32 r2 = PRN; + uint32 res = (r2 >> r1) | (r2 << (32 - r1)); PRES = res; SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01; #ifdef DSP_DIS_RORQ if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } -static void DSP_sat16s(void) +static void DSP_sat16s(void) { - INT32 r2 = PRN; - UINT32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2; + int32 r2 = PRN; + uint32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2; PRES = res; SET_ZN(res); } -static void DSP_sat32s(void) +static void DSP_sat32s(void) { - INT32 r2 = (UINT32)PRN; - INT32 temp = dsp_acc >> 32; - UINT32 res = (temp < -1) ? (INT32)0x80000000 : (temp > 0) ? (INT32)0x7FFFFFFF : r2; + int32 r2 = (uint32)PRN; + int32 temp = dsp_acc >> 32; + uint32 res = (temp < -1) ? (int32)0x80000000 : (temp > 0) ? (int32)0x7FFFFFFF : r2; PRES = res; SET_ZN(res); } @@ -3373,14 +4540,14 @@ static void DSP_sharq(void) { #ifdef DSP_DIS_SHARQ if (doDSPDis) - WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - UINT32 res = (INT32)PRN >> dsp_convert_zero[PIMM1]; + uint32 res = (int32)PRN >> dsp_convert_zero[PIMM1]; SET_ZN(res); dsp_flag_c = PRN & 0x01; PRES = res; #ifdef DSP_DIS_SHARQ if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -3388,15 +4555,15 @@ static void DSP_shlq(void) { #ifdef DSP_DIS_SHLQ if (doDSPDis) - WriteLog("%06X: SHLQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, 32 - PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: SHLQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, 32 - PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - INT32 r1 = 32 - PIMM1; - UINT32 res = PRN << r1; + int32 r1 = 32 - PIMM1; + uint32 res = PRN << r1; SET_ZN(res); dsp_flag_c = (PRN >> 31) & 1; PRES = res; #ifdef DSP_DIS_SHLQ if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -3404,15 +4571,15 @@ static void DSP_shrq(void) { #ifdef DSP_DIS_SHRQ if (doDSPDis) - WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - INT32 r1 = dsp_convert_zero[PIMM1]; - UINT32 res = PRN >> r1; + int32 r1 = dsp_convert_zero[PIMM1]; + uint32 res = PRN >> r1; SET_ZN(res); dsp_flag_c = PRN & 1; PRES = res; #ifdef DSP_DIS_SHRQ if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -3420,84 +4587,155 @@ static void DSP_store(void) { #ifdef DSP_DIS_STORE if (doDSPDis) - WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); + WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", DSP_PPC, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); #endif - DSPWriteLong(PRM, PRN, DSP); - NO_WRITEBACK; +// DSPWriteLong(PRM, PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = PRM & 0xFFFFFFFC; +#else + pipeline[plPtrExec].address = PRM; +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; } static void DSP_storeb(void) { #ifdef DSP_DIS_STOREB if (doDSPDis) - WriteLog("%06X: STOREB R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); + WriteLog("%06X: STOREB R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", DSP_PPC, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); #endif +// if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) +// DSPWriteLong(PRM, PRN & 0xFF, DSP); +// else +// JaguarWriteByte(PRM, PRN, DSP); +// +// NO_WRITEBACK; + pipeline[plPtrExec].address = PRM; + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) - DSPWriteLong(PRM, PRN & 0xFF, DSP); + { + pipeline[plPtrExec].value = PRN & 0xFF; + pipeline[plPtrExec].type = TYPE_DWORD; + } else - JaguarWriteByte(PRM, PRN, DSP); + { + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_BYTE; + } - NO_WRITEBACK; + WRITEBACK_ADDR; } static void DSP_storew(void) { #ifdef DSP_DIS_STOREW if (doDSPDis) - WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); + WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", DSP_PPC, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); +#endif +// if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) +// DSPWriteLong(PRM, PRN & 0xFFFF, DSP); +// else +// JaguarWriteWord(PRM, PRN, DSP); +// +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = PRM & 0xFFFFFFFE; +#else + pipeline[plPtrExec].address = PRM; #endif + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) - DSPWriteLong(PRM, PRN & 0xFFFF, DSP); + { + pipeline[plPtrExec].value = PRN & 0xFFFF; + pipeline[plPtrExec].type = TYPE_DWORD; + } else - JaguarWriteWord(PRM, PRN, DSP); - - NO_WRITEBACK; + { + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_WORD; + } + WRITEBACK_ADDR; } static void DSP_store_r14_i(void) { #ifdef DSP_DIS_STORE14I if (doDSPDis) - WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", dsp_pc-2, PIMM2, dsp_convert_zero[PIMM1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_convert_zero[PIMM1] << 2, dsp_reg[14]+(dsp_convert_zero[PIMM1] << 2)); + WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", DSP_PPC, PIMM2, dsp_convert_zero[PIMM1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_convert_zero[PIMM1] << 2, dsp_reg[14]+(dsp_convert_zero[PIMM1] << 2)); #endif - DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); - NO_WRITEBACK; +// DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2); +#else + pipeline[plPtrExec].address = dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2); +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; } static void DSP_store_r14_r(void) { - DSPWriteLong(dsp_reg[14] + PRM, PRN, DSP); - NO_WRITEBACK; +// DSPWriteLong(dsp_reg[14] + PRM, PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[14] + PRM) & 0xFFFFFFFC; +#else + pipeline[plPtrExec].address = dsp_reg[14] + PRM; +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; } static void DSP_store_r15_i(void) { #ifdef DSP_DIS_STORE15I if (doDSPDis) - WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", dsp_pc-2, PIMM2, dsp_convert_zero[PIMM1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_convert_zero[PIMM1] << 2, dsp_reg[15]+(dsp_convert_zero[PIMM1] << 2)); + WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", DSP_PPC, PIMM2, dsp_convert_zero[PIMM1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_convert_zero[PIMM1] << 2, dsp_reg[15]+(dsp_convert_zero[PIMM1] << 2)); #endif - DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); - NO_WRITEBACK; +// DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2); +#else + pipeline[plPtrExec].address = dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2); +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; } static void DSP_store_r15_r(void) { - DSPWriteLong(dsp_reg[15] + PRM, PRN, DSP); - NO_WRITEBACK; +// DSPWriteLong(dsp_reg[15] + PRM, PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[15] + PRM) & 0xFFFFFFFC; +#else + pipeline[plPtrExec].address = dsp_reg[15] + PRM; +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; } static void DSP_sub(void) { #ifdef DSP_DIS_SUB if (doDSPDis) - WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif - UINT32 res = PRN - PRM; + uint32 res = PRN - PRM; SET_ZNC_SUB(PRN, PRM, res); PRES = res; #ifdef DSP_DIS_SUB if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -3505,15 +4743,15 @@ static void DSP_subc(void) { #ifdef DSP_DIS_SUBC if (doDSPDis) - WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif - UINT32 res = PRN - PRM - dsp_flag_c; - UINT32 borrow = dsp_flag_c; + uint32 res = PRN - PRM - dsp_flag_c; + uint32 borrow = dsp_flag_c; SET_ZNC_SUB(PRN - borrow, PRM, res); PRES = res; #ifdef DSP_DIS_SUBC if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif } @@ -3521,23 +4759,23 @@ static void DSP_subq(void) { #ifdef DSP_DIS_SUBQ if (doDSPDis) - WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif - UINT32 r1 = dsp_convert_zero[PIMM1]; - UINT32 res = PRN - r1; + uint32 r1 = dsp_convert_zero[PIMM1]; + uint32 res = PRN - r1; SET_ZNC_SUB(PRN, r1, res); PRES = res; #ifdef DSP_DIS_SUBQ if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } -static void DSP_subqmod(void) +static void DSP_subqmod(void) { - UINT32 r1 = dsp_convert_zero[PIMM1]; - UINT32 r2 = PRN; - UINT32 res = r2 - r1; + uint32 r1 = dsp_convert_zero[PIMM1]; + uint32 r2 = PRN; + uint32 res = r2 - r1; res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); PRES = res; SET_ZNC_SUB(r2, r1, res); @@ -3547,12 +4785,12 @@ static void DSP_subqt(void) { #ifdef DSP_DIS_SUBQT if (doDSPDis) - WriteLog("%06X: SUBQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("%06X: SUBQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); #endif PRES = PRN - dsp_convert_zero[PIMM1]; #ifdef DSP_DIS_SUBQT if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); #endif } @@ -3560,12 +4798,12 @@ static void DSP_xor(void) { #ifdef DSP_DIS_XOR if (doDSPDis) - WriteLog("%06X: XOR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("%06X: XOR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); #endif PRES = PRN ^ PRM; SET_ZN(PRES); #ifdef DSP_DIS_XOR if (doDSPDis) - WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); #endif }