X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fdsp.cpp;h=7a0553f292b6c432a8daaa80b56c51daf88e7ef5;hb=6f25f63a18153bc2adc49c5f9a3862c2760716df;hp=1034f3c27ccafb45cb1b59e6f018c7f107c39356;hpb=5f349c8a960bfff50b44eb98e7f6e0224b543208;p=virtualjaguar diff --git a/src/dsp.cpp b/src/dsp.cpp index 1034f3c..7a0553f 100644 --- a/src/dsp.cpp +++ b/src/dsp.cpp @@ -3,10 +3,10 @@ // // Originally by David Raingeard // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) -// Extensive cleanups/rewrites by James L. Hammons +// Extensive cleanups/rewrites by James Hammons // (C) 2010 Underground Software // -// JLH = James L. Hammons +// JLH = James Hammons // // Who When What // --- ---------- ------------------------------------------------------------- @@ -18,17 +18,20 @@ #include // Used only for SDL_GetTicks... #include +#include +#include "dac.h" #include "gpu.h" #include "jagdasm.h" #include "jaguar.h" #include "jerry.h" #include "log.h" -#include "m68k.h" +#include "m68000/m68kinterface.h" //#include "memory.h" // Seems alignment in loads & stores was off... #define DSP_CORRECT_ALIGNMENT +//#define DSP_CORRECT_ALIGNMENT_STORE //#define DSP_DEBUG //#define DSP_DEBUG_IRQ @@ -411,9 +414,12 @@ static uint32 dsp_opcode_second_parameter; #define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) #define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b) -uint32 dsp_convert_zero[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; -uint8 * dsp_branch_condition_table = NULL; -static uint16 * mirror_table = NULL; +uint32 dsp_convert_zero[32] = { + 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +}; +uint8 dsp_branch_condition_table[32 * 8]; +static uint16 mirror_table[65536]; static uint8 dsp_ram_8[0x2000]; #define BRANCH_CONDITION(x) dsp_branch_condition_table[(x) + ((jaguar_flags & 7) << 5)] @@ -452,49 +458,39 @@ void DSPReleaseTimeslice(void) void dsp_build_branch_condition_table(void) { - // Allocate the mirror table - if (!mirror_table) - mirror_table = (uint16 *)malloc(65536 * sizeof(uint16)); - // Fill in the mirror table - if (mirror_table) - for(int i=0; i<65536; i++) - mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002) | - ((i >> 11) & 0x0004) | ((i >> 9) & 0x0008) | - ((i >> 7) & 0x0010) | ((i >> 5) & 0x0020) | - ((i >> 3) & 0x0040) | ((i >> 1) & 0x0080) | - ((i << 1) & 0x0100) | ((i << 3) & 0x0200) | - ((i << 5) & 0x0400) | ((i << 7) & 0x0800) | - ((i << 9) & 0x1000) | ((i << 11) & 0x2000) | - ((i << 13) & 0x4000) | ((i << 15) & 0x8000); - - if (!dsp_branch_condition_table) + for(int i=0; i<65536; i++) { - dsp_branch_condition_table = (uint8 *)malloc(32 * 8 * sizeof(uint8)); + mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002) + | ((i >> 11) & 0x0004) | ((i >> 9) & 0x0008) + | ((i >> 7) & 0x0010) | ((i >> 5) & 0x0020) + | ((i >> 3) & 0x0040) | ((i >> 1) & 0x0080) + | ((i << 1) & 0x0100) | ((i << 3) & 0x0200) + | ((i << 5) & 0x0400) | ((i << 7) & 0x0800) + | ((i << 9) & 0x1000) | ((i << 11) & 0x2000) + | ((i << 13) & 0x4000) | ((i << 15) & 0x8000); + } - // Fill in the condition table - if (dsp_branch_condition_table) + // Fill in the condition table + for(int i=0; i<8; i++) + { + for(int j=0; j<32; j++) { - for(int i=0; i<8; i++) - { - for(int j=0; j<32; j++) - { - int result = 1; - if (j & 1) - if (i & ZERO_FLAG) - result = 0; - if (j & 2) - if (!(i & ZERO_FLAG)) - result = 0; - if (j & 4) - if (i & (CARRY_FLAG << (j >> 4))) - result = 0; - if (j & 8) - if (!(i & (CARRY_FLAG << (j >> 4)))) - result = 0; - dsp_branch_condition_table[i * 32 + j] = result; - } - } + int result = 1; + + if ((j & 1) && (i & ZERO_FLAG)) + result = 0; + + if ((j & 2) && (!(i & ZERO_FLAG))) + result = 0; + + if ((j & 4) && (i & (CARRY_FLAG << (j >> 4)))) + result = 0; + + if ((j & 8) && (!(i & (CARRY_FLAG << (j >> 4))))) + result = 0; + + dsp_branch_condition_table[i * 32 + j] = result; } } } @@ -628,12 +624,9 @@ uint32 DSPReadLong(uint32 offset, uint32 who/*=UNKNOWN*/) offset &= 0x3F; switch (offset) { - case 0x00: /*dsp_flag_c?(dsp_flag_c=1):(dsp_flag_c=0); - dsp_flag_z?(dsp_flag_z=1):(dsp_flag_z=0); - dsp_flag_n?(dsp_flag_n=1):(dsp_flag_n=0);*/ - - dsp_flags = (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; - return dsp_flags & 0xFFFFC1FF; + case 0x00: + dsp_flags = (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; + return dsp_flags & 0xFFFFC1FF; case 0x04: return dsp_matrix_control; case 0x08: return dsp_pointer_to_matrix; case 0x0C: return dsp_data_organization; @@ -664,7 +657,7 @@ void DSPWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/) /* if (dsp_in_exec == 0) { m68k_end_timeslice(); - gpu_releaseTimeslice(); + dsp_releaseTimeslice(); }*/ return; } @@ -714,7 +707,7 @@ void DSPWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/) { // WriteLog("dsp: writing %.4x at 0x%.8x\n",data,offset+DSP_WORK_RAM_BASE); m68k_end_timeslice(); - gpu_releaseTimeslice(); + dsp_releaseTimeslice(); }*/ //CC only! #ifdef DSP_DEBUG_CC @@ -729,19 +722,22 @@ SET16(ram2, offset, data); if ((offset & 0x1C) == 0x1C) { if (offset & 0x03) - dsp_div_control = (dsp_div_control&0xffff0000)|(data&0xffff); + dsp_div_control = (dsp_div_control & 0xFFFF0000) | (data & 0xFFFF); else - dsp_div_control = (dsp_div_control&0xffff)|((data&0xffff)<<16); + dsp_div_control = (dsp_div_control & 0xFFFF) | ((data & 0xFFFF) << 16); } else { - uint32 old_data = DSPReadLong(offset & 0xffffffc, who); + uint32 old_data = DSPReadLong(offset & 0xFFFFFFC, who); + if (offset & 0x03) - old_data = (old_data&0xffff0000)|(data&0xffff); + old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF); else - old_data = (old_data&0xffff)|((data&0xffff)<<16); - DSPWriteLong(offset & 0xffffffc, old_data, who); + old_data = (old_data & 0xFFFF) | ((data & 0xFFFF) << 16); + + DSPWriteLong(offset & 0xFFFFFFC, old_data, who); } + return; } @@ -784,17 +780,61 @@ SET32(ram2, offset, data); case 0x00: { #ifdef DSP_DEBUG - WriteLog("DSP: Writing %08X to DSP_FLAGS by %s (REGPAGE is %s)...\n", data, whoName[who], (dsp_flags & REGPAGE ? "set" : "not set")); + WriteLog("DSP: Writing %08X to DSP_FLAGS by %s (REGPAGE is %sset)...\n", data, whoName[who], (dsp_flags & REGPAGE ? "" : "not ")); #endif // bool IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); - dsp_flags = data; + // NOTE: According to the JTRM, writing a 1 to IMASK has no effect; only the + // IRQ logic can set it. So we mask it out here to prevent problems... + dsp_flags = data & (~IMASK); dsp_flag_z = dsp_flags & 0x01; dsp_flag_c = (dsp_flags >> 1) & 0x01; dsp_flag_n = (dsp_flags >> 2) & 0x01; DSPUpdateRegisterBanks(); dsp_control &= ~((dsp_flags & CINT04FLAGS) >> 3); dsp_control &= ~((dsp_flags & CINT5FLAG) >> 1); + +// NB: This is just a wild hairy-assed guess as to what the playback frequency is. +// It can be timed to anything really, anything that writes to L/RTXD at a regular +// interval. Most things seem to use either the I2S interrupt or the TIMER 0 +// interrupt, so that's what we check for here. Just know that this approach +// can be easily fooled! +// Note also that if both interrupts are enabled, the I2S freq will win. :-P + +// Further Note: +// The impetus for this "fix" was Cybermorph, which sets the SCLK to 7 which is an +// audio frequency > 48 KHz. However, it stuffs the L/RTXD registers using TIMER0. +// So, while this works, it's a by-product of the lame way in which audio is currently +// handled. Hopefully, once we run the DSP in the host audio IRQ, this problem will +// go away of its own accord. :-P +// Or does it? It seems the I2S interrupt isn't on with Cybermorph, so something +// weird is going on here... +// Maybe it works like this: It acknowledges the 1st interrupt, but never clears it. +// So subsequent interrupts come into the chip, but they're never serviced but the +// I2S subsystem keeps going. +// After some testing on real hardware, it seems that if you enable TIMER0 and EXTERNAL +// IRQs on J_INT ($F10020), you don't have to run an I2S interrupt on the DSP. Also, +// It seems that it's only stable for values of SCLK <= 9. + +// All of the preceeding is moot now; we run the DSP in the host audio IRQ. This means +// that we don't actually need this stuff anymore. :-D +#if 0 + if (data & INT_ENA1) // I2S interrupt + { + int freq = GetCalculatedFrequency(); +//This happens too often to be useful... +// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq); + DACSetNewFrequency(freq); + } + else if (data & INT_ENA2) // TIMER 0 interrupt + { + int freq = JERRYGetPIT1Frequency(); +//This happens too often to be useful... +// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq); + DACSetNewFrequency(freq); + } +#endif + /* if (IMASKCleared) // If IMASK was cleared, #ifdef DSP_DEBUG_IRQ { @@ -855,7 +895,7 @@ if (who != DSP) case 0x14: { //#ifdef DSP_DEBUG -WriteLog("Write to DSP CTRL by %s: %08X\n", whoName[who], data); +WriteLog("Write to DSP CTRL by %s: %08X (DSP PC=$%08X)\n", whoName[who], data, dsp_pc); //#endif bool wasRunning = DSP_RUNNING; // uint32 dsp_was_running = DSP_RUNNING; @@ -883,7 +923,7 @@ WriteLog("Write to DSP CTRL by %s: %08X\n", whoName[who], data); WriteLog("DSP: CPU -> DSP interrupt\n"); #endif m68k_end_timeslice(); - GPUReleaseTimeslice(); + DSPReleaseTimeslice(); DSPSetIRQLine(DSPIRQ_CPU, ASSERT_LINE); data &= ~DSPINT0; } @@ -923,14 +963,14 @@ else WriteLog(" --> Stopped by %s! (DSP PC: %08X)", whoName[who], dsp_pc); WriteLog("\n"); #endif // DSP_DEBUG -//This isn't exactly right either--we don't know if it was the M68K or the GPU writing here... +//This isn't exactly right either--we don't know if it was the M68K or the DSP writing here... // !!! FIX !!! [DONE] if (DSP_RUNNING) { if (who == M68K) m68k_end_timeslice(); - else if (who == GPU) - GPUReleaseTimeslice(); + else if (who == DSP) + DSPReleaseTimeslice(); if (!wasRunning) FlushDSPPipeline(); @@ -1246,6 +1286,11 @@ DSPHandleIRQsNP(); // GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE); } +bool DSPIsRunning(void) +{ + return (DSP_RUNNING ? true : false); +} + void DSPInit(void) { // memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM"); @@ -1254,6 +1299,7 @@ void DSPInit(void) dsp_build_branch_condition_table(); DSPReset(); + srand(time(NULL)); // For randomizing local RAM } void DSPReset(void) @@ -1280,7 +1326,12 @@ void DSPReset(void) IMASKCleared = false; FlushDSPPipeline(); dsp_reset_stats(); - memset(dsp_ram_8, 0xFF, 0x2000); +// memset(dsp_ram_8, 0xFF, 0x2000); + // Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents + for(uint32 i=0; i<8192; i+=4) + { + *((uint32 *)(&dsp_ram_8[i])) = rand(); + } } void DSPDumpDisassembly(void) @@ -1289,6 +1340,7 @@ void DSPDumpDisassembly(void) WriteLog("\n---[DSP code at 00F1B000]---------------------------\n"); uint32 j = 0xF1B000; + while (j <= 0xF1CFFF) { uint32 oldj = j; @@ -1302,6 +1354,7 @@ void DSPDumpRegisters(void) //Shoud add modulus, etc to dump here... WriteLog("\n---[DSP flags: NCZ %d%d%d, DSP PC: %08X]------------\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_pc); WriteLog("\nRegisters bank 0\n"); + for(int j=0; j<8; j++) { WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", @@ -1310,7 +1363,9 @@ void DSPDumpRegisters(void) (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2], (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]); } + WriteLog("Registers bank 1\n"); + for(int j=0; j<8; j++) { WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", @@ -1324,7 +1379,7 @@ void DSPDumpRegisters(void) void DSPDone(void) { int i, j; - WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp %s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "was" : "wasn't")); + WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp was%s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "" : "n't")); WriteLog("DSP: %sin interrupt handler\n", (dsp_flags & IMASK ? "" : "not ")); // get the active interrupt bits @@ -1332,8 +1387,12 @@ void DSPDone(void) // get the interrupt mask int mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F); - WriteLog("DSP: pending=%08X enabled=%08X\n", bits, mask); + WriteLog("DSP: pending=$%X enabled=$%X (%s%s%s%s%s%s)\n", bits, mask, + (mask & 0x01 ? "CPU " : ""), (mask & 0x02 ? "I2S " : ""), + (mask & 0x04 ? "Timer0 " : ""), (mask & 0x08 ? "Timer1 " : ""), + (mask & 0x10 ? "Ext0 " : ""), (mask & 0x20 ? "Ext1" : "")); WriteLog("\nRegisters bank 0\n"); + for(int j=0; j<8; j++) { WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n", @@ -1342,7 +1401,9 @@ void DSPDone(void) (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2], (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]); } + WriteLog("\nRegisters bank 1\n"); + for (j=0; j<8; j++) { WriteLog("\tR%02i=%08X R%02i=%08X R%02i=%08X R%02i=%08X\n", @@ -1350,12 +1411,14 @@ void DSPDone(void) (j << 2) + 1, dsp_reg_bank_1[(j << 2) + 1], (j << 2) + 2, dsp_reg_bank_1[(j << 2) + 2], (j << 2) + 3, dsp_reg_bank_1[(j << 2) + 3]); - } + WriteLog("\n"); + static char buffer[512]; j = DSP_WORK_RAM_BASE; - while (j <= 0xF1BFFF) + + while (j <= 0xF1CFFF) { uint32 oldj = j; j += dasmjag(JAGUAR_DSP, buffer, j); @@ -1363,6 +1426,7 @@ void DSPDone(void) }//*/ WriteLog("DSP opcodes use:\n"); + for (i=0;i<64;i++) { if (dsp_opcode_use[i]) @@ -1372,11 +1436,11 @@ void DSPDone(void) // memory_free(dsp_ram_8); // memory_free(dsp_reg_bank_0); // memory_free(dsp_reg_bank_1); - if (dsp_branch_condition_table) - free(dsp_branch_condition_table); +// if (dsp_branch_condition_table) +// free(dsp_branch_condition_table); - if (mirror_table) - free(mirror_table); +// if (mirror_table) +// free(mirror_table); } @@ -1955,7 +2019,7 @@ static void dsp_opcode_store_r14_indexed(void) if (doDSPDis) WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[14]+(dsp_convert_zero[IMM_1] << 2)); #endif -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE DSPWriteLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP); #else DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[IMM_1] << 2), RN, DSP); @@ -1968,7 +2032,7 @@ static void dsp_opcode_store_r15_indexed(void) if (doDSPDis) WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[15]+(dsp_convert_zero[IMM_1] << 2)); #endif -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE DSPWriteLong((dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP); #else DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[IMM_1] << 2), RN, DSP); @@ -2045,7 +2109,7 @@ static void dsp_opcode_storew(void) if (doDSPDis) WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM); #endif -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) DSPWriteLong(RM & 0xFFFFFFFE, RN & 0xFFFF, DSP); else @@ -2064,7 +2128,7 @@ static void dsp_opcode_store(void) if (doDSPDis) WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM); #endif -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE DSPWriteLong(RM & 0xFFFFFFFC, RN, DSP); #else DSPWriteLong(RM, RN, DSP); @@ -2384,7 +2448,7 @@ static void dsp_opcode_normi(void) static void dsp_opcode_mmult(void) { int count = dsp_matrix_control&0x0f; - uint32 addr = dsp_pointer_to_matrix; // in the gpu ram + uint32 addr = dsp_pointer_to_matrix; // in the dsp ram int64 accum = 0; uint32 res; @@ -4106,7 +4170,7 @@ static void DSP_mirror(void) static void DSP_mmult(void) { int count = dsp_matrix_control&0x0f; - uint32 addr = dsp_pointer_to_matrix; // in the gpu ram + uint32 addr = dsp_pointer_to_matrix; // in the dsp ram int64 accum = 0; uint32 res; @@ -4527,7 +4591,7 @@ static void DSP_store(void) #endif // DSPWriteLong(PRM, PRN, DSP); // NO_WRITEBACK; -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE pipeline[plPtrExec].address = PRM & 0xFFFFFFFC; #else pipeline[plPtrExec].address = PRM; @@ -4577,7 +4641,7 @@ static void DSP_storew(void) // JaguarWriteWord(PRM, PRN, DSP); // // NO_WRITEBACK; -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE pipeline[plPtrExec].address = PRM & 0xFFFFFFFE; #else pipeline[plPtrExec].address = PRM; @@ -4604,7 +4668,7 @@ static void DSP_store_r14_i(void) #endif // DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); // NO_WRITEBACK; -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE pipeline[plPtrExec].address = (dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2); #else pipeline[plPtrExec].address = dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2); @@ -4618,7 +4682,7 @@ static void DSP_store_r14_r(void) { // DSPWriteLong(dsp_reg[14] + PRM, PRN, DSP); // NO_WRITEBACK; -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE pipeline[plPtrExec].address = (dsp_reg[14] + PRM) & 0xFFFFFFFC; #else pipeline[plPtrExec].address = dsp_reg[14] + PRM; @@ -4636,7 +4700,7 @@ static void DSP_store_r15_i(void) #endif // DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); // NO_WRITEBACK; -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE pipeline[plPtrExec].address = (dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2); #else pipeline[plPtrExec].address = dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2); @@ -4650,7 +4714,7 @@ static void DSP_store_r15_r(void) { // DSPWriteLong(dsp_reg[15] + PRM, PRN, DSP); // NO_WRITEBACK; -#ifdef DSP_CORRECT_ALIGNMENT +#ifdef DSP_CORRECT_ALIGNMENT_STORE pipeline[plPtrExec].address = (dsp_reg[15] + PRM) & 0xFFFFFFFC; #else pipeline[plPtrExec].address = dsp_reg[15] + PRM;