// --- ---------- ------------------------------------------------------------
// JLH 06/15/2006 Added changelog ;-)
// JLH 06/15/2006 Scrubbed all BYTE, WORD & DWORD references from the code
+// JLH 11/11/2006 Removed all SignedX() references
//
// Mebbe someday I'll get around to fixing the core to be more like V65C02...
+// We have a start... ;-)
//
+//#define __DEBUG__
+
#include "v6809.h"
#ifdef __DEBUG__
#include "log.h" // Temporary...
#endif
+// Various macros
+
+#define CLR_Z (regs.cc &= ~FLAG_Z)
+#define CLR_ZN (regs.cc &= ~(FLAG_Z | FLAG_N))
+#define CLR_ZNC (regs.cc &= ~(FLAG_Z | FLAG_N | FLAG_C))
+#define CLR_V (regs.cc &= ~FLAG_V)
+#define CLR_N (regs.cc &= ~FLAG_N)
+#define SET_Z(r) (regs.cc = ((r) == 0 ? regs.cc | FLAG_Z : regs.cc & ~FLAG_Z))
+#define SET_N(r) (regs.cc = ((r) & 0x80 ? regs.cc | FLAG_N : regs.cc & ~FLAG_N))
+
+//Not sure that this code is computing the carry correctly... Investigate! [Seems to be]
+#define SET_C_ADD(a,b) (regs.cc = ((uint8)(b) > (uint8)(~(a)) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+//#define SET_C_SUB(a,b) (regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_C_CMP(a,b) (regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_ZN(r) SET_N(r); SET_Z(r)
+#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
+//#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b)
+#define SET_ZNC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b)
+
+//Small problem with the EA_ macros: ABS macros don't increment the PC!!! !!! FIX !!!
+//Hmm, why not do like we did for READ_ABS*???
+#define EA_IMM regs.pc++
+#define EA_ZP regs.RdMem(regs.pc++)
+#define EA_ZP_X (regs.RdMem(regs.pc++) + regs.x) & 0xFF
+#define EA_ZP_Y (regs.RdMem(regs.pc++) + regs.y) & 0xFF
+#define EA_ABS RdMemW(regs.pc)
+#define EA_ABS_X RdMemW(regs.pc) + regs.x
+#define EA_ABS_Y RdMemW(regs.pc) + regs.y
+#define EA_IND_ZP_X RdMemW((regs.RdMem(regs.pc++) + regs.x) & 0xFF)
+#define EA_IND_ZP_Y RdMemW(regs.RdMem(regs.pc++)) + regs.y
+#define EA_IND_ZP RdMemW(regs.RdMem(regs.pc++))
+
+#define READ_IMM regs.RdMem(EA_IMM)
+#define READ_ZP regs.RdMem(EA_ZP)
+#define READ_ZP_X regs.RdMem(EA_ZP_X)
+#define READ_ZP_Y regs.RdMem(EA_ZP_Y)
+#define READ_ABS regs.RdMem(EA_ABS); regs.pc += 2
+#define READ_ABS_X regs.RdMem(EA_ABS_X); regs.pc += 2
+#define READ_ABS_Y regs.RdMem(EA_ABS_Y); regs.pc += 2
+#define READ_IND_ZP_X regs.RdMem(EA_IND_ZP_X)
+#define READ_IND_ZP_Y regs.RdMem(EA_IND_ZP_Y)
+#define READ_IND_ZP regs.RdMem(EA_IND_ZP)
+
+#define READ_IMM_WB(v) uint16 addr = EA_IMM; v = regs.RdMem(addr)
+#define READ_ZP_WB(v) uint16 addr = EA_ZP; v = regs.RdMem(addr)
+#define READ_ZP_X_WB(v) uint16 addr = EA_ZP_X; v = regs.RdMem(addr)
+#define READ_ABS_WB(v) uint16 addr = EA_ABS; v = regs.RdMem(addr); regs.pc += 2
+#define READ_ABS_X_WB(v) uint16 addr = EA_ABS_X; v = regs.RdMem(addr); regs.pc += 2
+#define READ_ABS_Y_WB(v) uint16 addr = EA_ABS_Y; v = regs.RdMem(addr); regs.pc += 2
+#define READ_IND_ZP_X_WB(v) uint16 addr = EA_IND_ZP_X; v = regs.RdMem(addr)
+#define READ_IND_ZP_Y_WB(v) uint16 addr = EA_IND_ZP_Y; v = regs.RdMem(addr)
+#define READ_IND_ZP_WB(v) uint16 addr = EA_IND_ZP; v = regs.RdMem(addr)
+
+#define WRITE_BACK(d) regs.WrMem(addr, (d))
+
// Private global variables
static V6809REGS regs;
+//Let's see if we can nuke this shit.
static uint16 addr; // Temporary variables common to all funcs...
static uint8 tmp;
// Private function prototypes
-static int SignedB(uint8); // Return signed byte from unsigned
-static int SignedW(uint16); // Return signed word from unsigned
static uint16 FetchW(void);
static uint16 RdMemW(uint16 addr);
static void WrMemW(uint16 addr, uint16 w);
regs.pc += 2;
return w;
}
-//
-// Fetch word function
-//
-/*uint16 FetchW(void)
-{
- return (uint16)(regs.RdMem(regs.pc++) << 8) | regs.RdMem(regs.pc++);
-}*/
//
// Read word from memory function
regs.WrMem(addr + 1, w & 0xFF);
}
-//
-// return signed byte from unsigned
-//
-int SignedB(uint8 b)
-{
- return (b & 0x80 ? b - 256 : b);
-}
-
-//
-// return signed word from unsigned
-//
-int SignedW(uint16 w)
-{
- return (w & 0x8000 ? w - 65536 : w);
-}
-
//
// Function to read TFR/EXG post byte
//
addr = RdMemW(woff);
break;
case 5:
- woff = DecodeReg(reg) + SignedB(regs.b);
+ woff = DecodeReg(reg) + (int16)(int8)regs.b;
addr = RdMemW(woff);
break;
case 6:
- woff = DecodeReg(reg) + SignedB(regs.a);
+ woff = DecodeReg(reg) + (int16)(int8)regs.a;
addr = RdMemW(woff);
break;
case 8:
- woff = DecodeReg(reg) + SignedB(regs.RdMem(regs.pc++));
+ woff = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++);
addr = RdMemW(woff);
break;
case 9:
- woff = DecodeReg(reg) + SignedW(FetchW());
+ woff = DecodeReg(reg) + FetchW();
addr = RdMemW(woff);
break;
case 11:
- woff = DecodeReg(reg) + SignedW((regs.a << 8) | regs.b);
+ woff = DecodeReg(reg) + ((regs.a << 8) | regs.b);
addr = RdMemW(woff);
break;
case 12:
- woff = regs.pc + SignedB(regs.RdMem(regs.pc++));
+ woff = regs.pc + (int16)(int8)regs.RdMem(regs.pc++);
addr = RdMemW(woff);
break;
case 13:
- woff = regs.pc + SignedW(FetchW());
+ woff = regs.pc + FetchW();
addr = RdMemW(woff);
break;
case 15:
}
addr = DecodeReg(reg); break; }
case 4: { addr = DecodeReg(reg); break; }
- case 5: { addr = DecodeReg(reg) + SignedB(regs.b); break; }
- case 6: { addr = DecodeReg(reg) + SignedB(regs.a); break; }
- case 8: { addr = DecodeReg(reg) + SignedB(regs.RdMem(regs.pc++)); break; }
- case 9: { addr = DecodeReg(reg) + SignedW(FetchW()); break; }
- case 11: { addr = DecodeReg(reg) + SignedW((regs.a << 8) | regs.b); break; }
- case 12: { addr = regs.pc + SignedB(regs.RdMem(regs.pc++)); break; }
- case 13: { addr = regs.pc + SignedW(FetchW()); break; }
+ case 5: { addr = DecodeReg(reg) + (int16)(int8)regs.b; break; }
+ case 6: { addr = DecodeReg(reg) + (int16)(int8)regs.a; break; }
+ case 8: { addr = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++); break; }
+ case 9: { addr = DecodeReg(reg) + FetchW(); break; }
+ case 11: { addr = DecodeReg(reg) + ((regs.a << 8) | regs.b); break; }
+ case 12: { addr = regs.pc + (int16)(int8)regs.RdMem(regs.pc++); break; }
+ case 13: { addr = regs.pc + FetchW(); break; }
}
}
}
{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
regs.cc &= 0xFD; // CLV
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 6;
}
static void Op0E(void) // JMP DP
exec_op1[regs.RdMem(regs.pc++)]();
}
-static void Op11(void) // Page 2 opcode
+static void Op11(void) // Page 2 opcode
{
exec_op2[regs.RdMem(regs.pc++)]();
}
-static void Op12(void) // NOP
+static void Op12(void) // NOP
{
regs.clock += 2;
}
-static void Op13(void) // SYNC
-{
- regs.clock += 2;
+static void Op13(void) // SYNC
+{
+ // Fix this so it does the right thing (software interrupt!)
+ regs.clock += 2;
}
-static void Op16(void) // LBRA
+
+static void Op16(void) // LBRA
{
- regs.pc += SignedW(FetchW());
- regs.clock += 5;
+// regs.pc += SignedW(FetchW());
+ regs.pc += FetchW(); // No need to make signed, both are 16 bit quantities
+
+ regs.clock += 5;
}
-static void Op17(void) // LBSR
+
+static void Op17(void) // LBSR
{
- addr = FetchW();
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc += SignedW(addr);
- regs.clock += 9;
+ uint16 word = FetchW();
+ regs.WrMem(--regs.s, regs.pc & 0xFF);
+ regs.WrMem(--regs.s, regs.pc >> 8);
+// regs.pc += SignedW(addr);
+ regs.pc += word; // No need to make signed, both are 16 bit
+
+ regs.clock += 9;
}
+
static void Op19(void) // DAA
{
if ((regs.cc&0x20) || ((regs.a&0x0F) > 0x09)) // H set or lo nyb too big?
regs.a += 0x60; regs.cc |= 0x01; // Then adjust & set carry
}
regs.cc &= 0xF1; // CL NZV
- if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
regs.clock += 2;
}
regs.clock += 3;
}
-static void Op1D(void) // SEX
+static void Op1D(void) // SEX
{
(regs.b & 0x80 ? regs.a = 0xFF : regs.a = 0x00);
regs.clock += 2;
}
-static void Op1E(void) // EXG
+static void Op1E(void) // EXG
{
tmp = regs.RdMem(regs.pc++);
addr = ReadEXG(tmp >> 4);
WriteEXG(tmp&0xF, ReadEXG(tmp>>4));
regs.clock += 7;
}
-static void Op20(void) // BRA
+
+static void Op20(void) // BRA
{
- regs.pc += SignedB(regs.RdMem(regs.pc++)); // Branch always
- regs.clock += 3;
+// regs.pc += SignedB(regs.RdMem(regs.pc++)); // Branch always
+ regs.pc += (int16)(int8)regs.RdMem(regs.pc) + 1; // Branch always
+
+ regs.clock += 3;
}
-static void Op21(void) // BRN
+
+static void Op21(void) // BRN
{
- regs.RdMem(regs.pc++);
- regs.clock += 3;
+ regs.RdMem(regs.pc++);
+
+ regs.clock += 3;
}
-static void Op22(void) // BHI
+
+static void Op22(void) // BHI
{
- tmp = regs.RdMem(regs.pc++);
- if (!(regs.cc&0x05)) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (!(regs.cc & 0x05))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op23(void) // BLS
+
+static void Op23(void) // BLS
{
- tmp = regs.RdMem(regs.pc++);
- if (regs.cc&0x05) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (regs.cc & 0x05)
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op24(void) // BCC (BHS)
+
+static void Op24(void) // BCC (BHS)
{
- tmp = regs.RdMem(regs.pc++);
- if (!(regs.cc&0x01)) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (!(regs.cc & 0x01))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op25(void) // BCS (BLO)
+
+static void Op25(void) // BCS (BLO)
{
- tmp = regs.RdMem(regs.pc++);
- if (regs.cc&0x01) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (regs.cc & 0x01)
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op26(void) // BNE
+
+static void Op26(void) // BNE
{
- tmp = regs.RdMem(regs.pc++);
- if (!(regs.cc&0x04)) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (!(regs.cc & 0x04))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op27(void) // BEQ
+
+static void Op27(void) // BEQ
{
- tmp = regs.RdMem(regs.pc++);
- if (regs.cc&0x04) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (regs.cc & 0x04)
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op28(void) // BVC
+
+static void Op28(void) // BVC
{
- tmp = regs.RdMem(regs.pc++);
- if (!(regs.cc&0x02)) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (!(regs.cc & 0x02))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op29(void) // BVS
+
+static void Op29(void) // BVS
{
- tmp = regs.RdMem(regs.pc++);
- if (regs.cc&0x02) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (regs.cc & 0x02)
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op2A(void) // BPL
+
+static void Op2A(void) // BPL
{
- tmp = regs.RdMem(regs.pc++);
- if (!(regs.cc&0x08)) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (!(regs.cc & 0x08))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op2B(void) // BMI
+
+static void Op2B(void) // BMI
{
- tmp = regs.RdMem(regs.pc++);
- if (regs.cc&0x08) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (regs.cc & 0x08)
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op2C(void) // BGE
+
+static void Op2C(void) // BGE
{
- tmp = regs.RdMem(regs.pc++);
- if (!(((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op2D(void) // BLT
+
+static void Op2D(void) // BLT
{
- tmp = regs.RdMem(regs.pc++);
- if (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op2E(void) // BGT
+
+static void Op2E(void) // BGT
{
- tmp = regs.RdMem(regs.pc++);
- if (!((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)))) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))))
+ regs.pc += word;
+
+ regs.clock += 3;
}
-static void Op2F(void) // BLE
+
+static void Op2F(void) // BLE
{
- tmp = regs.RdMem(regs.pc++);
- if ((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedB(tmp);
- regs.clock += 3;
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+ if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+ regs.pc += word;
+
+ regs.clock += 3;
}
+
static void Op30(void) // LEAX
{
regs.x = DecodeIDX(regs.RdMem(regs.pc++));
{
}
static void Op40(void) // NEGA
-{
+{
regs.a = 256 - regs.a;
(regs.a > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
(regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 2;
}
-static void Op49(void) // ROLA
+static void Op49(void) // ROLA
{
tmp = regs.a; regs.a = (tmp<<1) + (regs.cc&0x01);
(tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
regs.clock += 2;
}
static void Op50(void) // NEGB
- {
+ {
regs.b = 256 - regs.b;
// ((regs.b^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
(regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void Op5C(void) // INCB
{
regs.b++;
- (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 2;
regs.clock += 2;
}
static void Op60(void) // NEG IDX
- {
+ {
addr = DecodeIDX(regs.RdMem(regs.pc++));
tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
regs.WrMem(addr, res);
regs.clock += 6;
}
static void Op6C(void) // INC IDX
- {
+ {
addr = DecodeIDX(regs.RdMem(regs.pc++));
tmp = regs.RdMem(addr) + 1;
regs.WrMem(addr, tmp);
static void Op6D(void) // TST IDX
{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 6;
}
static void Op6E(void) // JMP IDX
regs.clock += 6;
}
static void Op70(void) // NEG ABS
- {
+ {
addr = FetchW();
tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
regs.WrMem(addr, res);
regs.clock += 7;
}
static void Op7C(void) // INC ABS
- {
+ {
uint8 tmp; uint16 addr;
addr = FetchW();
tmp = regs.RdMem(addr) + 1;
{
uint8 tmp = regs.RdMem(FetchW());
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 7;
}
regs.clock += 7;
}
static void Op80(void) // SUBA #
-{
- uint8 tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
+{
+ uint8 tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
regs.a -= tmp;
(as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
}
static void Op82(void) // SBCA #
{
- tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
+ tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
regs.clock += 2;
}
static void Op8B(void) // ADDA #
-{
+{
tmp = regs.RdMem(regs.pc++); addr = regs.a + tmp;
(addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 4;
}
-static void Op8D(void) // Bregs.s
- {
- tmp = regs.RdMem(regs.pc++);
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc += SignedB(tmp);
- regs.clock += 7;
- }
+
+static void Op8D(void) // Bregs.s
+{
+ uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+ regs.WrMem(--regs.s, regs.pc & 0xFF);
+ regs.WrMem(--regs.s, regs.pc >> 8);
+ regs.pc += word;
+
+ regs.clock += 7;
+}
+
static void Op8E(void) // LDX #
{
regs.x = FetchW();
regs.clock += 3;
}
static void Op90(void) // SUBA DP
- {
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
+ {
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
regs.a -= tmp;
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
}
static void Op92(void) // SBCA DP
{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
regs.clock += 4;
}
static void Op9B(void) // ADDA DP
-{
+{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
addr = (uint16)regs.a + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpA0(void) // SUBA IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
+ {
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
regs.a -= tmp;
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
}
static void OpA2(void) // SBCA IDX
{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 4;
}
static void OpAB(void) // ADDA IDX
-{
+{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
addr = (uint16)regs.a + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpB0(void) // SUBA ABS
- {
- tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
+ {
+ tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
regs.a -= tmp;
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
}
static void OpB2(void) // SBCA ABS
{
- tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
+ tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpBB(void) // ADDA ABS
-{
+{
tmp = regs.RdMem(FetchW());
addr = (uint16)regs.a + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
{
addr = FetchW();
regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // Go to absolute address (Not indir)
+ regs.pc = addr; // Go to absolute address (Not indir)
regs.clock += 8;
}
}
static void OpC0(void) // SUBB #
- {
- tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
+ {
+ tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
}
static void OpC2(void) // SBCB #
{
- tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
+ tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 2;
}
static void OpCB(void) // ADDB #
-{
+{
tmp = regs.RdMem(regs.pc++); addr = regs.b + tmp;
(addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 3;
}
static void OpD0(void) // SUBB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
}
static void OpD2(void) // SBCB DP
{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 4;
}
static void OpDB(void) // ADDB DP
-{
+{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
addr = (uint16)regs.b + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpE0(void) // SUBB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
}
static void OpE2(void) // SBCB IDX
{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 4;
}
static void OpEB(void) // ADDB IDX
-{
+{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
addr = (uint16)regs.b + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpF0(void) // SUBB ABS
- {
- tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
+ {
+ tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
}
static void OpF2(void) // SBCB ABS
{
- tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
+ tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 5;
- }
+ }
static void OpFB(void) // ADDB ABS
-{
+{
tmp = regs.RdMem(FetchW());
addr = (uint16)regs.b + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
// Page one opcodes' execute code
//
-static void Op1021(void) // LBRN
+static void Op1021(void) // LBRN
{
- addr = FetchW();
- regs.clock += 5;
+ addr = FetchW();
+
+ regs.clock += 5;
}
-static void Op1022(void) // LBHI
+
+static void Op1022(void) // LBHI
{
- addr = FetchW();
- if (!((regs.cc&0x01)|(regs.cc&0x04))) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (!((regs.cc & 0x01) | (regs.cc & 0x04)))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op1023(void) // LBLS
+
+static void Op1023(void) // LBLS
{
- addr = FetchW();
- if ((regs.cc&0x01)|(regs.cc&0x04)) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if ((regs.cc & 0x01) | (regs.cc & 0x04))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op1024(void) // LBCC (LBHS)
+
+static void Op1024(void) // LBCC (LBHS)
{
- addr = FetchW();
- if (!(regs.cc&0x01)) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (!(regs.cc & 0x01))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op1025(void) // LBCS (LBLO)
+
+static void Op1025(void) // LBCS (LBLO)
{
- addr = FetchW();
- if (regs.cc&0x01) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (regs.cc & 0x01)
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op1026(void) // LBNE
+
+static void Op1026(void) // LBNE
{
- addr = FetchW();
- if (!(regs.cc&0x04)) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (!(regs.cc & 0x04))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op1027(void) // LBEQ
+
+static void Op1027(void) // LBEQ
{
- addr = FetchW();
- if (regs.cc&0x04) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (regs.cc & 0x04)
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op1028(void) // LBVC
+
+static void Op1028(void) // LBVC
{
- addr = FetchW();
- if (!(regs.cc&0x02)) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (!(regs.cc & 0x02))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op1029(void) // LBVS
+
+static void Op1029(void) // LBVS
{
- addr = FetchW();
- if (regs.cc&0x02) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (regs.cc & 0x02)
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op102A(void) // LBPL
+
+static void Op102A(void) // LBPL
{
- addr = FetchW();
- if (!(regs.cc&0x08)) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (!(regs.cc & 0x08))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op102B(void) // LBMI
+
+static void Op102B(void) // LBMI
{
- addr = FetchW();
- if (regs.cc&0x08) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (regs.cc & 0x08)
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op102C(void) // LBGE
+
+static void Op102C(void) // LBGE
{
- addr = FetchW();
- if (!(((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op102D(void) // LBLT
+
+static void Op102D(void) // LBLT
{
- addr = FetchW();
- if (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op102E(void) // LBGT
+
+static void Op102E(void) // LBGT
{
- addr = FetchW();
- if (!((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)))) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))))
+ regs.pc += word;
+
+ regs.clock += 5;
}
-static void Op102F(void) // LBLE
+
+static void Op102F(void) // LBLE
{
- addr = FetchW();
- if ((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedW(addr);
- regs.clock += 5;
+ uint16 word = FetchW();
+
+ if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+ regs.pc += word;
+
+ regs.clock += 5;
}
+
static void Op103F(void) // SWI2 (Not yet implemented)
{
regs.clock += 20;
regs.cc &= 0xFD; // CLV
(regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
+ regs.clock += 6;
}
static void Op10DF(void) // STS DP
{
}
//temp, for testing...
-/*static uint8 backTrace[256];
+#ifdef __DEBUG__
+static uint8 backTrace[256];
static uint16 btPC[256];
static int btPtr = 0;//*/
+#endif
static void Op__(void) // Illegal opcode
{
regs.clock++;
// illegal = true;
regs.cpuFlags |= V6809_STATE_ILLEGAL_INST;
+#ifdef __DEBUG__
/*WriteLog("V6809: Executed illegal opcode %02X at PC=%04X...\n\nBacktrace:\n\n", regs.RdMem(regs.pc - 1), regs.pc - 1);
for(int i=0; i<256; i++)
{
- dpc = btPC[(btPtr+i)&0xFF];
- Decode_6809();
+ Decode6809(btPC[(btPtr + i) & 0xFF]);
+ WriteLog("\n");
}//*/
+#endif
}
//
// Function to execute 6809 instructions
//
+//#define DEBUG_ILLEGAL
+#ifdef DEBUG_ILLEGAL
+#include "log.h"
+#include "dis6809.h"
+uint8 btPtr = 0;
+uint8 backTrace[256];
+V6809REGS btRegs[256];
+bool tripped = false;
+#endif
void Execute6809(V6809REGS * context, uint32 cycles)
{
+ // If this is not in place, the clockOverrun calculations can cause the V6809 to get
+ // stuck in an infinite loop.
+ if (cycles == 0) // Nothing to do, so bail!
+ return;
+
myMemcpy(®s, context, sizeof(V6809REGS));
// Execute here...
- while (regs.clock < cycles)
+
+ // Since we can't guarantee that we'll execute the number of cycles passed in
+ // exactly, we have to keep track of how much we overran the number of cycles
+ // the last time we executed. Since we already executed those cycles, this time
+ // through we remove them from the cycles passed in in order to come out
+ // approximately even. Over the long run, this unevenness in execution times
+ // evens out.
+ uint64 endCycles = regs.clock + (uint64)(cycles - regs.clockOverrun);
+
+ while (regs.clock < endCycles)
+ {
+#ifdef DEBUG_ILLEGAL
+if (!tripped)
+{
+ backTrace[btPtr] = regs.RdMem(regs.pc);
+ btRegs[btPtr] = regs;
+ btPtr = (btPtr + 1) & 0xFF;
+
+ if (regs.cpuFlags & V6809_STATE_ILLEGAL_INST)
{
-/*static bool disasm = false;
-if (regs.pc == 0x15BA) disasm = true;
-if (disasm) { dpc = regs.pc; Decode_6809(); }
-if (regs.pc == 0x164A) disasm = false;//*/
+ WriteLog("V6809: Executed illegal instruction!!!!\n\nBacktrace:\n\n");
+ regs.cpuFlags &= ~V6809_STATE_ILLEGAL_INST;
+
+ for(uint16 i=btPtr; i<btPtr+256; i++)
+ {
+ Decode6809(btRegs[i & 0xFF].pc);
+// Note that these values are *before* execution, so stale...
+ WriteLog("\n\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+ btRegs[i & 0xFF].a, btRegs[i & 0xFF].b, btRegs[i & 0xFF].cc, btRegs[i & 0xFF].dp, btRegs[i & 0xFF].x, btRegs[i & 0xFF].y, btRegs[i & 0xFF].s, btRegs[i & 0xFF].u, btRegs[i & 0xFF].pc);//*/
+ }
+
+ tripped = true;
+ }
+}
+#endif
+#ifdef __DEBUG__
+//Decode6809(regs.pc);
+static bool disasm = false;
+/*//if (regs.pc == 0x15BA) disasm = true;
+//if (regs.pc == 0xFE76) disasm = true;
+if (regs.x == 0xFED4) disasm = true;
+if (disasm) Decode6809(regs.pc);
+//if (regs.pc == 0x164A) disasm = false;//*/
//temp, for testing...
/*backTrace[btPtr] = regs.RdMem(regs.pc);
btPC[btPtr] = regs.pc;
-btPtr = (btPtr++) & 0xFF;//*/
+btPtr = (btPtr + 1) & 0xFF;//*/
+#endif
exec_op0[regs.RdMem(regs.pc++)]();
// Handle any pending interrupts
if (flags & V6809_ASSERT_LINE_RESET) // *** RESET handler ***
{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: RESET line asserted!\n");
+#endif
regs.cc |= (FLAG_F | FLAG_I); // Set F, I
regs.dp = 0; // Reset direct page register
regs.pc = RdMemW(0xFFFE); // And load PC with the RESET vector
}
else if (flags & V6809_ASSERT_LINE_NMI) // *** NMI handler ***
{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: NMI line asserted!\n");
+#endif
regs.cc |= FLAG_E; // Set the Entire flag
regs.WrMem(--regs.s, regs.pc & 0xFF); // Save all regs...
regs.cc |= (FLAG_I | FLAG_F); // Set IRQ/FIRQ suppress flags
regs.pc = RdMemW(0xFFFC); // And load PC with the NMI vector
regs.clock += 19;
- context->cpuFlags &= ~V6809_ASSERT_LINE_NMI;// Reset the asserted line (NMI)...
- regs.cpuFlags &= ~V6809_ASSERT_LINE_NMI; // Reset the asserted line (NMI)...
+// context->cpuFlags &= ~V6809_ASSERT_LINE_NMI;// Reset the asserted line (NMI)...
+// regs.cpuFlags &= ~V6809_ASSERT_LINE_NMI; // Reset the asserted line (NMI)...
}
else if (flags & V6809_ASSERT_LINE_FIRQ) // *** FIRQ handler ***
{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: FIRQ line asserted!\n");
+#endif
if (!(regs.cc & FLAG_F)) // Is the FIRQ masked (F == 1)?
{
+#ifdef __DEBUG__
+if (disasm) WriteLog(" FIRQ taken...\n");
+#endif
regs.cc &= ~FLAG_E; // Clear the Entire flag
regs.WrMem(--regs.s, regs.pc & 0xFF); // Save PC, CC regs...
regs.cc |= (FLAG_I | FLAG_F); // Set IRQ/FIRQ suppress flags
regs.pc = RdMemW(0xFFF6); // And load PC with the IRQ vector
regs.clock += 10;
- context->cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
- regs.cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
+// context->cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
+// regs.cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
}
}
else if (flags & V6809_ASSERT_LINE_IRQ) // *** IRQ handler ***
{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: IRQ line asserted!\n");
+#endif
if (!(regs.cc & FLAG_I)) // Is the IRQ masked (I == 1)?
{
+#ifdef __DEBUG__
+if (disasm) WriteLog(" IRQ taken...\n");
+#endif
regs.cc |= FLAG_E; // Set the Entire flag
regs.WrMem(--regs.s, regs.pc & 0xFF); // Save all regs...
regs.cc |= FLAG_I; // Specs say that it doesn't affect FIRQ... or FLAG_F [WAS: Set IRQ/FIRQ suppress flags]
regs.pc = RdMemW(0xFFF8); // And load PC with the IRQ vector
regs.clock += 19;
- context->cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
- regs.cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
+// Apparently, not done here!
+// context->cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
+// regs.cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
}
}
-/*if (disasm) WriteLog("\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+#ifdef __DEBUG__
+if (disasm) WriteLog("\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
regs.a, regs.b, regs.cc, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
+/*WriteLog("\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+ regs.a, regs.b, regs.cc, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
+#endif
}
+ // Keep track of how much we overran so we can adjust on the next run...
+ regs.clockOverrun = (uint32)(regs.clock - endCycles);
+
myMemcpy(context, ®s, sizeof(V6809REGS));
}
//
// Get the clock of the currently executing CPU
//
-uint32 GetCurrentV6809Clock(void)
+uint64 GetCurrentV6809Clock(void)
{
return regs.clock;
}
+
+//
+// Get the PC of the currently executing CPU
+//
+uint16 GetCurrentV6809PC(void)
+{
+ return regs.pc;
+}
+
+// Set a line of the currently executing CPU
+void SetLine(uint32 line)
+{
+ regs.cpuFlags |= line;
+}
+
+// Clear a line of the currently executing CPU
+void ClearLine(uint32 line)
+{
+ regs.cpuFlags &= ~line;
+}
projects / stargem2 / blobdiff