//
-// Virtual 6809 v1.4
+// Virtual 6809 v1.4.2
//
-// by James L. Hammons
-// (c) 1997, 2009 Underground Software
+// by James Hammons
+// (C) 1997, 2009, 2014, 2023 Underground Software
//
-// JLH = James L. Hammons <jlhamm@acm.org>
+// JLH = James Hammons <jlhamm@acm.org>
//
// WHO WHEN WHAT
-// --- ---------- ------------------------------------------------------------
+// --- ---------- -----------------------------------------------------------
// JLH 06/15/2006 Added changelog ;-)
// JLH 06/15/2006 Scrubbed all BYTE, WORD & DWORD references from the code
// JLH 11/11/2006 Removed all SignedX() references
// JLH 09/29/2009 Converted V6809 to macro implementation!
+// JLH 04/17/2014 Misc. cleanups, fixes to missing instructions
+// JLH 01/03/2023 Added missing clock cycles to indexed memory accesses
//
-#define __DEBUG__
-
#include "v6809.h"
-#ifdef __DEBUG__
-#include "dis6809.h" // Temporary...
-#include "log.h" // Temporary...
-bool disasm = false;//so we can extern this shit
-#endif
-
#define TEST_DONT_BRANCH_OPTIMIZATION
// Various macros
#define SET_V(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x80) >> 7)
#define SET_V16(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x8000) >> 15)
#define SET_H(a,b,r) (flagH = (((a) ^ (b) ^ (r)) & 0x10) >> 4)
-
-//Not sure that this code is computing the carry correctly... Investigate! [Seems to be]
-//#define SET_C_ADD(a,b) (flagC = ((uint8)(b) > (uint8)(~(a)) ? 1 : 0))
-//#define SET_C_SUB(a,b) (regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
-//#define SET_C_CMP(a,b) (flagC = ((uint8)(b) >= (uint8)(a) ? 1 : 0))
#define SET_ZN(r) SET_N(r); SET_Z(r)
#define SET_ZN16(r) SET_N16(r); SET_Z(r)
-//#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
-//#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b)
-//#define SET_ZNC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b)
#define EA_IMM regs.pc++
#define EA_DP (regs.dp << 8) | regs.RdMem(regs.pc++)
#define READ_ABS regs.RdMem(EA_ABS)
#define READ_ABS16 RdMemW(EA_ABS)
-#define READ_IMM_WB(v) uint16 addr = EA_IMM; v = regs.RdMem(addr)
-#define READ_DP_WB(v) uint16 addr = EA_DP; v = regs.RdMem(addr)
-#define READ_IDX_WB(v) uint16 addr = EA_IDX; v = regs.RdMem(addr)
-#define READ_ABS_WB(v) uint16 addr = EA_ABS; v = regs.RdMem(addr)
+#define READ_IMM_WB(v) uint16_t addr = EA_IMM; v = regs.RdMem(addr)
+#define READ_DP_WB(v) uint16_t addr = EA_DP; v = regs.RdMem(addr)
+#define READ_IDX_WB(v) uint16_t addr = EA_IDX; v = regs.RdMem(addr)
+#define READ_ABS_WB(v) uint16_t addr = EA_ABS; v = regs.RdMem(addr)
#define WRITE_BACK(d) regs.WrMem(addr, (d))
// Private global variables
static V6809REGS regs;
-static uint8 flagE, flagF, flagH, flagI, flagN, flagZ, flagV, flagC;
+static uint8_t flagE, flagF, flagH, flagI, flagN, flagZ, flagV, flagC;
-uint8 page0Cycles[256] = {
+static const uint8_t page0Cycles[256] = {
6, 1, 1, 6, 6, 1, 6, 6, 6, 6, 6, 1, 6, 6, 3, 6, // $0x
1, 1, 2, 2, 1, 1, 5, 9, 1, 2, 3, 1, 3, 2, 8, 7, // $1x
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // $2x
5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6 // $Fx
};
-uint8 page1Cycles[256] = {
+static const uint8_t page1Cycles[256] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $0x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $1x
1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, // $2x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 7, 7 // $Fx
};
-uint8 page2Cycles[256] = {
+static const uint8_t page2Cycles[256] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $0x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $1x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $2x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 // $Fx
};
+// Cycle counts for PUL/PSHx instructions
+static uint8_t bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
+
// Private function prototypes
-static uint16 RdMemW(uint16 addr);
-static uint16 FetchMemW(uint16 addr);
-static void WrMemW(uint16 addr, uint16 w);
-static uint16 ReadEXG(uint8); // Read TFR/EXG post byte
-static void WriteEXG(uint8, uint16); // Set TFR/EXG data
-static uint16 DecodeReg(uint8); // Decode register data
-static uint16 DecodeIDX(uint8); // Decode IDX data
+static uint16_t RdMemW(uint16_t addr);
+static uint16_t FetchMemW(uint16_t addr);
+static void WrMemW(uint16_t addr, uint16_t w);
+static uint16_t ReadEXG(uint8_t); // Read TFR/EXG post byte
+static void WriteEXG(uint8_t, uint16_t); // Set TFR/EXG data
+static uint16_t DecodeReg(uint8_t); // Decode register data
+static uint16_t DecodeIDX(uint8_t); // Decode IDX data
//
// Read word from memory function
//
-static inline uint16 RdMemW(uint16 addr)
+static inline uint16_t RdMemW(uint16_t addr)
{
- return (uint16)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
+ return (uint16_t)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
}
//
// Fetch a word from memory function. Increments PC
//
-static inline uint16 FetchMemW(uint16 addr)
+static inline uint16_t FetchMemW(uint16_t addr)
{
regs.pc += 2;
- return (uint16)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
+ return (uint16_t)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
}
//
// Write word to memory function
//
-static inline void WrMemW(uint16 addr, uint16 w)
+static inline void WrMemW(uint16_t addr, uint16_t w)
{
regs.WrMem(addr + 0, w >> 8);
regs.WrMem(addr + 1, w & 0xFF);
//
// Function to read TFR/EXG post byte
//
-uint16 ReadEXG(uint8 code)
+static uint16_t ReadEXG(uint8_t code)
{
- uint16 retval;
+ uint16_t retval;
switch (code)
{
//
// Function to set TFR/EXG data
//
-void WriteEXG(uint8 code, uint16 data)
+static void WriteEXG(uint8_t code, uint16_t data)
{
switch (code)
{
//
// Function to decode register data
//
-uint16 DecodeReg(uint8 reg)
+static uint16_t DecodeReg(uint8_t reg)
{
- uint16 retval;
+ uint16_t retval;
switch (reg)
{
//
// Function to decode IDX data
//
-uint16 DecodeIDX(uint8 code)
+static uint16_t DecodeIDX(uint8_t code)
{
- uint16 addr, woff;
- uint8 reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
+/*
+Cycle counts are now taken into account here...
+
+ 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+90 5 6 5 6 3 4 4 0 4 7 0 7 4 8 0 5
+B0 5 6 5 6 3 4 4 0 4 7 0 7 4 8 0 5
+D0 5 6 5 6 3 4 4 0 4 7 0 7 4 8 0 5
+F0 5 6 5 6 3 4 4 0 4 7 0 7 4 8 0 5
+
+80 2 3 2 3 0 1 1 0 1 4 0 4 1 5 0 5
+A0 2 3 2 3 0 1 1 0 1 4 0 4 1 5 0 5
+C0 2 3 2 3 0 1 1 0 1 4 0 4 1 5 0 5
+E0 2 3 2 3 0 1 1 0 1 4 0 4 1 5 0 5
+*/
+ uint16_t addr, woff;
+ int16_t offset;
+ uint8_t reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
if (!(code & 0x80)) // Hi bit unset? Then decode 4 bit offset
+ {
addr = DecodeReg(reg) + (idxind ? lo_nyb - 16 : lo_nyb);
+ regs.clock++;
+ }
else
{
if (idxind)
case 2: regs.u += 2; break;
case 3: regs.s += 2; break;
}
+ regs.clock += 6;
break;
case 3:
switch (reg)
}
woff = DecodeReg(reg);
addr = RdMemW(woff);
+ regs.clock += 6;
break;
case 4:
woff = DecodeReg(reg);
addr = RdMemW(woff);
+ regs.clock += 3;
break;
case 5:
- woff = DecodeReg(reg) + (int16)(int8)regs.b;
+ woff = DecodeReg(reg) + (int16_t)(int8_t)regs.b;
addr = RdMemW(woff);
+ regs.clock += 4;
break;
case 6:
- woff = DecodeReg(reg) + (int16)(int8)regs.a;
+ woff = DecodeReg(reg) + (int16_t)(int8_t)regs.a;
addr = RdMemW(woff);
+ regs.clock += 4;
break;
case 8:
- woff = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++);
+ woff = DecodeReg(reg) + (int16_t)(int8_t)regs.RdMem(regs.pc++);
addr = RdMemW(woff);
+ regs.clock += 4;
break;
case 9:
woff = DecodeReg(reg) + FetchMemW(regs.pc);
addr = RdMemW(woff);
+ regs.clock += 7;
break;
case 11:
woff = DecodeReg(reg) + ((regs.a << 8) | regs.b);
addr = RdMemW(woff);
+ regs.clock += 7;
break;
case 12:
- woff = regs.pc + (int16)(int8)regs.RdMem(regs.pc++);
+// woff = regs.pc + (int16_t)(int8_t)regs.RdMem(regs.pc++);
+#if 1
+ // I believe this is the correct interpretation
+ offset = (int16_t)(int8_t)regs.RdMem(regs.pc++);
+ woff = regs.pc + offset;
+#else
+ woff = regs.pc + (int16_t)(int8_t)regs.RdMem(regs.pc);
+ regs.pc++;
+#endif
addr = RdMemW(woff);
+ regs.clock += 4;
break;
case 13:
woff = regs.pc + FetchMemW(regs.pc);
addr = RdMemW(woff);
+ regs.clock += 8;
break;
case 15:
woff = FetchMemW(regs.pc);
addr = RdMemW(woff);
+ regs.clock += 5;
break;
+ default:
+ addr = 0;
}
}
else
case 2: regs.u++; break;
case 3: regs.s++; break;
}
+ regs.clock += 2;
break;
case 1:
addr = DecodeReg(reg);
case 2: regs.u += 2; break;
case 3: regs.s += 2; break;
}
+ regs.clock += 3;
+ break;
+ case 2:
+ switch(reg)
+ {
+ case 0: regs.x--; break;
+ case 1: regs.y--; break;
+ case 2: regs.u--; break;
+ case 3: regs.s--; break;
+ }
+ addr = DecodeReg(reg);
+ regs.clock += 2;
+ break;
+ case 3:
+ switch(reg)
+ {
+ case 0: regs.x -= 2; break;
+ case 1: regs.y -= 2; break;
+ case 2: regs.u -= 2; break;
+ case 3: regs.s -= 2; break;
+ }
+ addr = DecodeReg(reg);
+ regs.clock += 3;
+ break;
+ case 4:
+ addr = DecodeReg(reg);
+ break;
+ case 5:
+ addr = DecodeReg(reg) + (int16_t)(int8_t)regs.b;
+ regs.clock++;
+ break;
+ case 6:
+ addr = DecodeReg(reg) + (int16_t)(int8_t)regs.a;
+ regs.clock++;
+ break;
+ case 8:
+ addr = DecodeReg(reg) + (int16_t)(int8_t)regs.RdMem(regs.pc++);
+ regs.clock++;
+ break;
+ case 9:
+ addr = DecodeReg(reg) + FetchMemW(regs.pc);
+ regs.clock += 4;
break;
- case 2: { switch(reg)
- {
- case 0: regs.x--; break;
- case 1: regs.y--; break;
- case 2: regs.u--; break;
- case 3: regs.s--; break;
- }
- addr = DecodeReg(reg); break; }
- case 3: { switch(reg)
- {
- case 0: regs.x--; regs.x--; break;
- case 1: regs.y--; regs.y--; break;
- case 2: regs.u--; regs.u--; break;
- case 3: regs.s--; regs.s--; break;
- }
- addr = DecodeReg(reg); break; }
- case 4: { addr = DecodeReg(reg); break; }
- case 5: { addr = DecodeReg(reg) + (int16)(int8)regs.b; break; }
- case 6: { addr = DecodeReg(reg) + (int16)(int8)regs.a; break; }
- case 8: { addr = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++); break; }
- case 9: { addr = DecodeReg(reg) + FetchMemW(regs.pc); break; }
- case 11: { addr = DecodeReg(reg) + ((regs.a << 8) | regs.b); break; }
- case 12: { addr = regs.pc + (int16)(int8)regs.RdMem(regs.pc++); break; }
- case 13: { addr = regs.pc + FetchMemW(regs.pc); break; }
+ case 11:
+ addr = DecodeReg(reg) + ((regs.a << 8) | regs.b);
+ regs.clock += 4;
+ break;
+ case 12:
+// addr = regs.pc + (int16_t)(int8_t)regs.RdMem(regs.pc++);
+#if 1
+ // I believe this is the correct interpretation of the above
+ offset = (int16_t)(int8_t)regs.RdMem(regs.pc++);
+ addr = regs.pc + offset;
+#else
+ addr = regs.pc + (int16_t)(int8_t)regs.RdMem(regs.pc);
+ regs.pc++;
+#endif
+ regs.clock++;
+ break;
+ case 13:
+ addr = regs.pc + FetchMemW(regs.pc);
+ regs.clock += 5;
+ break;
+ default:
+ addr = 0;
}
}
}
//
// 6809 OPCODE IMPLEMENTATION
//
-// NOTE: Lots of macros are used here to save a LOT of typing. Also
-// helps speed the debugging process. :-) Because of this, combining
+// NOTE: Lots of macros are used here to save a LOT of typing. Also
+// helps speed the debugging process. :-) Because of this, combining
// certain lines may look like a good idea but would end in disaster.
-// You have been warned! ;-)
+// You have been warned! ;-)
//
/*
// ADC opcodes
#define OP_ADC_HANDLER(m, acc) \
- uint16 sum = (uint16)acc + (m) + (uint16)flagC; \
+ uint16_t sum = (uint16_t)acc + (m) + (uint16_t)flagC; \
flagC = (sum >> 8) & 0x01; \
SET_H(m, acc, sum); \
SET_V(m, acc, sum); \
acc = sum & 0xFF; \
SET_ZN(acc)
-/*
-Old flag handling code:
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
-*/
-
static void Op89(void) // ADCA #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADC_HANDLER(m, regs.a);
}
static void Op99(void) // ADCA DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADC_HANDLER(m, regs.a);
}
static void OpA9(void) // ADCA IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADC_HANDLER(m, regs.a);
}
static void OpB9(void) // ADCA ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADC_HANDLER(m, regs.a);
}
static void OpC9(void) // ADCB #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADC_HANDLER(m, regs.b);
}
static void OpD9(void) // ADCB DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADC_HANDLER(m, regs.b);
}
static void OpE9(void) // ADCB IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADC_HANDLER(m, regs.b);
}
static void OpF9(void) // ADCB ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADC_HANDLER(m, regs.b);
}
// ADD opcodes
#define OP_ADD_HANDLER(m, acc) \
- uint16 sum = (uint16)(acc) + (m); \
+ uint16_t sum = (uint16_t)(acc) + (m); \
flagC = (sum >> 8) & 0x01; \
SET_H(m, acc, sum); \
SET_V(m, acc, sum); \
SET_ZN(acc)
#define OP_ADD_HANDLER16(m, hireg, loreg) \
- uint32 acc = (uint32)((hireg << 8) | loreg); \
- uint32 sum = acc + (m); \
+ uint32_t acc = (uint32_t)((hireg << 8) | loreg); \
+ uint32_t sum = acc + (m); \
flagC = (sum >> 16) & 0x01; \
SET_V16(m, acc, sum); \
acc = sum & 0xFFFF; \
loreg = acc & 0xFF; \
SET_ZN16(acc)
-/*
-Old flags:
- (addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
-
- dr += addr;
- (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- dr &= 0xFFFF;
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 4;
-*/
-
static void Op3A(void) // ABX
{
- regs.x += (uint16)regs.b;
+ regs.x += (uint16_t)regs.b;
}
static void Op8B(void) // ADDA #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADD_HANDLER(m, regs.a);
}
static void Op9B(void) // ADDA DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADD_HANDLER(m, regs.a);
}
static void OpAB(void) // ADDA IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADD_HANDLER(m, regs.a);
}
static void OpBB(void) // ADDA ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADD_HANDLER(m, regs.a);
}
static void OpC3(void) // ADDD #
{
- uint32 m = READ_IMM16;
+ uint32_t m = READ_IMM16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpCB(void) // ADDB #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADD_HANDLER(m, regs.b);
}
static void OpD3(void) // ADDD DP
{
- uint32 m = READ_DP16;
+ uint32_t m = READ_DP16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpDB(void) // ADDB DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADD_HANDLER(m, regs.b);
}
static void OpE3(void) // ADDD IDX
{
- uint32 m = READ_IDX16;
+ uint32_t m = READ_IDX16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpEB(void) // ADDB IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADD_HANDLER(m, regs.b);
}
static void OpF3(void) // ADDD ABS
{
- uint32 m = READ_ABS16;
+ uint32_t m = READ_ABS16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpFB(void) // ADDB ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADD_HANDLER(m, regs.b);
}
static void Op84(void) // ANDA #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_AND_HANDLER(m, regs.a);
}
static void Op94(void) // ANDA DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_AND_HANDLER(m, regs.a);
}
static void OpA4(void) // ANDA IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_AND_HANDLER(m, regs.a);
}
static void OpB4(void) // ANDA ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_AND_HANDLER(m, regs.a);
}
static void OpC4(void) // ANDB #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_AND_HANDLER(m, regs.b);
}
static void OpD4(void) // ANDB DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_AND_HANDLER(m, regs.b);
}
static void OpE4(void) // ANDB IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_AND_HANDLER(m, regs.b);
}
static void OpF4(void) // ANDB ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_AND_HANDLER(m, regs.b);
}
// ASL opcodes
#define OP_ASL_HANDLER(m) \
- uint16 res = m << 1; \
+ uint16_t res = m << 1; \
SET_V(m, m, res); \
flagC = (res >> 8) & 0x01; \
m = res & 0xFF; \
static void Op08(void) // ASL DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op68(void) // ASL IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op78(void) // ASL ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
// ASR opcodes (arithmetic, so preserves the sign)
#define OP_ASR_HANDLER(m) \
- uint8 res = (m & 0x80) | (m >> 1); \
+ uint8_t res = (m & 0x80) | (m >> 1); \
SET_ZN(res); \
flagC = m & 0x01; \
m = res
static void Op07(void) // ASR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ASR_HANDLER(m);
WRITE_BACK(m);
static void Op67(void) // ASR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ASR_HANDLER(m);
WRITE_BACK(m);
static void Op77(void) // ASR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ASR_HANDLER(m);
WRITE_BACK(m);
static void Op16(void) // LBRA
{
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
regs.pc += offset;
}
static void Op20(void) // BRA
{
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
regs.pc += offset;
}
static void Op21(void) // BRN
{
// This is basically a 2 byte NOP
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
}
static void Op22(void) // BHI
{
// !C && !Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
//Not sure if the ! operator will do what we want, so we use ^ 1 (we need a 1 or a 0 here)...
static void Op23(void) // BLS
{
// C || Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | flagC);
static void Op24(void) // BHS/CC
{
// !C
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagC ^ 0x01);
static void Op25(void) // BLO/CS
{
// C
- int16 offset = (int16)(int8)READ_IMM;
-//if (disasm)
-// WriteLog("[offset=%04X,flagC=%08X]", offset, flagC);
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagC;
static void Op26(void) // BNE
{
// !Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ ^ 0x01);
static void Op27(void) // BEQ
{
// Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagZ;
static void Op28(void) // BVC
{
// !V
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagV ^ 0x01);
static void Op29(void) // BVS
{
// V
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagV;
static void Op2A(void) // BPL
{
// !N
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagN ^ 0x01);
static void Op2B(void) // BMI
{
// N
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagN;
static void Op2C(void) // BGE
{
// (N && V) || (!N && !V)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV) | ((flagN ^ 0x01) & (flagV ^ 0x01)));
static void Op2D(void) // BLT
{
// (N && !V) || (!N && V)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
static void Op2E(void) // BGT
{
// (N && V && !Z) || (!N && !V && !Z)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV & (flagZ ^ 0x01)) | ((flagN ^ 0x01) & (flagV ^ 0x01) & (flagZ ^ 0x01)));
static void Op2F(void) // BLE
{
// Z || (N && !V) || (!N && V)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | (flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
static void Op1021(void) // LBRN
{
// This is basically a 4 byte NOP
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
}
static void Op1022(void) // LBHI
{
// !C && !Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
//Not sure if the ! operator will do what we want, so we use ^ 1 (we need a 1 or a 0 here)...
static void Op1023(void) // LBLS
{
// C || Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | flagC);
static void Op1024(void) // LBHS/CC
{
// !C
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagC ^ 0x01);
static void Op1025(void) // LBLO/CS
{
// C
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagC;
static void Op1026(void) // LBNE
{
// !Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ ^ 0x01);
static void Op1027(void) // LBEQ
{
// Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagZ;
static void Op1028(void) // LBVC
{
// !V
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagV ^ 0x01);
static void Op1029(void) // LBVS
{
// V
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagV;
static void Op102A(void) // LBPL
{
// !N
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagN ^ 0x01);
static void Op102B(void) // LBMI
{
// N
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagN;
static void Op102C(void) // LBGE
{
// (N && V) || (!N && !V)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV) | ((flagN ^ 0x01) & (flagV ^ 0x01)));
static void Op102D(void) // LBLT
{
// (N && !V) || (!N && V)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
static void Op102E(void) // LBGT
{
// (N && V && !Z) || (!N && !V && !Z)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV & (flagZ ^ 0x01)) | ((flagN ^ 0x01) & (flagV ^ 0x01) & (flagZ ^ 0x01)));
static void Op102F(void) // LBLE
{
// Z || (N && !V) || (!N && V)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | (flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
// BIT opcodes
#define OP_BIT_HANDLER(m, acc) \
- uint8 result = acc & (m); \
+ uint8_t result = acc & (m); \
SET_ZN(result); \
CLR_V
static void Op85(void) // BITA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_BIT_HANDLER(m, regs.a);
}
static void Op95(void) // BITA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_BIT_HANDLER(m, regs.a);
}
static void OpA5(void) // BITA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_BIT_HANDLER(m, regs.a);
}
static void OpB5(void) // BITA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_BIT_HANDLER(m, regs.a);
}
static void OpC5(void) // BITB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_BIT_HANDLER(m, regs.b);
}
static void OpD5(void) // BITB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_BIT_HANDLER(m, regs.b);
}
static void OpE5(void) // BITB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_BIT_HANDLER(m, regs.b);
}
static void OpF5(void) // BITB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_BIT_HANDLER(m, regs.b);
}
static void Op0F(void) // CLR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_CLR_HANDLER(m);
WRITE_BACK(m);
static void Op6F(void) // CLR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_CLR_HANDLER(m);
WRITE_BACK(m);
static void Op7F(void) // CLR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_CLR_HANDLER(m);
WRITE_BACK(m);
// CMP opcodes
#define OP_CMP_HANDLER(m, acc) \
- uint16 sum = (uint16)(acc) - (m); \
+ uint16_t sum = (uint16_t)(acc) - (m); \
flagC = (sum >> 8) & 0x01; \
SET_V(m, acc, sum); \
SET_ZN(sum)
#define OP_CMP_HANDLER16(m, acc) \
- uint32 sum = (uint32)(acc) - (m); \
+ uint32_t sum = (uint32_t)(acc) - (m); \
flagC = (sum >> 16) & 0x01; \
SET_V16(m, acc, sum); \
SET_ZN16(sum)
static void Op81(void) // CMPA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_CMP_HANDLER(m, regs.a);
}
static void Op8C(void) // CMPX #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.x);
}
static void Op91(void) // CMPA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_CMP_HANDLER(m, regs.a);
}
static void Op9C(void) // CMPX DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.x);
}
static void OpA1(void) // CMPA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_CMP_HANDLER(m, regs.a);
}
static void OpAC(void) // CMPX IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.x);
}
static void OpB1(void) // CMPA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_CMP_HANDLER(m, regs.a);
}
static void OpBC(void) // CMPX ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.x);
}
static void OpC1(void) // CMPB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_CMP_HANDLER(m, regs.b);
}
static void OpD1(void) // CMPB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_CMP_HANDLER(m, regs.b);
}
static void OpE1(void) // CMPB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_CMP_HANDLER(m, regs.b);
}
static void OpF1(void) // CMPB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_CMP_HANDLER(m, regs.b);
}
static void Op1083(void) // CMPD #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op108C(void) // CMPY #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op1093(void) // CMPD DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op109C(void) // CMPY DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op10A3(void) // CMPD IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op10AC(void) // CMPY IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op10B3(void) // CMPD ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op10BC(void) // CMPY ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op1183(void) // CMPU #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op118C(void) // CMPS #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op1193(void) // CMPU DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op119C(void) // CMPS DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op11A3(void) // CMPU IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op11AC(void) // CMPS IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op11B3(void) // CMPU ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op11BC(void) // CMPS ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op03(void) // COM DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_COM_HANDLER(m);
WRITE_BACK(m);
static void Op63(void) // COM IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_COM_HANDLER(m);
WRITE_BACK(m);
static void Op73(void) // COM ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_COM_HANDLER(m);
WRITE_BACK(m);
static void Op3E(void) // RESET
{
- regs.cpuFlags |= V6809_ASSERT_LINE_RESET;
+ regs.cpuFlags |= V6809_LINE_RESET;
}
static void Op3F(void) // SWI
{
}
-/*
-D3F8: A6 47 LDA (7),U CC=--H----- A=30 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FA
-D3FA: 8B 01 ADDA #$01 CC=--H----- A=31 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FC
-D3FC: 19 DAA CC=--H----- A=37 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FD
-*/
-
static void Op19() // DAA
{
- uint16 result = (uint16)regs.a;
+ uint16_t result = (uint16_t)regs.a;
-// if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H))
if ((regs.a & 0x0F) > 0x09 || flagH)
result += 0x06;
-// if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09))
if ((regs.a & 0xF0) > 0x90 || flagC || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09))
result += 0x60;
- regs.a = (uint8)result;
+ regs.a = (uint8_t)result;
SET_ZN(result);
CLR_V;
flagC |= (result & 0x100) >> 8; // Overwrite carry if it was 0, otherwise, ignore
static void Op0A(void) // DEC DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void Op6A(void) // DEC IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void Op7A(void) // DEC ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void Op88(void) // EORA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_EOR_HANDLER(m, regs.a);
}
static void Op98(void) // EORA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_EOR_HANDLER(m, regs.a);
}
static void OpA8(void) // EORA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_EOR_HANDLER(m, regs.a);
}
static void OpB8(void) // EORA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_EOR_HANDLER(m, regs.a);
}
static void OpC8(void) // EORB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_EOR_HANDLER(m, regs.b);
}
static void OpD8(void) // EORB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_EOR_HANDLER(m, regs.b);
}
static void OpE8(void) // EORB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_EOR_HANDLER(m, regs.b);
}
static void OpF8(void) // EORB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_EOR_HANDLER(m, regs.b);
}
static void Op0C(void) // INC DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void Op6C(void) // INC IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void Op7C(void) // INC ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void Op0E(void) // JMP DP
{
- regs.pc = EA_DP;
+ // This needs to be separate because of the EA_DP adding to regs.pc.
+ uint16_t m = EA_DP;
+ regs.pc = m;
}
static void Op17(void) // LBSR
{
- uint16 word = FetchMemW(regs.pc);
+ uint16_t word = FetchMemW(regs.pc);
PUSHS16(regs.pc);
regs.pc += word;
}
static void Op8D(void) // BSR
{
- uint16 word = (int16)(int8)READ_IMM;
+ uint16_t word = (int16_t)(int8_t)READ_IMM;
PUSHS16(regs.pc);
regs.pc += word;
}
static void Op9D(void) // JSR DP
{
- uint16 word = EA_DP;
+ uint16_t word = EA_DP;
PUSHS16(regs.pc);
regs.pc = word;
}
static void OpAD(void) // JSR IDX
{
- uint16 word = EA_IDX;
+ uint16_t word = EA_IDX;
PUSHS16(regs.pc);
regs.pc = word;
}
static void OpBD(void) // JSR ABS
{
- uint16 word = EA_ABS;
+ uint16_t word = EA_ABS;
PUSHS16(regs.pc);
regs.pc = word;
}
{
// If bit 3 & 7 are not equal, $FF is the result (undocumented)...
- uint8 m = READ_IMM;
- uint8 reg1 = m >> 4, reg2 = m & 0x0F;
- uint16 acc1 = ReadEXG(reg1);
- uint16 acc2 = ReadEXG(reg2);
+ uint8_t m = READ_IMM;
+ uint8_t reg1 = m >> 4, reg2 = m & 0x0F;
+ uint16_t acc1 = ReadEXG(reg1);
+ uint16_t acc2 = ReadEXG(reg2);
// If bit 3 & 7 are not equal, $FF is the result (undocumented)...
if (((m >> 4) ^ m) & 0x08)
static void Op1F(void) // TFR
{
- uint8 m = READ_IMM;
- uint16 acc = ReadEXG(m >> 4);
+ uint8_t m = READ_IMM;
+ uint16_t acc = ReadEXG(m >> 4);
// If bit 3 & 7 are not equal, $FF is the result (undocumented)...
if (((m >> 4) ^ m) & 0x08)
static void Op86(void) // LDA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_LDA_HANDLER(m, regs.a);
}
static void Op8E(void) // LDX #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.x);
}
static void Op96(void) // LDA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_LDA_HANDLER(m, regs.a);
}
static void Op9E(void) // LDX DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.x);
}
static void OpA6(void) // LDA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_LDA_HANDLER(m, regs.a);
}
static void OpAE(void) // LDX IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.x);
}
static void OpB6(void) // LDA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_LDA_HANDLER(m, regs.a);
}
static void OpBE(void) // LDX ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.x);
}
static void OpC6(void) // LDB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_LDA_HANDLER(m, regs.b);
}
static void OpCC(void) // LDD #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16D(m);
}
static void OpCE(void) // LDU #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.u);
}
static void OpD6(void) // LDB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_LDA_HANDLER(m, regs.b);
}
static void OpDC(void) // LDD DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16D(m);
}
static void OpDE(void) // LDU DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.u);
}
static void OpE6(void) // LDB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_LDA_HANDLER(m, regs.b);
}
static void OpEC(void) // LDD IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16D(m);
}
static void OpEE(void) // LDU IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.u);
}
static void OpF6(void) // LDB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_LDA_HANDLER(m, regs.b);
}
static void OpFC(void) // LDD ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16D(m);
}
static void OpFE(void) // LDU ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.u);
}
static void Op108E(void) // LDY #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op109E(void) // LDY DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op10AE(void) // LDY IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op10BE(void) // LDY ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op10CE(void) // LDS #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op10DE(void) // LDS DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op10EE(void) // LDS IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op10FE(void) // LDS ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op04(void) // LSR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op64(void) // LSR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op74(void) // LSR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op3D(void) // MUL
{
- uint16 prod = regs.a * regs.b;
+ uint16_t prod = regs.a * regs.b;
regs.a = prod >> 8;
regs.b = prod & 0xFF;
SET_Z(prod);
// NEG opcodes
#define OP_NEG_HANDLER(m) \
- uint8 res = -m; \
+ uint8_t res = -m; \
SET_ZN(res); \
SET_V(0, m, res); \
flagC = (res >= 0x80 ? 1 : 0); \
m = res
-/*
- UINT16 r,t;
- DIRBYTE(t);
- r = -t;
- CLR_NZVC;
- SET_FLAGS8(0,t,r);
- WM(EAD,r);
-#define SET_FLAGS8(a,b,r) {SET_N8(r);SET_Z8(r);SET_V8(a,b,r);SET_C8(r);}
-#define SET_C8(a) CC|=((a&0x100)>>8)
-*/
static void Op00(void) // NEG DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_NEG_HANDLER(m);
WRITE_BACK(m);
static void Op60(void) // NEG IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_NEG_HANDLER(m);
WRITE_BACK(m);
static void Op70(void) // NEG ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_NEG_HANDLER(m);
WRITE_BACK(m);
static void Op8A(void) // ORA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_OR_HANDLER(m, regs.a);
}
static void Op9A(void) // ORA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_OR_HANDLER(m, regs.a);
}
static void OpAA(void) // ORA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_OR_HANDLER(m, regs.a);
}
static void OpBA(void) // ORA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_OR_HANDLER(m, regs.a);
}
static void OpCA(void) // ORB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_OR_HANDLER(m, regs.b);
}
static void OpDA(void) // ORB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_OR_HANDLER(m, regs.b);
}
static void OpEA(void) // ORB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_OR_HANDLER(m, regs.b);
}
static void OpFA(void) // ORB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_OR_HANDLER(m, regs.b);
}
static void Op34(void) // PSHS
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x80)
PUSHS16(regs.pc);
}
// Count bits in each nybble to come up with correct cycle counts...
- uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
static void Op35(void) // PULS
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x01)
{
PULLS16(regs.pc);
// Count bits in each nybble to come up with correct cycle counts...
- uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
static void Op36(void) // PHSU
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x80)
PUSHU16(regs.pc);
}
// Count bits in each nybble to come up with correct cycle counts...
- uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
static void Op37(void) // PULU
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x01)
{
PULLU16(regs.pc);
// Count bits in each nybble to come up with correct cycle counts...
- uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
// ROL opcodes
#define OP_ROL_HANDLER(m) \
- uint8 res = (m << 1) | flagC; \
+ uint8_t res = (m << 1) | flagC; \
SET_ZN(res); \
SET_V(m, m, res); \
flagC = (m >> 7) & 0x01; \
m = res
-/*
- UINT16 t,r;
- DIRBYTE(t);
- r = (CC & CC_C) | (t << 1);
- CLR_NZVC;
- SET_FLAGS8(t,t,r);
- WM(EAD,r);
-*/
static void Op09(void) // ROL DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
static void Op69(void) // ROL IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
static void Op79(void) // ROL ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
// ROR opcodes
#define OP_ROR_HANDLER(m) \
- uint8 res = (flagC << 7) | (m >> 1); \
+ uint8_t res = (flagC << 7) | (m >> 1); \
SET_ZN(res); \
SET_V(m, m, res); \
flagC = m & 0x01; \
static void Op06(void) // ROR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op66(void) // ROR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op76(void) // ROR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
// SBC opcodes
#define OP_SBC_HANDLER(m, acc) \
- uint16 sum = (uint16)acc - (m) - (uint16)flagC; \
+ uint16_t sum = (uint16_t)acc - (m) - (uint16_t)flagC; \
flagC = (sum >> 8) & 0x01; \
SET_V(m, acc, sum); \
- acc = (uint8)sum; \
+ acc = (uint8_t)sum; \
SET_ZN(acc)
static void Op82(void) // SBCA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SBC_HANDLER(m, regs.a);
}
static void Op92(void) // SBCA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SBC_HANDLER(m, regs.a);
}
static void OpA2(void) // SBCA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SBC_HANDLER(m, regs.a);
}
static void OpB2(void) // SBCA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SBC_HANDLER(m, regs.a);
}
static void OpC2(void) // SBCB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SBC_HANDLER(m, regs.b);
}
static void OpD2(void) // SBCB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SBC_HANDLER(m, regs.b);
}
static void OpE2(void) // SBCB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SBC_HANDLER(m, regs.b);
}
static void OpF2(void) // SBCB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SBC_HANDLER(m, regs.b);
}
static void Op97(void) // STA DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER(addr, regs.a);
}
static void Op9F(void) // STX DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.x);
}
static void OpA7(void) // STA IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER(addr, regs.a);
}
static void OpAF(void) // STX IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.x);
}
static void OpB7(void) // STA ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER(addr, regs.a);
}
static void OpBF(void) // STX ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.x);
}
static void OpD7(void) // STB DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER(addr, regs.b);
}
static void OpDD(void) // STD DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, (regs.a << 8) | regs.b);
}
static void OpDF(void) // STU DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.u);
}
static void OpE7(void) // STB IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER(addr, regs.b);
}
static void OpED(void) // STD IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, (regs.a << 8) | regs.b);
}
static void OpEF(void) // STU IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.u);
}
static void OpF7(void) // STB ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER(addr, regs.b);
}
static void OpFD(void) // STD ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, (regs.a << 8) | regs.b);
}
static void OpFF(void) // STU ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.u);
}
static void Op109F(void) // STY DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.y);
}
static void Op10AF(void) // STY IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.y);
}
static void Op10BF(void) // STY ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.y);
}
static void Op10DF(void) // STS DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.s);
}
static void Op10EF(void) // STS IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.s);
}
static void Op10FF(void) // STS ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.s);
}
// SUB opcodes
#define OP_SUB_HANDLER(m, acc) \
- uint16 sum = (uint16)acc - (m); \
+ uint16_t sum = (uint16_t)acc - (m); \
flagC = (sum >> 8) & 0x01; \
SET_V(m, acc, sum); \
- acc = (uint8)sum; \
+ acc = (uint8_t)sum; \
SET_ZN(acc)
#define OP_SUB_HANDLER16D(m) \
- uint32 acc = (uint32)((regs.a << 8) | regs.b); \
- uint32 sum = acc - (m); \
+ uint32_t acc = (uint32_t)((regs.a << 8) | regs.b); \
+ uint32_t sum = acc - (m); \
flagC = (sum >> 16) & 0x01; \
SET_V16(m, acc, sum); \
acc = sum & 0xFFFF; \
static void Op80(void) // SUBA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SUB_HANDLER(m, regs.a);
}
static void Op83(void) // SUBD #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_SUB_HANDLER16D(m);
}
static void Op90(void) // SUBA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SUB_HANDLER(m, regs.a);
}
static void Op93(void) // SUBD DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_SUB_HANDLER16D(m);
}
static void OpA0(void) // SUBA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SUB_HANDLER(m, regs.a);
}
static void OpA3(void) // SUBD IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_SUB_HANDLER16D(m);
}
static void OpB0(void) // SUBA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SUB_HANDLER(m, regs.a);
}
static void OpB3(void) // SUBD ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_SUB_HANDLER16D(m);
}
static void OpC0(void) // SUBB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SUB_HANDLER(m, regs.b);
}
static void OpD0(void) // SUBB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SUB_HANDLER(m, regs.b);
}
static void OpE0(void) // SUBB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SUB_HANDLER(m, regs.b);
}
static void OpF0(void) // SUBB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SUB_HANDLER(m, regs.b);
}
static void Op0D(void) // TST DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_TST_HANDLER(m);
}
static void Op6D(void) // TST IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_TST_HANDLER(m);
}
static void Op7D(void) // TST ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_TST_HANDLER(m);
}
+//
// Undocumented Opcodes
-
+//
static void Op01(void)
{
Op00(); // NEG DP
}
-
-//temp, for testing...
-#ifdef __DEBUG__
-static uint8 backTrace[256];
-static uint16 btPC[256];
-static int btPtr = 0;//*/
-#endif
-static void Op__(void) // Illegal opcode
+static void Op__(void) // Illegal opcode
{
regs.clock++;
-// illegal = true;
regs.cpuFlags |= V6809_STATE_ILLEGAL_INST;
-#ifdef __DEBUG__
-/*WriteLog("V6809: Executed illegal opcode %02X at PC=%04X...\n\nBacktrace:\n\n", regs.RdMem(regs.pc - 1), regs.pc - 1);
-for(int i=0; i<256; i++)
-{
- Decode6809(btPC[(btPtr + i) & 0xFF]);
- WriteLog("\n");
-}//*/
-#endif
}
//
// Page 1 opcode
static void Op10(void)
{
-// exec_op1[regs.RdMem(regs.pc++)]();
- uint8 opcode = regs.RdMem(regs.pc++);
+ uint8_t opcode = regs.RdMem(regs.pc++);
exec_op1[opcode]();
regs.clock += page1Cycles[opcode];
}
// Page 2 opcode
static void Op11(void)
{
-// exec_op2[regs.RdMem(regs.pc++)]();
- uint8 opcode = regs.RdMem(regs.pc++);
+ uint8_t opcode = regs.RdMem(regs.pc++);
exec_op2[opcode]();
regs.clock += page2Cycles[opcode];
}
-
//
// Internal "memcpy" (so we don't have to link with any external libraries!)
//
-static void myMemcpy(void * dst, void * src, uint32 size)
+static void myMemcpy(void * dst, void * src, uint32_t size)
{
- uint8 * d = (uint8 *)dst, * s = (uint8 *)src;
+ uint8_t * d = (uint8_t *)dst, * s = (uint8_t *)src;
- for(uint32 i=0; i<size; i++)
+ for(uint32_t i=0; i<size; i++)
d[i] = s[i];
}
//
// Function to execute 6809 instructions
//
-//#define DEBUG_ILLEGAL
-#ifdef DEBUG_ILLEGAL
-#include "log.h"
-#include "dis6809.h"
-uint8 btPtr = 0;
-uint8 backTrace[256];
-V6809REGS btRegs[256];
-bool tripped = false;
-#endif
-void Execute6809(V6809REGS * context, uint32 cycles)
+void Execute6809(V6809REGS * context, uint32_t cycles)
{
- // If this is not in place, the clockOverrun calculations can cause the V6809 to get
- // stuck in an infinite loop.
+ // If this is not in place, the clockOverrun calculations can cause the
+ // V6809 to get stuck in an infinite loop.
if (cycles == 0) // Nothing to do, so bail!
return;
myMemcpy(®s, context, sizeof(V6809REGS));
- UNPACK_FLAGS; // Explode flags register into individual uint8s
+ // Explode flags register into individual uint8_ts
+ UNPACK_FLAGS;
// Execute here...
- // Since we can't guarantee that we'll execute the number of cycles passed in
- // exactly, we have to keep track of how much we overran the number of cycles
- // the last time we executed. Since we already executed those cycles, this time
- // through we remove them from the cycles passed in in order to come out
- // approximately even. Over the long run, this unevenness in execution times
- // evens out.
- uint64 endCycles = regs.clock + (uint64)(cycles - regs.clockOverrun);
+ // Since we can't guarantee that we'll execute the number of cycles passed
+ // in exactly, we have to keep track of how much we overran the number of
+ // cycles the last time we executed. Since we already executed those
+ // cycles, this time through we remove them from the cycles passed in in
+ // order to come out approximately even. Over the long run, this unevenness
+ // in execution times evens out. :-)
+ uint64_t endCycles = regs.clock + (uint64_t)(cycles - regs.clockOverrun);
while (regs.clock < endCycles)
{
-#ifdef DEBUG_ILLEGAL
-if (!tripped)
-{
- backTrace[btPtr] = regs.RdMem(regs.pc);
- btRegs[btPtr] = regs;
- btPtr = (btPtr + 1) & 0xFF;
-
- if (regs.cpuFlags & V6809_STATE_ILLEGAL_INST)
- {
- WriteLog("V6809: Executed illegal instruction!!!!\n\nBacktrace:\n\n");
- regs.cpuFlags &= ~V6809_STATE_ILLEGAL_INST;
-
- for(uint16 i=btPtr; i<btPtr+256; i++)
- {
- Decode6809(btRegs[i & 0xFF].pc);
-// Note that these values are *before* execution, so stale...
- WriteLog("\n\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
- btRegs[i & 0xFF].a, btRegs[i & 0xFF].b, btRegs[i & 0xFF].cc, btRegs[i & 0xFF].dp, btRegs[i & 0xFF].x, btRegs[i & 0xFF].y, btRegs[i & 0xFF].s, btRegs[i & 0xFF].u, btRegs[i & 0xFF].pc);//*/
- }
-
- tripped = true;
- }
-}
-#endif
-#ifdef __DEBUG__
-if (disasm)
-{
- Decode6809(regs.pc);
-// WriteLog("[e=%02X,f=%02X,h=%02X,i=%02X,n=%02X,z=%02X,v=%02X,c=%02X]", flagE, flagF, flagH, flagI, flagN, flagZ, flagV, flagC);
-}
-#if 0 //we solved this...
-if ((flagE | flagF | flagH | flagI | flagN | flagZ | flagV | flagC) > 1)
- WriteLog("\n\n!!! FLAG OUT OF BOUNDS !!!\n\n");
-#endif
-//static bool disasm = false;
-/*//if (regs.pc == 0x15BA) disasm = true;
-//if (regs.pc == 0xFE76) disasm = true;
-if (regs.x == 0xFED4) disasm = true;
-if (disasm) Decode6809(regs.pc);
-//if (regs.pc == 0x164A) disasm = false;//*/
-
-//temp, for testing...
-/*backTrace[btPtr] = regs.RdMem(regs.pc);
-btPC[btPtr] = regs.pc;
-btPtr = (btPtr + 1) & 0xFF;//*/
-#endif
-// exec_op0[regs.RdMem(regs.pc++)]();
- uint8 opcode = regs.RdMem(regs.pc++);
+ uint8_t opcode = regs.RdMem(regs.pc++);
exec_op0[opcode]();
regs.clock += page0Cycles[opcode];
// Handle any pending interrupts
// Hmm, this is bad and only works when flags are changed OUTSIDE of the running context...
-// uint32 flags = context->cpuFlags;
- uint32 flags = regs.cpuFlags;
+// uint32_t flags = context->cpuFlags;
+ uint32_t flags = regs.cpuFlags;
- if (flags & V6809_ASSERT_LINE_RESET) // *** RESET handler ***
+ // *** RESET handler ***
+ if (flags & V6809_LINE_RESET)
{
-#ifdef __DEBUG__
-if (disasm) WriteLog("\nV6809: RESET line asserted!\n");
-#endif
- flagF = flagI = 1; // Set F, I
- regs.dp = 0; // Reset direct page register
- regs.pc = RdMemW(0xFFFE); // And load PC with the RESET vector
- context->cpuFlags &= ~V6809_ASSERT_LINE_RESET;
- regs.cpuFlags &= ~V6809_ASSERT_LINE_RESET;
+ flagF = flagI = 1; // Set F, I
+ regs.dp = 0; // Reset direct page register
+ regs.pc = RdMemW(0xFFFE); // And load PC with the RESET vector
+ context->cpuFlags &= ~V6809_LINE_RESET;
+ regs.cpuFlags &= ~V6809_LINE_RESET;
}
- else if (flags & V6809_ASSERT_LINE_NMI) // *** NMI handler ***
+ // *** NMI handler ***
+ else if (flags & V6809_LINE_NMI)
{
-#ifdef __DEBUG__
-if (disasm) WriteLog("\nV6809: NMI line asserted!\n");
-#endif
- flagE = 1; // Set Entire flag
- regs.cc = PACK_FLAGS; // Mash flags back into the CC register
+ flagE = 1; // Set Entire flag
+ regs.cc = PACK_FLAGS; // Mash flags back into the CC register
- PUSHS16(regs.pc); // Save all regs...
+ PUSHS16(regs.pc); // Save all regs...
PUSHS16(regs.u);
PUSHS16(regs.y);
PUSHS16(regs.x);
PUSHS(regs.a);
PUSHS(regs.cc);
- flagI = flagF = 1; // Set IRQ/FIRQ suppress flags
- regs.pc = RdMemW(0xFFFC); // And load PC with the NMI vector
+ flagI = flagF = 1; // Set IRQ/FIRQ suppress flags
+ regs.pc = RdMemW(0xFFFC); // And load PC with the NMI vector
regs.clock += 19;
-// context->cpuFlags &= ~V6809_ASSERT_LINE_NMI;// Reset the asserted line (NMI)...
-// regs.cpuFlags &= ~V6809_ASSERT_LINE_NMI; // Reset the asserted line (NMI)...
}
- else if (flags & V6809_ASSERT_LINE_FIRQ) // *** FIRQ handler ***
+ // *** FIRQ handler ***
+ else if (flags & V6809_LINE_FIRQ)
{
-#ifdef __DEBUG__
-if (disasm) WriteLog("\nV6809: FIRQ line asserted!\n");
-#endif
- if (!flagF) // Is the FIRQ masked (F == 1)?
+ if (!flagF) // Is the FIRQ masked (F == 1)?
{
-#ifdef __DEBUG__
-if (disasm) WriteLog(" FIRQ taken...\n");
-#endif
- flagE = 0; // Clear Entire flag
- regs.cc = PACK_FLAGS; // Mash flags back into the CC register
+ flagE = 0; // Clear Entire flag
+ regs.cc = PACK_FLAGS; // Mash flags back into the CC register
PUSHS16(regs.pc);
PUSHS(regs.cc);
- flagI = flagF = 1; // Set IRQ/FIRQ suppress flags
- regs.pc = RdMemW(0xFFF6); // And load PC with the IRQ vector
+ flagI = flagF = 1; // Set IRQ/FIRQ suppress flags
+ regs.pc = RdMemW(0xFFF6); // And load PC with the IRQ vector
regs.clock += 10;
-// context->cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
-// regs.cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
}
}
- else if (flags & V6809_ASSERT_LINE_IRQ) // *** IRQ handler ***
+ // *** IRQ handler ***
+ else if (flags & V6809_LINE_IRQ)
{
-#ifdef __DEBUG__
-if (disasm) WriteLog("\nV6809: IRQ line asserted!\n");
-#endif
- if (!flagI) // Is the IRQ masked (I == 1)?
+ if (!flagI) // Is the IRQ masked (I == 1)?
{
-#ifdef __DEBUG__
-if (disasm) WriteLog(" IRQ taken...\n");
-#endif
- flagE = 1; // Set the Entire flag
- regs.cc = PACK_FLAGS; // Mash flags back into the CC register
+ flagE = 1; // Set the Entire flag
+ regs.cc = PACK_FLAGS; // Mash flags back into the CC register
PUSHS16(regs.pc);
PUSHS16(regs.u);
PUSHS(regs.a);
PUSHS(regs.cc);
- flagI = 1; // Specs say that it doesn't affect FIRQ... or FLAG_F [WAS: Set IRQ/FIRQ suppress flags]
- regs.pc = RdMemW(0xFFF8); // And load PC with the IRQ vector
+ flagI = 1; // Specs say that it doesn't affect FIRQ... or FLAG_F [WAS: Set IRQ/FIRQ suppress flags]
+ regs.pc = RdMemW(0xFFF8); // And load PC with the IRQ vector
regs.clock += 19;
-// Apparently, not done here!
-// context->cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
-// regs.cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
}
}
-#ifdef __DEBUG__
-if (disasm) WriteLog("CC=%s%s%s%s%s%s%s%s A=%02X B=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
- (flagE ? "E" : "-"), (flagF ? "F" : "-"), (flagH ? "H" : "-"), (flagI ? "I" : "-"),
- (flagN ? "N" : "-"), (flagZ ? "Z" : "-"), (flagV ? "V" : "-"), (flagC ? "C" : "-"),
- regs.a, regs.b, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
-/*WriteLog("\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
- regs.a, regs.b, regs.cc, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
-#endif
}
// Keep track of how much we overran so we can adjust on the next run...
- regs.clockOverrun = (uint32)(regs.clock - endCycles);
+ regs.clockOverrun = (uint32_t)(regs.clock - endCycles);
- regs.cc = PACK_FLAGS; // Mash flags back into the CC register
+ regs.cc = PACK_FLAGS; // Mash flags back into the CC register
myMemcpy(context, ®s, sizeof(V6809REGS));
}
//
// Get the clock of the currently executing CPU
//
-uint64 GetCurrentV6809Clock(void)
+uint64_t GetCurrentV6809Clock(void)
{
return regs.clock;
}
//
// Get the PC of the currently executing CPU
//
-uint16 GetCurrentV6809PC(void)
+uint16_t GetCurrentV6809PC(void)
{
return regs.pc;
}
// Set a line of the currently executing CPU
-void SetLineOfCurrentV6809(uint32 line)
+void SetLineOfCurrentV6809(uint32_t line)
{
regs.cpuFlags |= line;
}
// Clear a line of the currently executing CPU
-void ClearLineOfCurrentV6809(uint32 line)
+void ClearLineOfCurrentV6809(uint32_t line)
{
-#ifdef __DEBUG__
-if (disasm)
- WriteLog("V6809: Clearing line %s...", (line == V6809_ASSERT_LINE_IRQ ? "IRQ" : "OTHER"));
-#endif
regs.cpuFlags &= ~line;
}
-
-#if 0
-FE54: 27 6A BEQ $FEC0 CC=EF-I-Z-- A=39 B=01 DP=00 X=FEE2 Y=F51
-E S=BFFF U=0000 PC=FEC0
-FEC0: 6E A4 JMP ,Y CC=EF-I-Z-- A=39 B=01 DP=00 X=FEE2 Y=F51E S=BFFF
- U=0000 PC=F51E
-F51E: 86 34 LDA #$34 CC=EF-I---- A=34 B=01 DP=00 X=FEE2 Y=F51E S=BFFF
- U=0000 PC=F520
-F520: B7 C8 0D STA $C80D CC=EF-I---- A=34 B=01 DP=00 X=FEE2 Y=F51E S=BFFF U=0000 PC=F523
-F523: B7 C8 0F STA $C80F CC=EF-I---- A=34 B=01 DP=00 X=FEE2 Y=F51E S=BFFF U=0000 PC=F526
-F526: 7F C8 0E CLR $C80EV6809: Clearing line IRQ... CC=EF-I-Z-- A=34 B=01 DP=00 X=FEE2 Y=F51E S=BFFF U=0000 PC=F529
-F529: 86 9C LDA #$9C CC=EF-IN--- A=9C B=01 DP=00 X=FEE2 Y=F51E S=BFFF U=0000 PC=F52B
-F52B: 1F 8B TFR A,DP CC=EF-IN--- A=9C B=01 DP=9C X=FEE2 Y=F51E S=BFFF U=0000 PC=F52D
-F52D: 10 CE BF FF LDS #$BFFF CC=EF-IN--- A=9C B=01 DP=9C X=FEE2 Y=F51E S=BFFF U=0000 PC=F531
-F531: BD 13 BD JSR $13BD CC=EF-IN--- A=9C B=01 DP=9C X=FEE2 Y=F51E S=BFFD U=0000 PC=13BD
-13BD: 34 76 PSHS A B X Y U CC=EF-IN--- A=9C B=01 DP=9C X=FEE2 Y=F51E S=BFF5 U=0000 PC=13BF
-13BF: CE 9C 00 LDU #$9C00 CC=EF-IN--- A=9C B=01 DP=9C X=FEE2 Y=F51E S=BFF5 U=9C00 PC=13C2
-13C2: 8E 00 00 LDX #$0000 CC=EF-I-Z-- A=9C B=01 DP=9C X=0000 Y=F51E S=BFF5 U=9C00 PC=13C5
-13C5: 1F 12 TFR X,Y CC=EF-I-Z-- A=9C B=01 DP=9C X=0000 Y=0000 S=BFF5 U=9C00 PC=13C7
-13C7: 1F 10 TFR X,D CC=EF-I-Z-- A=00 B=00 DP=9C X=0000 Y=0000 S=BFF5 U=9C00 PC=13C9
-13C9: 36 36 PSHU A B X Y CC=EF-I-Z-- A=00 B=00 DP=9C X=0000 Y=0000 S=BFEF U=9C00 PC=13CB
-13CB: 36 36 PSHU A B X Y CC=EF-I-Z-- A=00 B=00 DP=9C X=0000 Y=0000 S=BFE9 U=9C00 PC=13CD
-13CD: 36 36 PSHU A B X Y CC=EF-I-Z-- A=00 B=00 DP=9C X=0000 Y=0000 S=BFE3 U=9C00 PC=13CF
-13CF: 36 36 PSHU A B X Y CC=EF-I-Z-- A=00 B=00 DP=9C X=0000 Y=0000 S=BFDD U=9C00 PC=13D1
-13D1: 36 36 PSHU A B X Y CC=EF-I-Z-- A=00 B=00 DP=9C X=0000 Y=0000 S=BFD7 U=9C00 PC=13D3
-13D3: 36 10 PSHU X CC=EF-I-Z-- A=00 B=00 DP=9C X=0000 Y=0000 S=BFD5 U=9C00 PC=13D5
-13D5: 11 83 00 00 CMPU #$0000 CC=EF-IN--- A=00 B=00 DP=9C X=0000 Y=000
-#endif
projects / stargem2 / blobdiff