// Private global variables
static V6809REGS regs;
-static WORD addr; // Temporary variables common to all funcs...
-static BYTE tmp;
+static uint16 addr; // Temporary variables common to all funcs...
+static uint8 tmp;
// Private function prototypes
-static int SignedB(BYTE); // Return signed byte from unsigned
-static int SignedW(WORD); // Return signed word from unsigned
-static WORD FetchW(void);
-static WORD RdMemW(WORD addr);
-static void WrMemW(WORD addr, WORD w);
-static WORD ReadEXG(BYTE); // Read TFR/EXG post byte
-static void WriteEXG(BYTE, WORD); // Set TFR/EXG data
-static WORD DecodeReg(BYTE); // Decode register data
-static WORD DecodeIDX(BYTE); // Decode IDX data
+static int SignedB(uint8); // Return signed byte from unsigned
+static int SignedW(uint16); // Return signed word from unsigned
+static uint16 FetchW(void);
+static uint16 RdMemW(uint16 addr);
+static void WrMemW(uint16 addr, uint16 w);
+static uint16 ReadEXG(uint8); // Read TFR/EXG post byte
+static void WriteEXG(uint8, uint16); // Set TFR/EXG data
+static uint16 DecodeReg(uint8); // Decode register data
+static uint16 DecodeIDX(uint8); // Decode IDX data
// This is here because of the stupid forward declaration rule that C++ forces (the C++ compiler
// isn't smart enough to know that the identifiers in the arrays are declared later, it doesn't
// Fetch a word out of 6809 memory (little endian format)
// This is a leftover from when fetches were separated from garden variety reads...
//
-static WORD FetchW()
+static uint16 FetchW()
{
- WORD w = RdMemW(regs.pc);
+ uint16 w = RdMemW(regs.pc);
regs.pc += 2;
return w;
}
//
// Fetch word function
//
-/*WORD FetchW(void)
+/*uint16 FetchW(void)
{
- return (WORD)(regs.RdMem(regs.pc++) << 8) | regs.RdMem(regs.pc++);
+ return (uint16)(regs.RdMem(regs.pc++) << 8) | regs.RdMem(regs.pc++);
}*/
//
// Read word from memory function
//
-WORD RdMemW(WORD addr)
+uint16 RdMemW(uint16 addr)
{
- return (WORD)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
+ return (uint16)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
}
//
// Write word to memory function
//
-void WrMemW(WORD addr, WORD w)
+void WrMemW(uint16 addr, uint16 w)
{
regs.WrMem(addr + 0, w >> 8);
regs.WrMem(addr + 1, w & 0xFF);
//
// return signed byte from unsigned
//
-int SignedB(BYTE b)
+int SignedB(uint8 b)
{
return (b & 0x80 ? b - 256 : b);
}
//
// return signed word from unsigned
//
-int SignedW(WORD w)
+int SignedW(uint16 w)
{
return (w & 0x8000 ? w - 65536 : w);
}
//
// Function to read TFR/EXG post byte
//
-WORD ReadEXG(BYTE code)
+uint16 ReadEXG(uint8 code)
{
- WORD retval;
+ uint16 retval;
switch (code)
{
//
// Function to set TFR/EXG data
//
-void WriteEXG(BYTE code, WORD data)
+void WriteEXG(uint8 code, uint16 data)
{
switch (code)
{
//
// Function to decode register data
//
-WORD DecodeReg(BYTE reg)
+uint16 DecodeReg(uint8 reg)
{
- WORD retval;
+ uint16 retval;
switch (reg)
{
//
// Function to decode IDX data
//
-WORD DecodeIDX(BYTE code)
+uint16 DecodeIDX(uint8 code)
{
- WORD addr, woff;
- BYTE reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
+ uint16 addr, woff;
+ uint8 reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
if (!(code & 0x80)) // Hi bit unset? Then decode 4 bit offset
addr = DecodeReg(reg) + (idxind ? lo_nyb - 16 : lo_nyb);
}
static void Op06(void) // ROR DP
{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++); BYTE tmp2 = regs.RdMem(addr);
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr);
tmp = (tmp2>>1) + (regs.cc&0x01)*128;
regs.WrMem(addr, tmp);
(tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
}
static void Op09(void) // ROL DP
{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++); BYTE tmp2 = regs.RdMem(addr);
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr);
tmp = (tmp2<<1) + (regs.cc&0x01);
regs.WrMem(addr, tmp);
(tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
regs.cc &= 0xFD; // CLV
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 6;
}
static void Op0E(void) // JMP DP
}
static void Op13(void) // SYNC
-{
+{
regs.clock += 2;
}
static void Op16(void) // LBRA
regs.a += 0x60; regs.cc |= 0x01; // Then adjust & set carry
}
regs.cc &= 0xF1; // CL NZV
- if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
regs.clock += 2;
}
{
}
static void Op40(void) // NEGA
-{
+{
regs.a = 256 - regs.a;
(regs.a > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
(regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 2;
}
-static void Op49(void) // ROLA
+static void Op49(void) // ROLA
{
tmp = regs.a; regs.a = (tmp<<1) + (regs.cc&0x01);
(tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
regs.clock += 2;
}
static void Op50(void) // NEGB
- {
+ {
regs.b = 256 - regs.b;
// ((regs.b^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
(regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void Op5C(void) // INCB
{
regs.b++;
- (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 2;
regs.clock += 2;
}
static void Op60(void) // NEG IDX
- {
+ {
addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr); BYTE res = 256 - tmp;
+ tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
regs.WrMem(addr, res);
// ((res^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
(res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void Op66(void) // ROR IDX
{
addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr); BYTE tmp2 = tmp;
+ tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
tmp = (tmp >> 1) + (regs.cc&0x01)*128;
regs.WrMem(addr, tmp);
(tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
}
static void Op69(void) // ROL IDX
{
- BYTE tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ uint8 tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
tmp = (tmp2<<1) + (regs.cc&0x01);
regs.WrMem(addr, tmp);
(tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
}
static void Op6A(void) // DEC IDX
{
- BYTE tmp; WORD addr;
+ uint8 tmp; uint16 addr;
addr = DecodeIDX(regs.RdMem(regs.pc++));
tmp = regs.RdMem(addr) - 1;
regs.WrMem(addr, tmp);
regs.clock += 6;
}
static void Op6C(void) // INC IDX
- {
+ {
addr = DecodeIDX(regs.RdMem(regs.pc++));
tmp = regs.RdMem(addr) + 1;
regs.WrMem(addr, tmp);
static void Op6D(void) // TST IDX
{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 6;
}
static void Op6E(void) // JMP IDX
regs.clock += 6;
}
static void Op70(void) // NEG ABS
- {
+ {
addr = FetchW();
- tmp = regs.RdMem(addr); BYTE res = 256 - tmp;
+ tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
regs.WrMem(addr, res);
(res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
(res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
}
static void Op76(void) // ROR ABS
{
- BYTE tmp; WORD addr;
+ uint8 tmp; uint16 addr;
addr = FetchW();
- tmp = regs.RdMem(addr); BYTE tmp2 = tmp;
+ tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
tmp = (tmp >> 1) + (regs.cc&0x01)*128;
regs.WrMem(addr, tmp);
(tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
}
static void Op77(void) // ASR ABS
{
- BYTE tmp; WORD addr;
+ uint8 tmp; uint16 addr;
addr = FetchW();
tmp = regs.RdMem(addr);
(tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
}
static void Op78(void) // LSL ABS
{
- BYTE tmp; WORD addr;
+ uint8 tmp; uint16 addr;
addr = FetchW();
tmp = regs.RdMem(addr);
(tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
}
static void Op79(void) // ROL ABS
{
- BYTE tmp2 = regs.RdMem(FetchW());
+ uint8 tmp2 = regs.RdMem(FetchW());
tmp = (tmp2<<1) + (regs.cc&0x01);
regs.WrMem(addr, tmp);
(tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
}
static void Op7A(void) // DEC ABS
{
- BYTE tmp; WORD addr;
+ uint8 tmp; uint16 addr;
addr = FetchW();
tmp = regs.RdMem(addr) - 1;
regs.WrMem(addr, tmp);
regs.clock += 7;
}
static void Op7C(void) // INC ABS
- {
- BYTE tmp; WORD addr;
+ {
+ uint8 tmp; uint16 addr;
addr = FetchW();
tmp = regs.RdMem(addr) + 1;
regs.WrMem(addr, tmp);
static void Op7D(void) // TST ABS
{
- BYTE tmp = regs.RdMem(FetchW());
+ uint8 tmp = regs.RdMem(FetchW());
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 7;
}
regs.clock += 7;
}
static void Op80(void) // SUBA #
-{
- BYTE tmp = regs.RdMem(regs.pc++); BYTE as = regs.a;
+{
+ uint8 tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
regs.a -= tmp;
(as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void Op81(void) // CMPA #
{
tmp = regs.RdMem(regs.pc++);
- BYTE db = regs.a - tmp;
+ uint8 db = regs.a - tmp;
(regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
}
static void Op82(void) // SBCA #
{
- tmp = regs.RdMem(regs.pc++); BYTE as = regs.a;
+ tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
}
static void Op83(void) // SUBD #
{
- addr = FetchW(); WORD dr = (regs.a<<8)|regs.b, ds = dr;
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
dr -= addr;
(ds < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void Op89(void) // ADCA #
{
tmp = regs.RdMem(regs.pc++);
- addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
regs.clock += 2;
}
static void Op8B(void) // ADDA #
-{
+{
tmp = regs.RdMem(regs.pc++); addr = regs.a + tmp;
(addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
static void Op8C(void) // CMPX #
{
addr = FetchW();
- WORD dw = regs.x - addr;
+ uint16 dw = regs.x - addr;
(regs.x < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((regs.x^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
regs.clock += 3;
}
static void Op90(void) // SUBA DP
- {
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); BYTE as = regs.a;
+ {
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
regs.a -= tmp;
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void Op91(void) // CMPA DP
{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- BYTE db = regs.a - tmp;
+ uint8 db = regs.a - tmp;
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op92(void) // SBCA DP
{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); BYTE as = regs.a;
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
}
static void Op93(void) // SUBD DP
{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++); WORD dr = (regs.a<<8)|regs.b, ds = dr;
- WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
dr -= adr2;
(ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void Op99(void) // ADCA DP
{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
regs.clock += 4;
}
static void Op9B(void) // ADDA DP
-{
+{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (WORD)regs.a + (WORD)tmp;
+ addr = (uint16)regs.a + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
static void Op9C(void) // CMPX DP
{
addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- WORD dw = regs.x - adr2;
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.x - adr2;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.x < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
regs.clock += 5;
}
static void OpA0(void) // SUBA IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); BYTE as = regs.a;
+ {
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
regs.a -= tmp;
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void OpA1(void) // CMPA IDX
{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- BYTE db = regs.a - tmp;
+ uint8 db = regs.a - tmp;
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void OpA2(void) // SBCA IDX
{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); BYTE as = regs.a;
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
}
static void OpA3(void) // SUBD IDX
{
- addr = DecodeIDX(regs.RdMem(regs.pc++)); WORD dr = (regs.a<<8)|regs.b, ds = dr;
- WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ addr = DecodeIDX(regs.RdMem(regs.pc++)); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
dr -= adr2;
(ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void OpA9(void) // ADCA IDX
{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 4;
}
static void OpAB(void) // ADDA IDX
-{
+{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (WORD)regs.a + (WORD)tmp;
+ addr = (uint16)regs.a + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.a = addr & 0xFF; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
static void OpAC(void) // CMPX IDX
{
addr = DecodeIDX(regs.RdMem(regs.pc++));
- WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- WORD dw = regs.x - addr2;
+ uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.x - addr2;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
regs.clock += 5;
}
static void OpB0(void) // SUBA ABS
- {
- tmp = regs.RdMem(FetchW()); BYTE as = regs.a;
+ {
+ tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
regs.a -= tmp;
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void OpB1(void) // CMPA ABS
{
tmp = regs.RdMem(FetchW());
- BYTE db = regs.a - tmp;
+ uint8 db = regs.a - tmp;
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void OpB2(void) // SBCA ABS
{
- tmp = regs.RdMem(FetchW()); BYTE as = regs.a;
+ tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
regs.a = regs.a - tmp - (regs.cc&0x01);
(as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
}
static void OpB3(void) // SUBD ABS
{
- addr = FetchW(); WORD dr = (regs.a<<8)|regs.b, ds = dr;
- WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
dr -= adr2;
(ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
static void OpB9(void) // ADCA ABS
{
tmp = regs.RdMem(FetchW());
- addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.a = addr; // Set accumulator
(regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpBB(void) // ADDA ABS
-{
+{
tmp = regs.RdMem(FetchW());
- addr = (WORD)regs.a + (WORD)tmp;
+ addr = (uint16)regs.a + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
}
static void OpBC(void) // CMPX ABS
{
- addr = FetchW(); WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- WORD dw = regs.x - addr2;
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.x - addr2;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
{
addr = FetchW();
regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // Go to absolute address (Not indir)
+ regs.pc = addr; // Go to absolute address (Not indir)
regs.clock += 8;
}
}
static void OpC0(void) // SUBB #
- {
- tmp = regs.RdMem(regs.pc++); BYTE bs = regs.b;
+ {
+ tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void OpC1(void) // CMPB #
{
tmp = regs.RdMem(regs.pc++);
- BYTE db = regs.b - tmp;
+ uint8 db = regs.b - tmp;
(regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
}
static void OpC2(void) // SBCB #
{
- tmp = regs.RdMem(regs.pc++); BYTE bs = regs.b;
+ tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void OpC9(void) // ADCB #
{
tmp = regs.RdMem(regs.pc++);
- addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 2;
}
static void OpCB(void) // ADDB #
-{
+{
tmp = regs.RdMem(regs.pc++); addr = regs.b + tmp;
(addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 3;
}
static void OpD0(void) // SUBB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); BYTE bs = regs.b;
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void OpD1(void) // CMPB DP
{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- BYTE db = regs.b - tmp;
+ uint8 db = regs.b - tmp;
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void OpD2(void) // SBCB DP
{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); BYTE bs = regs.b;
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void OpD3(void) // ADDD DP
{
addr = (regs.dp<<8)|regs.RdMem(regs.pc++); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
- WORD adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+ uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
dr += adr2;
(dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
dr &= 0xFFFF;
static void OpD9(void) // ADCB DP
{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 4;
}
static void OpDB(void) // ADDB DP
-{
+{
tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (WORD)regs.b + (WORD)tmp;
+ addr = (uint16)regs.b + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpE0(void) // SUBB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); BYTE bs = regs.b;
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void OpE1(void) // CMPB IDX
{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- BYTE db = regs.b - tmp;
+ uint8 db = regs.b - tmp;
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void OpE2(void) // SBCB IDX
{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); BYTE bs = regs.b;
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
static void OpE3(void) // ADDD IDX
{
addr = DecodeIDX(regs.RdMem(regs.pc++)); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
- WORD adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+ uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
dr += adr2;
(dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
dr &= 0xFFFF;
static void OpE9(void) // ADCB IDX
{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 4;
}
static void OpEB(void) // ADDB IDX
-{
+{
tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (WORD)regs.b + (WORD)tmp;
+ addr = (uint16)regs.b + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
regs.b = addr; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
regs.clock += 5;
}
static void OpF0(void) // SUBB ABS
- {
- tmp = regs.RdMem(FetchW()); BYTE bs = regs.b;
+ {
+ tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
regs.b -= tmp;
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void OpF1(void) // CMPB ABS
{
tmp = regs.RdMem(FetchW());
- BYTE db = regs.b - tmp;
+ uint8 db = regs.b - tmp;
(db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void OpF2(void) // SBCB ABS
{
- tmp = regs.RdMem(FetchW()); BYTE bs = regs.b;
+ tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
regs.b = regs.b - tmp - (regs.cc&0x01);
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
static void OpF3(void) // ADDD ABS
{
addr = FetchW(); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
- WORD adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+ uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
dr += adr2;
(dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
dr &= 0xFFFF;
static void OpF9(void) // ADCB ABS
{
tmp = regs.RdMem(FetchW());
- addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
regs.clock += 5;
- }
+ }
static void OpFB(void) // ADDB ABS
-{
+{
tmp = regs.RdMem(FetchW());
- addr = (WORD)regs.b + (WORD)tmp;
+ addr = (uint16)regs.b + (uint16)tmp;
(addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
regs.b = addr & 0xFF; // Set accumulator
(regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
(regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
}
static void Op1083(void) // CMPD #
{
- addr = FetchW(); WORD dr = (regs.a<<8)|regs.b;
- WORD dw = dr - addr;
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b;
+ uint16 dw = dr - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((dr^addr^dw^((WORD)regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ ((dr^addr^dw^((uint16)regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
regs.clock += 5;
}
static void Op108C(void) // CMPY #
{
addr = FetchW();
- WORD dw = regs.y - addr;
+ uint16 dw = regs.y - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op1093(void) // CMPD DP
{
- WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++), dr = (regs.a<<8)|regs.b;
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++), dr = (regs.a<<8)|regs.b;
addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- WORD dw = dr - addr;
+ uint16 dw = dr - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op109C(void) // CMPY DP
{
- WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- WORD dw = regs.y - addr;
+ uint16 dw = regs.y - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op10A3(void) // CMPD IDX
{
- WORD adr2 = DecodeIDX(regs.RdMem(regs.pc++)), dr = (regs.a<<8)|regs.b;
+ uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++)), dr = (regs.a<<8)|regs.b;
addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- WORD dw = dr - addr;
+ uint16 dw = dr - addr;
regs.cc &= 0xF0; // CLC CLV CLZ CLN
if (dr < addr) regs.cc |= 0x01; // Set Carry flag
if ((dr^addr^dw^(regs.cc<<15))&0x8000) regs.cc |= 0x02; // Set oVerflow
}
static void Op10AC(void) // CMPY IDX
{
- WORD adr2 = DecodeIDX(regs.RdMem(regs.pc++));
+ uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++));
addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- WORD dw = regs.y - addr;
+ uint16 dw = regs.y - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op10B3(void) // CMPD ABS
{
- addr = FetchW(); WORD dr = (regs.a<<8)|regs.b;
- WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- WORD dw = dr - addr2;
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b;
+ uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = dr - addr2;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(dr < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op10BC(void) // CMPY ABS
{
- addr = FetchW(); WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- WORD dw = regs.y - addr2;
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.y - addr2;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.y < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
regs.cc &= 0xFD; // CLV
(regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
+ regs.clock += 6;
}
static void Op10DF(void) // STS DP
{
static void Op1183(void) // CMPU #
{
addr = FetchW();
- WORD dw = regs.u - addr;
+ uint16 dw = regs.u - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
static void Op118C(void) // CMPS #
{
addr = FetchW();
- WORD dw = regs.s - addr;
+ uint16 dw = regs.s - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op1193(void) // CMPU DP
{
- WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- WORD dw = regs.u - addr;
+ uint16 dw = regs.u - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op119C(void) // CMPS DP
{
- WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- WORD dw = regs.s - addr;
+ uint16 dw = regs.s - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op11A3(void) // CMPU IDX
{
- WORD addr2 = DecodeIDX(regs.RdMem(regs.pc++));
+ uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
- WORD dw = regs.u - addr;
+ uint16 dw = regs.u - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op11AC(void) // CMPS IDX
{
- WORD addr2 = DecodeIDX(regs.RdMem(regs.pc++));
+ uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
- WORD dw = regs.s - addr;
+ uint16 dw = regs.s - addr;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
static void Op11B3(void) // CMPU ABS
{
- addr = FetchW(); WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- WORD dw = regs.u - addr2;
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.u - addr2;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.u < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
static void Op11BC(void) // CMPS ABS
{
- addr = FetchW(); WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- WORD dw = regs.s - addr2;
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.s - addr2;
(dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
(regs.s < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
}
//temp, for testing...
-/*static BYTE backTrace[256];
-static WORD btPC[256];
+/*static uint8 backTrace[256];
+static uint16 btPC[256];
static int btPtr = 0;//*/
static void Op__(void) // Illegal opcode
{
//
// Internal "memcpy" (so we don't have to link with any external libraries!)
//
-static void myMemcpy(void * dst, void * src, DWORD size)
+static void myMemcpy(void * dst, void * src, uint32 size)
{
- BYTE * d = (BYTE *)dst, * s = (BYTE *)src;
+ uint8 * d = (uint8 *)dst, * s = (uint8 *)src;
- for(DWORD i=0; i<size; i++)
+ for(uint32 i=0; i<size; i++)
d[i] = s[i];
}
//
// Function to execute 6809 instructions
//
-void Execute6809(V6809REGS * context, DWORD cycles)
+void Execute6809(V6809REGS * context, uint32 cycles)
{
myMemcpy(®s, context, sizeof(V6809REGS));
// Execute here...
-DWORD clockSave = regs.clock;
+uint32 clockSave = regs.clock;
regs.clock = 0;
while (regs.clock < cycles)
{
// Handle any pending interrupts
- DWORD flags = context->cpuFlags;
+ uint32 flags = context->cpuFlags;
if (flags & V6809_ASSERT_LINE_RESET) // *** RESET handler ***
{