//
-// Virtual 6809 v1.3
+// Virtual 6809 v1.4
//
// by James L. Hammons
-// (c) 1997, 2006 Underground Software
+// (c) 1997, 2009 Underground Software
//
// JLH = James L. Hammons <jlhamm@acm.org>
//
// JLH 06/15/2006 Added changelog ;-)
// JLH 06/15/2006 Scrubbed all BYTE, WORD & DWORD references from the code
// JLH 11/11/2006 Removed all SignedX() references
-//
-
-// Mebbe someday I'll get around to fixing the core to be more like V65C02...
-// We have a start... ;-)
+// JLH 09/29/2009 Converted V6809 to macro implementation!
//
#define __DEBUG__
#define SET_N16(r) (flagN = ((r) & 0x8000) >> 15)
#define SET_V(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x80) >> 7)
#define SET_V16(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x8000) >> 15)
+#define SET_H(a,b,r) (flagH = (((a) ^ (b) ^ (r)) & 0x10) >> 4)
//Not sure that this code is computing the carry correctly... Investigate! [Seems to be]
-#define SET_C_ADD(a,b) (flagC = ((uint8)(b) > (uint8)(~(a)) ? 1 : 0))
-//#define SET_C_SUB(a,b) (regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
-#define SET_C_CMP(a,b) (flagC = ((uint8)(b) >= (uint8)(a) ? 1 : 0))
+//#define SET_C_ADD(a,b) (flagC = ((uint8_t)(b) > (uint8_t)(~(a)) ? 1 : 0))
+//#define SET_C_SUB(a,b) (regs.cc = ((uint8_t)(b) >= (uint8_t)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+//#define SET_C_CMP(a,b) (flagC = ((uint8_t)(b) >= (uint8_t)(a) ? 1 : 0))
#define SET_ZN(r) SET_N(r); SET_Z(r)
#define SET_ZN16(r) SET_N16(r); SET_Z(r)
-#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
+//#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
//#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b)
-#define SET_ZNC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b)
+//#define SET_ZNC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b)
-//Small problem with the EA_ macros: ABS macros don't increment the PC!!! !!! FIX !!!
-//Hmm, why not do like we did for READ_ABS*???
-//Because the EA_* macros are usually used as an argument to a function call, that's why.
-//Now, we CAN fix it using FetchMemW()!!! [DONE]
#define EA_IMM regs.pc++
#define EA_DP (regs.dp << 8) | regs.RdMem(regs.pc++)
#define EA_IDX DecodeIDX(regs.RdMem(regs.pc++))
#define READ_ABS regs.RdMem(EA_ABS)
#define READ_ABS16 RdMemW(EA_ABS)
-#define READ_IMM_WB(v) uint16 addr = EA_IMM; v = regs.RdMem(addr)
-#define READ_DP_WB(v) uint16 addr = EA_DP; v = regs.RdMem(addr)
-#define READ_IDX_WB(v) uint16 addr = EA_IDX; v = regs.RdMem(addr)
-#define READ_ABS_WB(v) uint16 addr = EA_ABS; v = regs.RdMem(addr)
+#define READ_IMM_WB(v) uint16_t addr = EA_IMM; v = regs.RdMem(addr)
+#define READ_DP_WB(v) uint16_t addr = EA_DP; v = regs.RdMem(addr)
+#define READ_IDX_WB(v) uint16_t addr = EA_IDX; v = regs.RdMem(addr)
+#define READ_ABS_WB(v) uint16_t addr = EA_ABS; v = regs.RdMem(addr)
#define WRITE_BACK(d) regs.WrMem(addr, (d))
// Private global variables
static V6809REGS regs;
-static uint8 flagE, flagF, flagH, flagI, flagN, flagZ, flagV, flagC;
+static uint8_t flagE, flagF, flagH, flagI, flagN, flagZ, flagV, flagC;
-uint8 page0Cycles[256] = {
+uint8_t page0Cycles[256] = {
6, 1, 1, 6, 6, 1, 6, 6, 6, 6, 6, 1, 6, 6, 3, 6, // $0x
1, 1, 2, 2, 1, 1, 5, 9, 1, 2, 3, 1, 3, 2, 8, 7, // $1x
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // $2x
5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6 // $Fx
};
-uint8 page1Cycles[256] = {
+uint8_t page1Cycles[256] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $0x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $1x
1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, // $2x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 7, 7 // $Fx
};
-uint8 page2Cycles[256] = {
+uint8_t page2Cycles[256] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $0x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $1x
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $2x
// Private function prototypes
-static uint16 RdMemW(uint16 addr);
-static uint16 FetchMemW(uint16 addr);
-static void WrMemW(uint16 addr, uint16 w);
-static uint16 ReadEXG(uint8); // Read TFR/EXG post byte
-static void WriteEXG(uint8, uint16); // Set TFR/EXG data
-static uint16 DecodeReg(uint8); // Decode register data
-static uint16 DecodeIDX(uint8); // Decode IDX data
+static uint16_t RdMemW(uint16_t addr);
+static uint16_t FetchMemW(uint16_t addr);
+static void WrMemW(uint16_t addr, uint16_t w);
+static uint16_t ReadEXG(uint8_t); // Read TFR/EXG post byte
+static void WriteEXG(uint8_t, uint16_t); // Set TFR/EXG data
+static uint16_t DecodeReg(uint8_t); // Decode register data
+static uint16_t DecodeIDX(uint8_t); // Decode IDX data
//
// Read word from memory function
//
-static inline uint16 RdMemW(uint16 addr)
+static inline uint16_t RdMemW(uint16_t addr)
{
- return (uint16)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
+ return (uint16_t)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
}
//
// Fetch a word from memory function. Increments PC
//
-static inline uint16 FetchMemW(uint16 addr)
+static inline uint16_t FetchMemW(uint16_t addr)
{
regs.pc += 2;
- return (uint16)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
+ return (uint16_t)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
}
//
// Write word to memory function
//
-static inline void WrMemW(uint16 addr, uint16 w)
+static inline void WrMemW(uint16_t addr, uint16_t w)
{
regs.WrMem(addr + 0, w >> 8);
regs.WrMem(addr + 1, w & 0xFF);
//
// Function to read TFR/EXG post byte
//
-uint16 ReadEXG(uint8 code)
+uint16_t ReadEXG(uint8_t code)
{
- uint16 retval;
+ uint16_t retval;
switch (code)
{
retval = regs.b;
break;
case 10:
+ PACK_FLAGS;
retval = regs.cc;
break;
case 11:
//
// Function to set TFR/EXG data
//
-void WriteEXG(uint8 code, uint16 data)
+void WriteEXG(uint8_t code, uint16_t data)
{
switch (code)
{
case 9:
regs.b = data & 0xFF; break;
case 10:
- regs.cc = data & 0xFF; break;
+ regs.cc = data & 0xFF; UNPACK_FLAGS; break;
case 11:
regs.dp = data & 0xFF; break;
}
//
// Function to decode register data
//
-uint16 DecodeReg(uint8 reg)
+uint16_t DecodeReg(uint8_t reg)
{
- uint16 retval;
+ uint16_t retval;
switch (reg)
{
//
// Function to decode IDX data
//
-uint16 DecodeIDX(uint8 code)
+uint16_t DecodeIDX(uint8_t code)
{
- uint16 addr, woff;
- uint8 reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
+ uint16_t addr, woff;
+ uint8_t reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
if (!(code & 0x80)) // Hi bit unset? Then decode 4 bit offset
addr = DecodeReg(reg) + (idxind ? lo_nyb - 16 : lo_nyb);
addr = RdMemW(woff);
break;
case 5:
- woff = DecodeReg(reg) + (int16)(int8)regs.b;
+ woff = DecodeReg(reg) + (int16_t)(int8_t)regs.b;
addr = RdMemW(woff);
break;
case 6:
- woff = DecodeReg(reg) + (int16)(int8)regs.a;
+ woff = DecodeReg(reg) + (int16_t)(int8_t)regs.a;
addr = RdMemW(woff);
break;
case 8:
- woff = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++);
+ woff = DecodeReg(reg) + (int16_t)(int8_t)regs.RdMem(regs.pc++);
addr = RdMemW(woff);
break;
case 9:
addr = RdMemW(woff);
break;
case 12:
- woff = regs.pc + (int16)(int8)regs.RdMem(regs.pc++);
+ woff = regs.pc + (int16_t)(int8_t)regs.RdMem(regs.pc++);
addr = RdMemW(woff);
break;
case 13:
}
addr = DecodeReg(reg); break; }
case 4: { addr = DecodeReg(reg); break; }
- case 5: { addr = DecodeReg(reg) + (int16)(int8)regs.b; break; }
- case 6: { addr = DecodeReg(reg) + (int16)(int8)regs.a; break; }
- case 8: { addr = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++); break; }
+ case 5: { addr = DecodeReg(reg) + (int16_t)(int8_t)regs.b; break; }
+ case 6: { addr = DecodeReg(reg) + (int16_t)(int8_t)regs.a; break; }
+ case 8: { addr = DecodeReg(reg) + (int16_t)(int8_t)regs.RdMem(regs.pc++); break; }
case 9: { addr = DecodeReg(reg) + FetchMemW(regs.pc); break; }
case 11: { addr = DecodeReg(reg) + ((regs.a << 8) | regs.b); break; }
- case 12: { addr = regs.pc + (int16)(int8)regs.RdMem(regs.pc++); break; }
+ case 12: { addr = regs.pc + (int16_t)(int8_t)regs.RdMem(regs.pc++); break; }
case 13: { addr = regs.pc + FetchMemW(regs.pc); break; }
}
}
return addr;
}
-#if 1
-
//
// 6809 OPCODE IMPLEMENTATION
//
// ADC opcodes
#define OP_ADC_HANDLER(m, acc) \
- uint16 sum = (uint16)acc + (m) + (uint16)flagC; \
+ uint16_t sum = (uint16_t)acc + (m) + (uint16_t)flagC; \
flagC = (sum >> 8) & 0x01; \
- flagH = (sum >> 4) & 0x01; \
+ SET_H(m, acc, sum); \
SET_V(m, acc, sum); \
acc = sum & 0xFF; \
SET_ZN(acc)
static void Op89(void) // ADCA #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADC_HANDLER(m, regs.a);
}
static void Op99(void) // ADCA DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADC_HANDLER(m, regs.a);
}
static void OpA9(void) // ADCA IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADC_HANDLER(m, regs.a);
}
static void OpB9(void) // ADCA ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADC_HANDLER(m, regs.a);
}
static void OpC9(void) // ADCB #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADC_HANDLER(m, regs.b);
}
static void OpD9(void) // ADCB DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADC_HANDLER(m, regs.b);
}
static void OpE9(void) // ADCB IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADC_HANDLER(m, regs.b);
}
static void OpF9(void) // ADCB ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADC_HANDLER(m, regs.b);
}
// ADD opcodes
#define OP_ADD_HANDLER(m, acc) \
- uint16 sum = (uint16)(acc) + (m); \
+ uint16_t sum = (uint16_t)(acc) + (m); \
flagC = (sum >> 8) & 0x01; \
- flagH = (sum >> 4) & 0x01; \
+ SET_H(m, acc, sum); \
SET_V(m, acc, sum); \
(acc) = sum & 0xFF; \
SET_ZN(acc)
#define OP_ADD_HANDLER16(m, hireg, loreg) \
- uint32 acc = (uint32)((hireg << 8) | loreg); \
- uint32 sum = acc + (m); \
+ uint32_t acc = (uint32_t)((hireg << 8) | loreg); \
+ uint32_t sum = acc + (m); \
flagC = (sum >> 16) & 0x01; \
SET_V16(m, acc, sum); \
acc = sum & 0xFFFF; \
static void Op3A(void) // ABX
{
- regs.x += (uint16)regs.b;
+ regs.x += (uint16_t)regs.b;
}
static void Op8B(void) // ADDA #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADD_HANDLER(m, regs.a);
}
static void Op9B(void) // ADDA DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADD_HANDLER(m, regs.a);
}
static void OpAB(void) // ADDA IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADD_HANDLER(m, regs.a);
}
static void OpBB(void) // ADDA ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADD_HANDLER(m, regs.a);
}
static void OpC3(void) // ADDD #
{
- uint32 m = READ_IMM16;
+ uint32_t m = READ_IMM16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpCB(void) // ADDB #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADD_HANDLER(m, regs.b);
}
static void OpD3(void) // ADDD DP
{
- uint32 m = READ_DP16;
+ uint32_t m = READ_DP16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpDB(void) // ADDB DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_ADD_HANDLER(m, regs.b);
}
static void OpE3(void) // ADDD IDX
{
- uint32 m = READ_IDX16;
+ uint32_t m = READ_IDX16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpEB(void) // ADDB IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_ADD_HANDLER(m, regs.b);
}
static void OpF3(void) // ADDD ABS
{
- uint32 m = READ_ABS16;
+ uint32_t m = READ_ABS16;
OP_ADD_HANDLER16(m, regs.a, regs.b);
}
static void OpFB(void) // ADDB ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADD_HANDLER(m, regs.b);
}
static void Op84(void) // ANDA #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_AND_HANDLER(m, regs.a);
}
static void Op94(void) // ANDA DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_AND_HANDLER(m, regs.a);
}
static void OpA4(void) // ANDA IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_AND_HANDLER(m, regs.a);
}
static void OpB4(void) // ANDA ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_AND_HANDLER(m, regs.a);
}
static void OpC4(void) // ANDB #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_AND_HANDLER(m, regs.b);
}
static void OpD4(void) // ANDB DP
{
- uint16 m = READ_DP;
+ uint16_t m = READ_DP;
OP_AND_HANDLER(m, regs.b);
}
static void OpE4(void) // ANDB IDX
{
- uint16 m = READ_IDX;
+ uint16_t m = READ_IDX;
OP_AND_HANDLER(m, regs.b);
}
static void OpF4(void) // ANDB ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_AND_HANDLER(m, regs.b);
}
// ASL opcodes
#define OP_ASL_HANDLER(m) \
- uint16 res = m << 1; \
+ uint16_t res = m << 1; \
SET_V(m, m, res); \
flagC = (res >> 8) & 0x01; \
m = res & 0xFF; \
static void Op08(void) // ASL DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op68(void) // ASL IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op78(void) // ASL ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
// ASR opcodes (arithmetic, so preserves the sign)
#define OP_ASR_HANDLER(m) \
- uint8 res = (m & 0x80) | (m >> 1); \
+ uint8_t res = (m & 0x80) | (m >> 1); \
SET_ZN(res); \
flagC = m & 0x01; \
m = res
static void Op07(void) // ASR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ASR_HANDLER(m);
WRITE_BACK(m);
static void Op67(void) // ASR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ASR_HANDLER(m);
WRITE_BACK(m);
static void Op77(void) // ASR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ASR_HANDLER(m);
WRITE_BACK(m);
static void Op16(void) // LBRA
{
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
regs.pc += offset;
}
static void Op20(void) // BRA
{
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
regs.pc += offset;
}
static void Op21(void) // BRN
{
// This is basically a 2 byte NOP
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
}
static void Op22(void) // BHI
{
// !C && !Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
//Not sure if the ! operator will do what we want, so we use ^ 1 (we need a 1 or a 0 here)...
static void Op23(void) // BLS
{
// C || Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | flagC);
static void Op24(void) // BHS/CC
{
// !C
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagC ^ 0x01);
static void Op25(void) // BLO/CS
{
// C
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
//if (disasm)
// WriteLog("[offset=%04X,flagC=%08X]", offset, flagC);
static void Op26(void) // BNE
{
// !Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ ^ 0x01);
static void Op27(void) // BEQ
{
// Z
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagZ;
static void Op28(void) // BVC
{
// !V
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagV ^ 0x01);
static void Op29(void) // BVS
{
// V
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagV;
static void Op2A(void) // BPL
{
// !N
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagN ^ 0x01);
static void Op2B(void) // BMI
{
// N
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagN;
static void Op2C(void) // BGE
{
// (N && V) || (!N && !V)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV) | ((flagN ^ 0x01) & (flagV ^ 0x01)));
static void Op2D(void) // BLT
{
// (N && !V) || (!N && V)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
static void Op2E(void) // BGT
{
// (N && V && !Z) || (!N && !V && !Z)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV & (flagZ ^ 0x01)) | ((flagN ^ 0x01) & (flagV ^ 0x01) & (flagZ ^ 0x01)));
static void Op2F(void) // BLE
{
// Z || (N && !V) || (!N && V)
- int16 offset = (int16)(int8)READ_IMM;
+ int16_t offset = (int16_t)(int8_t)READ_IMM;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | (flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
static void Op1021(void) // LBRN
{
// This is basically a 4 byte NOP
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
}
static void Op1022(void) // LBHI
{
// !C && !Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
//Not sure if the ! operator will do what we want, so we use ^ 1 (we need a 1 or a 0 here)...
static void Op1023(void) // LBLS
{
// C || Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | flagC);
static void Op1024(void) // LBHS/CC
{
// !C
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagC ^ 0x01);
static void Op1025(void) // LBLO/CS
{
// C
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagC;
static void Op1026(void) // LBNE
{
// !Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ ^ 0x01);
static void Op1027(void) // LBEQ
{
// Z
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagZ;
static void Op1028(void) // LBVC
{
// !V
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagV ^ 0x01);
static void Op1029(void) // LBVS
{
// V
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagV;
static void Op102A(void) // LBPL
{
// !N
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagN ^ 0x01);
static void Op102B(void) // LBMI
{
// N
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * flagN;
static void Op102C(void) // LBGE
{
// (N && V) || (!N && !V)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV) | ((flagN ^ 0x01) & (flagV ^ 0x01)));
static void Op102D(void) // LBLT
{
// (N && !V) || (!N && V)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
static void Op102E(void) // LBGT
{
// (N && V && !Z) || (!N && !V && !Z)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * ((flagN & flagV & (flagZ ^ 0x01)) | ((flagN ^ 0x01) & (flagV ^ 0x01) & (flagZ ^ 0x01)));
static void Op102F(void) // LBLE
{
// Z || (N && !V) || (!N && V)
- uint16 offset = READ_IMM16;
+ uint16_t offset = READ_IMM16;
#ifdef TEST_DONT_BRANCH_OPTIMIZATION
regs.pc += offset * (flagZ | (flagN & (flagV ^ 0x01)) | ((flagN ^ 0x01) & flagV));
// BIT opcodes
#define OP_BIT_HANDLER(m, acc) \
- uint8 result = acc & (m); \
+ uint8_t result = acc & (m); \
SET_ZN(result); \
CLR_V
static void Op85(void) // BITA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_BIT_HANDLER(m, regs.a);
}
static void Op95(void) // BITA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_BIT_HANDLER(m, regs.a);
}
static void OpA5(void) // BITA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_BIT_HANDLER(m, regs.a);
}
static void OpB5(void) // BITA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_BIT_HANDLER(m, regs.a);
}
static void OpC5(void) // BITB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_BIT_HANDLER(m, regs.b);
}
static void OpD5(void) // BITB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_BIT_HANDLER(m, regs.b);
}
static void OpE5(void) // BITB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_BIT_HANDLER(m, regs.b);
}
static void OpF5(void) // BITB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_BIT_HANDLER(m, regs.b);
}
static void Op0F(void) // CLR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_CLR_HANDLER(m);
WRITE_BACK(m);
static void Op6F(void) // CLR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_CLR_HANDLER(m);
WRITE_BACK(m);
static void Op7F(void) // CLR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_CLR_HANDLER(m);
WRITE_BACK(m);
// CMP opcodes
#define OP_CMP_HANDLER(m, acc) \
- uint16 sum = (uint16)(acc) - (m); \
+ uint16_t sum = (uint16_t)(acc) - (m); \
flagC = (sum >> 8) & 0x01; \
SET_V(m, acc, sum); \
SET_ZN(sum)
#define OP_CMP_HANDLER16(m, acc) \
- uint32 sum = (uint32)(acc) - (m); \
+ uint32_t sum = (uint32_t)(acc) - (m); \
flagC = (sum >> 16) & 0x01; \
SET_V16(m, acc, sum); \
SET_ZN16(sum)
static void Op81(void) // CMPA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_CMP_HANDLER(m, regs.a);
}
static void Op8C(void) // CMPX #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.x);
}
static void Op91(void) // CMPA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_CMP_HANDLER(m, regs.a);
}
static void Op9C(void) // CMPX DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.x);
}
static void OpA1(void) // CMPA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_CMP_HANDLER(m, regs.a);
}
static void OpAC(void) // CMPX IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.x);
}
static void OpB1(void) // CMPA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_CMP_HANDLER(m, regs.a);
}
static void OpBC(void) // CMPX ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.x);
}
static void OpC1(void) // CMPB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_CMP_HANDLER(m, regs.b);
}
static void OpD1(void) // CMPB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_CMP_HANDLER(m, regs.b);
}
static void OpE1(void) // CMPB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_CMP_HANDLER(m, regs.b);
}
static void OpF1(void) // CMPB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_CMP_HANDLER(m, regs.b);
}
static void Op1083(void) // CMPD #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op108C(void) // CMPY #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op1093(void) // CMPD DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op109C(void) // CMPY DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op10A3(void) // CMPD IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op10AC(void) // CMPY IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op10B3(void) // CMPD ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, (regs.a << 8) | regs.b);
}
static void Op10BC(void) // CMPY ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.y);
}
static void Op1183(void) // CMPU #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op118C(void) // CMPS #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op1193(void) // CMPU DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op119C(void) // CMPS DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op11A3(void) // CMPU IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op11AC(void) // CMPS IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op11B3(void) // CMPU ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.u);
}
static void Op11BC(void) // CMPS ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_CMP_HANDLER16(m, regs.s);
}
static void Op03(void) // COM DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_COM_HANDLER(m);
WRITE_BACK(m);
static void Op63(void) // COM IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_COM_HANDLER(m);
WRITE_BACK(m);
static void Op73(void) // COM ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_COM_HANDLER(m);
WRITE_BACK(m);
{
}
+/*
+D3F8: A6 47 LDA (7),U CC=--H----- A=30 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FA
+D3FA: 8B 01 ADDA #$01 CC=--H----- A=31 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FC
+D3FC: 19 DAA CC=--H----- A=37 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FD
+*/
+
static void Op19() // DAA
{
- uint16 result = (uint16)regs.a;
+ uint16_t result = (uint16_t)regs.a;
- if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H))
+// if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H))
+ if ((regs.a & 0x0F) > 0x09 || flagH)
result += 0x06;
- if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09))
+// if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09))
+ if ((regs.a & 0xF0) > 0x90 || flagC || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09))
result += 0x60;
- regs.a = (uint8)result;
+ regs.a = (uint8_t)result;
SET_ZN(result);
CLR_V;
flagC |= (result & 0x100) >> 8; // Overwrite carry if it was 0, otherwise, ignore
static void Op0A(void) // DEC DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void Op6A(void) // DEC IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void Op7A(void) // DEC ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void Op88(void) // EORA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_EOR_HANDLER(m, regs.a);
}
static void Op98(void) // EORA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_EOR_HANDLER(m, regs.a);
}
static void OpA8(void) // EORA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_EOR_HANDLER(m, regs.a);
}
static void OpB8(void) // EORA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_EOR_HANDLER(m, regs.a);
}
static void OpC8(void) // EORB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_EOR_HANDLER(m, regs.b);
}
static void OpD8(void) // EORB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_EOR_HANDLER(m, regs.b);
}
static void OpE8(void) // EORB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_EOR_HANDLER(m, regs.b);
}
static void OpF8(void) // EORB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_EOR_HANDLER(m, regs.b);
}
static void Op0C(void) // INC DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void Op6C(void) // INC IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void Op7C(void) // INC ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void Op17(void) // LBSR
{
- uint16 word = FetchMemW(regs.pc);
+ uint16_t word = FetchMemW(regs.pc);
PUSHS16(regs.pc);
regs.pc += word;
}
static void Op8D(void) // BSR
{
- uint16 word = (int16)(int8)READ_IMM;
+ uint16_t word = (int16_t)(int8_t)READ_IMM;
PUSHS16(regs.pc);
regs.pc += word;
}
static void Op9D(void) // JSR DP
{
- uint16 word = EA_DP;
+ uint16_t word = EA_DP;
PUSHS16(regs.pc);
regs.pc = word;
}
static void OpAD(void) // JSR IDX
{
- uint16 word = EA_IDX;
+ uint16_t word = EA_IDX;
PUSHS16(regs.pc);
regs.pc = word;
}
static void OpBD(void) // JSR ABS
{
- uint16 word = EA_ABS;
+ uint16_t word = EA_ABS;
PUSHS16(regs.pc);
regs.pc = word;
}
static void Op1E(void) // EXG
{
- uint8 m = READ_IMM;
- uint8 reg1 = m >> 4, reg2 = m & 0x0F;
- uint16 acc = ReadEXG(reg1);
- WriteEXG(reg1, ReadEXG(reg2));
- WriteEXG(reg2, acc);
+ // If bit 3 & 7 are not equal, $FF is the result (undocumented)...
+
+ uint8_t m = READ_IMM;
+ uint8_t reg1 = m >> 4, reg2 = m & 0x0F;
+ uint16_t acc1 = ReadEXG(reg1);
+ uint16_t acc2 = ReadEXG(reg2);
+
+ // If bit 3 & 7 are not equal, $FF is the result (undocumented)...
+ if (((m >> 4) ^ m) & 0x08)
+ acc1 = acc2 = 0xFF;
+
+ WriteEXG(reg1, acc2);
+ WriteEXG(reg2, acc1);
}
static void Op1F(void) // TFR
{
- uint8 m = READ_IMM;
- WriteEXG(m & 0x0F, ReadEXG(m >> 4));
+ uint8_t m = READ_IMM;
+ uint16_t acc = ReadEXG(m >> 4);
+
+ // If bit 3 & 7 are not equal, $FF is the result (undocumented)...
+ if (((m >> 4) ^ m) & 0x08)
+ acc = 0xFF;
+
+ WriteEXG(m & 0x0F, acc);
}
/*
static void Op86(void) // LDA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_LDA_HANDLER(m, regs.a);
}
static void Op8E(void) // LDX #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.x);
}
static void Op96(void) // LDA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_LDA_HANDLER(m, regs.a);
}
static void Op9E(void) // LDX DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.x);
}
static void OpA6(void) // LDA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_LDA_HANDLER(m, regs.a);
}
static void OpAE(void) // LDX IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.x);
}
static void OpB6(void) // LDA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_LDA_HANDLER(m, regs.a);
}
static void OpBE(void) // LDX ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.x);
}
static void OpC6(void) // LDB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_LDA_HANDLER(m, regs.b);
}
static void OpCC(void) // LDD #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16D(m);
}
static void OpCE(void) // LDU #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.u);
}
static void OpD6(void) // LDB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_LDA_HANDLER(m, regs.b);
}
static void OpDC(void) // LDD DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16D(m);
}
static void OpDE(void) // LDU DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.u);
}
static void OpE6(void) // LDB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_LDA_HANDLER(m, regs.b);
}
static void OpEC(void) // LDD IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16D(m);
}
static void OpEE(void) // LDU IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.u);
}
static void OpF6(void) // LDB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_LDA_HANDLER(m, regs.b);
}
static void OpFC(void) // LDD ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16D(m);
}
static void OpFE(void) // LDU ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.u);
}
static void Op108E(void) // LDY #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op109E(void) // LDY DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op10AE(void) // LDY IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op10BE(void) // LDY ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.y);
}
static void Op10CE(void) // LDS #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op10DE(void) // LDS DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op10EE(void) // LDS IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op10FE(void) // LDS ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_LDA_HANDLER16(m, regs.s);
}
static void Op04(void) // LSR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op64(void) // LSR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op74(void) // LSR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op3D(void) // MUL
{
- uint16 prod = regs.a * regs.b;
+ uint16_t prod = regs.a * regs.b;
regs.a = prod >> 8;
regs.b = prod & 0xFF;
SET_Z(prod);
// NEG opcodes
#define OP_NEG_HANDLER(m) \
- uint8 res = -m; \
+ uint8_t res = -m; \
SET_ZN(res); \
SET_V(0, m, res); \
flagC = (res >= 0x80 ? 1 : 0); \
*/
static void Op00(void) // NEG DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_NEG_HANDLER(m);
WRITE_BACK(m);
static void Op60(void) // NEG IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_NEG_HANDLER(m);
WRITE_BACK(m);
static void Op70(void) // NEG ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_NEG_HANDLER(m);
WRITE_BACK(m);
static void Op8A(void) // ORA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_OR_HANDLER(m, regs.a);
}
static void Op9A(void) // ORA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_OR_HANDLER(m, regs.a);
}
static void OpAA(void) // ORA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_OR_HANDLER(m, regs.a);
}
static void OpBA(void) // ORA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_OR_HANDLER(m, regs.a);
}
static void OpCA(void) // ORB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_OR_HANDLER(m, regs.b);
}
static void OpDA(void) // ORB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_OR_HANDLER(m, regs.b);
}
static void OpEA(void) // ORB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_OR_HANDLER(m, regs.b);
}
static void OpFA(void) // ORB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_OR_HANDLER(m, regs.b);
}
static void Op34(void) // PSHS
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x80)
PUSHS16(regs.pc);
regs.cc = PACK_FLAGS;
PUSHS(regs.cc);
}
+
+ // Count bits in each nybble to come up with correct cycle counts...
+ uint8_t bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
+ regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
static void Op35(void) // PULS
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x01)
{
PULLS16(regs.u);
if (m & 0x80)
PULLS16(regs.pc);
+
+ // Count bits in each nybble to come up with correct cycle counts...
+ uint8_t bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
+ regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
static void Op36(void) // PHSU
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x80)
PUSHU16(regs.pc);
regs.cc = PACK_FLAGS;
PUSHU(regs.cc);
}
+
+ // Count bits in each nybble to come up with correct cycle counts...
+ uint8_t bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
+ regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
static void Op37(void) // PULU
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
if (m & 0x01)
{
PULLU16(regs.s);
if (m & 0x80)
PULLU16(regs.pc);
+
+ // Count bits in each nybble to come up with correct cycle counts...
+ uint8_t bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
+ regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]);
}
/*
// ROL opcodes
#define OP_ROL_HANDLER(m) \
- uint8 res = (m << 1) | flagC; \
+ uint8_t res = (m << 1) | flagC; \
SET_ZN(res); \
SET_V(m, m, res); \
flagC = (m >> 7) & 0x01; \
*/
static void Op09(void) // ROL DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
static void Op69(void) // ROL IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
static void Op79(void) // ROL ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
// ROR opcodes
#define OP_ROR_HANDLER(m) \
- uint8 res = (flagC << 7) | (m >> 1); \
+ uint8_t res = (flagC << 7) | (m >> 1); \
SET_ZN(res); \
SET_V(m, m, res); \
flagC = m & 0x01; \
static void Op06(void) // ROR DP
{
- uint8 m;
+ uint8_t m;
READ_DP_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op66(void) // ROR IDX
{
- uint8 m;
+ uint8_t m;
READ_IDX_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op76(void) // ROR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
// SBC opcodes
#define OP_SBC_HANDLER(m, acc) \
- uint16 sum = (uint16)acc - (m) - (uint16)flagC; \
+ uint16_t sum = (uint16_t)acc - (m) - (uint16_t)flagC; \
flagC = (sum >> 8) & 0x01; \
SET_V(m, acc, sum); \
- acc = (uint8)sum; \
+ acc = (uint8_t)sum; \
SET_ZN(acc)
static void Op82(void) // SBCA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SBC_HANDLER(m, regs.a);
}
static void Op92(void) // SBCA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SBC_HANDLER(m, regs.a);
}
static void OpA2(void) // SBCA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SBC_HANDLER(m, regs.a);
}
static void OpB2(void) // SBCA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SBC_HANDLER(m, regs.a);
}
static void OpC2(void) // SBCB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SBC_HANDLER(m, regs.b);
}
static void OpD2(void) // SBCB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SBC_HANDLER(m, regs.b);
}
static void OpE2(void) // SBCB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SBC_HANDLER(m, regs.b);
}
static void OpF2(void) // SBCB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SBC_HANDLER(m, regs.b);
}
static void Op97(void) // STA DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER(addr, regs.a);
}
static void Op9F(void) // STX DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.x);
}
static void OpA7(void) // STA IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER(addr, regs.a);
}
static void OpAF(void) // STX IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.x);
}
static void OpB7(void) // STA ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER(addr, regs.a);
}
static void OpBF(void) // STX ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.x);
}
static void OpD7(void) // STB DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER(addr, regs.b);
}
static void OpDD(void) // STD DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, (regs.a << 8) | regs.b);
}
static void OpDF(void) // STU DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.u);
}
static void OpE7(void) // STB IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER(addr, regs.b);
}
static void OpED(void) // STD IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, (regs.a << 8) | regs.b);
}
static void OpEF(void) // STU IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.u);
}
static void OpF7(void) // STB ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER(addr, regs.b);
}
static void OpFD(void) // STD ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, (regs.a << 8) | regs.b);
}
static void OpFF(void) // STU ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.u);
}
static void Op109F(void) // STY DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.y);
}
static void Op10AF(void) // STY IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.y);
}
static void Op10BF(void) // STY ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.y);
}
static void Op10DF(void) // STS DP
{
- uint16 addr = EA_DP;
+ uint16_t addr = EA_DP;
OP_STA_HANDLER16(addr, regs.s);
}
static void Op10EF(void) // STS IDX
{
- uint16 addr = EA_IDX;
+ uint16_t addr = EA_IDX;
OP_STA_HANDLER16(addr, regs.s);
}
static void Op10FF(void) // STS ABS
{
- uint16 addr = EA_ABS;
+ uint16_t addr = EA_ABS;
OP_STA_HANDLER16(addr, regs.s);
}
// SUB opcodes
#define OP_SUB_HANDLER(m, acc) \
- uint16 sum = (uint16)acc - (m); \
+ uint16_t sum = (uint16_t)acc - (m); \
flagC = (sum >> 8) & 0x01; \
SET_V(m, acc, sum); \
- acc = (uint8)sum; \
+ acc = (uint8_t)sum; \
SET_ZN(acc)
#define OP_SUB_HANDLER16D(m) \
- uint32 acc = (uint32)((regs.a << 8) | regs.b); \
- uint32 sum = acc - (m); \
+ uint32_t acc = (uint32_t)((regs.a << 8) | regs.b); \
+ uint32_t sum = acc - (m); \
flagC = (sum >> 16) & 0x01; \
SET_V16(m, acc, sum); \
acc = sum & 0xFFFF; \
static void Op80(void) // SUBA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SUB_HANDLER(m, regs.a);
}
static void Op83(void) // SUBD #
{
- uint16 m = READ_IMM16;
+ uint16_t m = READ_IMM16;
OP_SUB_HANDLER16D(m);
}
static void Op90(void) // SUBA DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SUB_HANDLER(m, regs.a);
}
static void Op93(void) // SUBD DP
{
- uint16 m = READ_DP16;
+ uint16_t m = READ_DP16;
OP_SUB_HANDLER16D(m);
}
static void OpA0(void) // SUBA IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SUB_HANDLER(m, regs.a);
}
static void OpA3(void) // SUBD IDX
{
- uint16 m = READ_IDX16;
+ uint16_t m = READ_IDX16;
OP_SUB_HANDLER16D(m);
}
static void OpB0(void) // SUBA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SUB_HANDLER(m, regs.a);
}
static void OpB3(void) // SUBD ABS
{
- uint16 m = READ_ABS16;
+ uint16_t m = READ_ABS16;
OP_SUB_HANDLER16D(m);
}
static void OpC0(void) // SUBB #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_SUB_HANDLER(m, regs.b);
}
static void OpD0(void) // SUBB DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_SUB_HANDLER(m, regs.b);
}
static void OpE0(void) // SUBB IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_SUB_HANDLER(m, regs.b);
}
static void OpF0(void) // SUBB ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_SUB_HANDLER(m, regs.b);
}
static void Op0D(void) // TST DP
{
- uint8 m = READ_DP;
+ uint8_t m = READ_DP;
OP_TST_HANDLER(m);
}
static void Op6D(void) // TST IDX
{
- uint8 m = READ_IDX;
+ uint8_t m = READ_IDX;
OP_TST_HANDLER(m);
}
static void Op7D(void) // TST ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_TST_HANDLER(m);
}
Op00(); // NEG DP
}
-#else
-
-//
-// Page zero instructions...
-//
-
-static void Op00(void) // NEG DP
-{
- addr = (regs.dp << 8) | regs.RdMem(regs.pc++);
- tmp = 256 - regs.RdMem(addr);
- regs.WrMem(addr, tmp);
-
- (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp & 0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (tmp > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
-
- regs.clock += 6;
-}
-
-static void Op01(void) // NEG DP (Undocumented)
-{
- Op00();
-}
-
-static void Op03(void) // COM DP
-{
- addr = (regs.dp << 8) | regs.RdMem(regs.pc++);
- tmp = 0xFF ^ regs.RdMem(addr);
- regs.WrMem(addr, tmp);
-
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV SEC
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 6;
-}
-
-static void Op04(void) // LSR DP
-{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- tmp >>= 1; regs.WrMem(addr, tmp);
- regs.cc &= 0xF7; // CLN
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 6;
-}
-static void Op06(void) // ROR DP
-{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr);
- tmp = (tmp2>>1) + (regs.cc&0x01)*128;
- regs.WrMem(addr, tmp);
- (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op07(void) // ASR DP
-{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++); tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- tmp >>= 1;
- if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op08(void) // LSL DP
-{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++); // NEEDS OVERFLOW ADJUSTMENT
- tmp = regs.RdMem(addr);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- tmp <<= 1;
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op09(void) // ROL DP
-{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr);
- tmp = (tmp2<<1) + (regs.cc&0x01);
- regs.WrMem(addr, tmp);
- (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- ((tmp2&0x80)^((tmp2<<1)&0x80) ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op0A(void) // DEC DP
-{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- tmp = regs.RdMem(addr) - 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op0C(void) // INC DP
-{
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- tmp = regs.RdMem(addr) + 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op0D(void) // TST DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op0E(void) // JMP DP
-{
- regs.pc = (regs.dp<<8) | regs.RdMem(regs.pc++);
- regs.clock += 3;
-}
-static void Op0F(void) // CLR DP
-{
- regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), 0);
- regs.cc &= 0xF0; regs.cc |= 0x04; // CLN, SEZ, CLV, CLC
- regs.clock += 6;
-}
-
-static void Op12(void) // NOP
-{
- regs.clock += 2;
-}
-
-static void Op13(void) // SYNC
-{
- // Fix this so it does the right thing (software interrupt!)
- regs.clock += 2;
-}
-
-static void Op16(void) // LBRA
-{
-// regs.pc += SignedW(FetchW());
- regs.pc += FetchW(); // No need to make signed, both are 16 bit quantities
-
- regs.clock += 5;
-}
-
-static void Op17(void) // LBSR
-{
- uint16 word = FetchW();
- regs.WrMem(--regs.s, regs.pc & 0xFF);
- regs.WrMem(--regs.s, regs.pc >> 8);
-// regs.pc += SignedW(addr);
- regs.pc += word; // No need to make signed, both are 16 bit
-
- regs.clock += 9;
-}
-
-static void Op19(void) // DAA
-{
-#if 0
- uint8 result = regs.a;
-
- if ((regs.cc&0x20) || ((regs.a&0x0F) > 0x09)) // H set or lo nyb too big?
- {
-// regs.a += 0x06;
- result += 0x06;
- regs.cc |= 0x20; // Then adjust & set half carry
- }
-
- if ((regs.cc&0x01) || (regs.a > 0x9F)) // C set or hi nyb too big?
- {
-// regs.a += 0x60;
- result += 0x60;
- regs.cc |= 0x01; // Then adjust & set carry
- }
-
- regs.a = result;
-
- regs.cc &= 0xF1; // CL NZV
- if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
-#else
- uint16 result = (uint16)regs.a;
-
- if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H))
- result += 0x06;
-
- if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09))
- result += 0x60;
-
- regs.a = (uint8)result;
-// SET_ZN(result);
-// CLR_V; // Not sure this is correct...
- regs.cc &= 0xF1; // CL NZV
- if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
-// flagC |= (result & 0x100) >> 8; // Overwrite carry if it was 0, otherwise, ignore
- regs.cc |= (result & 0x100) > 8;
-#endif
- regs.clock += 2;
-}
-
-static void Op1A(void) // ORCC #
-{
- regs.cc |= regs.RdMem(regs.pc++);
-
- regs.clock += 3;
-}
-
-static void Op1C(void) // ANDCC #
-{
- regs.cc &= regs.RdMem(regs.pc++);
-
- regs.clock += 3;
-}
-
-static void Op1D(void) // SEX
-{
- (regs.b & 0x80 ? regs.a = 0xFF : regs.a = 0x00);
-
- ((regs.a | regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a & 0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 2;
-}
-
-static void Op1E(void) // EXG
-{
- tmp = regs.RdMem(regs.pc++);
- addr = ReadEXG(tmp >> 4);
- WriteEXG(tmp >> 4, ReadEXG(tmp & 0xF));
- WriteEXG(tmp & 0xF, addr);
-
- regs.clock += 8;
-}
-
-static void Op1F(void) // TFR
-{
- tmp = regs.RdMem(regs.pc++);
- WriteEXG(tmp&0xF, ReadEXG(tmp>>4));
- regs.clock += 7;
-}
-
-static void Op20(void) // BRA
-{
-// regs.pc += SignedB(regs.RdMem(regs.pc++)); // Branch always
- regs.pc += (int16)(int8)regs.RdMem(regs.pc) + 1; // Branch always
-
- regs.clock += 3;
-}
-
-static void Op21(void) // BRN
-{
- regs.RdMem(regs.pc++);
-
- regs.clock += 3;
-}
-
-static void Op22(void) // BHI
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (!(regs.cc & 0x05))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op23(void) // BLS
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (regs.cc & 0x05)
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op24(void) // BCC (BHS)
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (!(regs.cc & 0x01))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op25(void) // BCS (BLO)
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (regs.cc & 0x01)
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op26(void) // BNE
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (!(regs.cc & 0x04))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op27(void) // BEQ
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (regs.cc & 0x04)
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op28(void) // BVC
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (!(regs.cc & 0x02))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op29(void) // BVS
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (regs.cc & 0x02)
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op2A(void) // BPL
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (!(regs.cc & 0x08))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op2B(void) // BMI
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (regs.cc & 0x08)
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op2C(void) // BGE
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op2D(void) // BLT
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op2E(void) // BGT
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op2F(void) // BLE
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
-
- if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
- regs.pc += word;
-
- regs.clock += 3;
-}
-
-static void Op30(void) // LEAX
-{
- regs.x = DecodeIDX(regs.RdMem(regs.pc++));
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 4;
-}
-static void Op31(void) // LEAY
-{
- regs.y = DecodeIDX(regs.RdMem(regs.pc++));
- (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 4;
-}
-static void Op32(void) // LEAS
-{
- regs.s = DecodeIDX(regs.RdMem(regs.pc++));
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 4;
-}
-static void Op33(void) // LEAU
-{
- regs.u = DecodeIDX(regs.RdMem(regs.pc++));
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 4;
-}
-static void Op34(void) // PSHS
-{
- tmp = regs.RdMem(regs.pc++);
- if (tmp&0x80) { regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8); }
- if (tmp&0x40) { regs.WrMem(--regs.s, regs.u&0xFF); regs.WrMem(--regs.s, regs.u>>8); }
- if (tmp&0x20) { regs.WrMem(--regs.s, regs.y&0xFF); regs.WrMem(--regs.s, regs.y>>8); }
- if (tmp&0x10) { regs.WrMem(--regs.s, regs.x&0xFF); regs.WrMem(--regs.s, regs.x>>8); }
- if (tmp&0x08) regs.WrMem(--regs.s, regs.dp);
- if (tmp&0x04) regs.WrMem(--regs.s, regs.b);
- if (tmp&0x02) regs.WrMem(--regs.s, regs.a);
- if (tmp&0x01) regs.WrMem(--regs.s, regs.cc);
- regs.clock += 5;
-}
-static void Op35(void) // PULS
-{
- tmp = regs.RdMem(regs.pc++);
- if (tmp&0x01) regs.cc = regs.RdMem(regs.s++);
- if (tmp&0x02) regs.a = regs.RdMem(regs.s++);
- if (tmp&0x04) regs.b = regs.RdMem(regs.s++);
- if (tmp&0x08) regs.dp = regs.RdMem(regs.s++);
- if (tmp&0x10) regs.x = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- if (tmp&0x20) regs.y = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- if (tmp&0x40) regs.u = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- if (tmp&0x80) regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.clock += 5;
-}
-
-static void Op36(void) // PSHU
-{
- tmp = regs.RdMem(regs.pc++);
-
- if (tmp & 0x80) { regs.WrMem(--regs.u, regs.pc & 0xFF); regs.WrMem(--regs.u, regs.pc >> 8); }
- if (tmp & 0x40) { regs.WrMem(--regs.u, regs.s & 0xFF); regs.WrMem(--regs.u, regs.s >> 8); }
- if (tmp & 0x20) { regs.WrMem(--regs.u, regs.y & 0xFF); regs.WrMem(--regs.u, regs.y >> 8); }
- if (tmp & 0x10) { regs.WrMem(--regs.u, regs.x & 0xFF); regs.WrMem(--regs.u, regs.x >> 8); }
- if (tmp & 0x08) regs.WrMem(--regs.u, regs.dp);
- if (tmp & 0x04) regs.WrMem(--regs.u, regs.b);
- if (tmp & 0x02) regs.WrMem(--regs.u, regs.a);
- if (tmp & 0x01) regs.WrMem(--regs.u, regs.cc);
-
- regs.clock += 5;
-}
-
-static void Op37(void) // PULU
-{
- tmp = regs.RdMem(regs.pc++);
- if (tmp&0x01) regs.cc = regs.RdMem(regs.u++);
- if (tmp&0x02) regs.a = regs.RdMem(regs.u++);
- if (tmp&0x04) regs.b = regs.RdMem(regs.u++);
- if (tmp&0x08) regs.dp = regs.RdMem(regs.u++);
- if (tmp&0x10) regs.x = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
- if (tmp&0x20) regs.y = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
- if (tmp&0x40) regs.s = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
- if (tmp&0x80) regs.pc = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
- regs.clock += 5;
-}
-static void Op39(void) // RTS
-{
- regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.clock += 5;
-}
-static void Op3B(void) // RTI
-{
- regs.cc = regs.RdMem(regs.s++);
- if (regs.cc&0x80) // If E flag set, pull all regs
- {
- regs.a = regs.RdMem(regs.s++); regs.b = regs.RdMem(regs.s++); regs.dp = regs.RdMem(regs.s++);
- regs.x = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.y = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.u = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.clock += 15;
- }
- else
- {
- regs.clock += 6;
- }
- regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
-}
-static void Op3C(void) // CWAI
-{
- regs.cc &= regs.RdMem(regs.pc++); regs.cc |= 0x80;
- regs.clock += 1000000; // Force interrupt
-}
-static void Op3D(void) // MUL
-{
- addr = regs.a * regs.b; regs.a = addr>>8; regs.b = addr&0xFF;
- (addr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
- (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
- regs.clock += 11;
-}
-static void Op3E(void) // RESET
-{
-}
-static void Op3F(void) // SWI
-{
-}
-static void Op40(void) // NEGA
-{
- regs.a = 256 - regs.a;
- (regs.a > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op43(void) // COMA
-{
- regs.a ^= 0xFF;
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op44(void) // LSRA
-{
- (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- regs.a >>= 1;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op46(void) // RORA
-{
- tmp = regs.a; regs.a = (tmp>>1) + (regs.cc&0x01)*128;
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op47(void) // ASRA
-{
- (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- regs.a >>= 1; // Do the shift
- if (regs.a&0x40) regs.a |= 0x80; // Set neg if it was set
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op48(void) // LSLA [Keep checking from here...]
-{
- (regs.a&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- regs.a <<= 1;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op49(void) // ROLA
-{
- tmp = regs.a; regs.a = (tmp<<1) + (regs.cc&0x01);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op4A(void) // DECA
-{
- regs.a--;
- (regs.a == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op4C(void) // INCA
- {
- regs.a++;
- (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op4D(void) // TSTA
- {
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op4F(void) // CLRA
-{
- regs.a = 0;
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 2;
-}
-static void Op50(void) // NEGB
- {
- regs.b = 256 - regs.b;
-// ((regs.b^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
- (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- regs.clock += 2;
- }
-static void Op53(void) // COMB
- {
- regs.b ^= 0xFF;
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op54(void) // LSRB
- {
- (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- regs.b >>= 1;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op56(void) // RORB
- {
- tmp = regs.b; regs.b = (regs.b >> 1) + (regs.cc&0x01)*128;
- (tmp&0x01 ? regs.cc |=0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op57(void) // ASRB
- {
- (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- regs.b >>= 1; // Do the shift
- if (regs.b&0x40) regs.b |= 0x80; // Set neg if it was set
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op58(void) // LSLB
- {
- (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- regs.b <<= 1;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op59(void) // ROLB
-{
- tmp = regs.b;
- regs.b = (tmp<<1) + (regs.cc&0x01);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op5A(void) // DECB
- {
- regs.b--;
- (regs.b == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op5C(void) // INCB
- {
- regs.b++;
- (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op5D(void) // TSTB
- {
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op5F(void) // CLRB
- {
- regs.b = 0;
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 2;
- }
-static void Op60(void) // NEG IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
- regs.WrMem(addr, res);
-// ((res^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
- (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- regs.clock += 6;
- }
-static void Op63(void) // COM IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr) ^ 0xFF;
- regs.WrMem(addr, tmp);
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op64(void) // LSR IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- tmp >>= 1; regs.WrMem(addr, tmp);
- regs.cc &= 0xF7; // CLN
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 6;
- }
-static void Op66(void) // ROR IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
- tmp = (tmp >> 1) + (regs.cc&0x01)*128;
- regs.WrMem(addr, tmp);
- (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op67(void) // ASR IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- tmp >>= 1;
- if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op68(void) // LSL IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- tmp <<= 1;
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op69(void) // ROL IDX
-{
- uint8 tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- tmp = (tmp2<<1) + (regs.cc&0x01);
- regs.WrMem(addr, tmp);
- (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op6A(void) // DEC IDX
- {
- uint8 tmp; uint16 addr;
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr) - 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op6C(void) // INC IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr) + 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op6D(void) // TST IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op6E(void) // JMP IDX
-{
- regs.pc = DecodeIDX(regs.RdMem(regs.pc++));
- regs.clock += 3;
-}
-static void Op6F(void) // CLR IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, 0);
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 6;
-}
-static void Op70(void) // NEG ABS
- {
- addr = FetchW();
- tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
- regs.WrMem(addr, res);
- (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- regs.clock += 7;
- }
-static void Op73(void) // COM ABS
- {
- addr = FetchW();
- tmp = regs.RdMem(addr) ^ 0xFF;
- regs.WrMem(addr, tmp);
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op74(void) // LSR ABS
- {
- addr = FetchW();
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- tmp >>= 1; regs.WrMem(addr, tmp);
- regs.cc &= 0xF7; // CLN
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 7;
- }
-static void Op76(void) // ROR ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
- tmp = (tmp >> 1) + (regs.cc&0x01)*128;
- regs.WrMem(addr, tmp);
- (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op77(void) // ASR ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- tmp >>= 1;
- if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op78(void) // LSL ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- tmp <<= 1;
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op79(void) // ROL ABS
-{
- uint8 tmp2 = regs.RdMem(FetchW());
- tmp = (tmp2<<1) + (regs.cc&0x01);
- regs.WrMem(addr, tmp);
- (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
-}
-static void Op7A(void) // DEC ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr) - 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op7C(void) // INC ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr) + 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-
-static void Op7D(void) // TST ABS
-{
- uint8 tmp = regs.RdMem(FetchW());
-
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 7;
-}
-
-static void Op7E(void) // JMP ABS
-{
- regs.pc = FetchW();
- regs.clock += 3;
-}
-static void Op7F(void) // CLR ABS
- {
- regs.WrMem(FetchW(), 0);
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 7;
- }
-static void Op80(void) // SUBA #
-{
- uint8 tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
- regs.a -= tmp;
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op81(void) // CMPA #
-{
- tmp = regs.RdMem(regs.pc++);
- uint8 db = regs.a - tmp;
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op82(void) // SBCA #
-{
- tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op83(void) // SUBD #
-{
- addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- dr -= addr;
- (ds < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 4;
-}
-static void Op85(void) // BITA #
- {
- tmp = regs.a & regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op86(void) // LDA #
- {
- regs.a = regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op88(void) // EORA #
- {
- regs.a ^= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op8A(void) // ORA #
- {
- regs.a |= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op8C(void) // CMPX #
-{
- addr = FetchW();
- uint16 dw = regs.x - addr;
- (regs.x < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-
-static void Op8D(void) // Bregs.s
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
- regs.WrMem(--regs.s, regs.pc & 0xFF);
- regs.WrMem(--regs.s, regs.pc >> 8);
- regs.pc += word;
-
- regs.clock += 7;
-}
-
-static void Op8E(void) // LDX #
- {
- regs.x = FetchW();
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 3;
- }
-static void Op90(void) // SUBA DP
- {
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
- regs.a -= tmp;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void Op91(void) // CMPA DP
- {
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- uint8 db = regs.a - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void Op92(void) // SBCA DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void Op93(void) // SUBD DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- dr -= adr2;
- (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 6;
-}
-static void Op84(void) // ANDA #
- {
- regs.a &= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op94(void) // ANDA DP
-{
- regs.a &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 4;
-}
-static void Op95(void) // BITA DP
- {
- tmp = regs.a & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op96(void) // LDA DP
-{
- regs.a = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xF1; // CLN CLZ CLV
- if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 4;
-}
-static void Op97(void) // STA DP
- {
- regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.a);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op98(void) // EORA DP
- {
- regs.a ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op9A(void) // ORA DP
- {
- regs.a |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op9C(void) // CMPX DP
- {
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.x - adr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.x < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^adr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 6;
- }
-static void Op9D(void) // JSR DP
- {
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // JSR to DP location...
- regs.clock += 7;
- }
-static void Op9E(void) // LDX DP
- {
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void Op9F(void) // STX DP
- {
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpA0(void) // SUBA IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
- regs.a -= tmp;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void OpA1(void) // CMPA IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- uint8 db = regs.a - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void OpA2(void) // SBCA IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpA3(void) // SUBD IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++)); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- dr -= adr2;
- (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 6;
-}
-static void OpA4(void) // ANDA IDX
- {
- regs.a &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpA5(void) // BITA IDX
- {
- tmp = regs.a & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpA6(void) // LDA IDX
-{
- regs.a = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 4;
-}
-static void OpA7(void) // STA IDX
-{
- regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.a);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 4;
-}
-static void OpA8(void) // EORA IDX
- {
- regs.a ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpAA(void) // ORA IDX
-{
- regs.a |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpAC(void) // CMPX IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.x - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 6;
-}
-static void OpAD(void) // JSR IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // Jregs.s directly to IDX ptr
- regs.clock += 7;
-}
-static void OpAE(void) // LDX IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpAF(void) // STX IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.x == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.x&0x8000) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 5;
-}
-static void OpB0(void) // SUBA ABS
- {
- tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
- regs.a -= tmp;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
- }
-static void OpB1(void) // CMPA ABS
- {
- tmp = regs.RdMem(FetchW());
- uint8 db = regs.a - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
- }
-static void OpB2(void) // SBCA ABS
-{
- tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB3(void) // SUBD ABS
-{
- addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- dr -= adr2;
- (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 7;
-}
-static void OpB4(void) // ANDA ABS
-{
- regs.a &= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB5(void) // BITA ABS
-{
- tmp = regs.a & regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB6(void) // LDA ABS
-{
- regs.a = regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB7(void) // STA ABS
-{
- regs.WrMem(FetchW(), regs.a);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB8(void) // EORA ABS
-{
- regs.a ^= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpBA(void) // ORA ABS
-{
- regs.a |= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpBC(void) // CMPX ABS
-{
- addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.x - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 7;
-}
-static void OpBD(void) // JSR ABS
-{
- addr = FetchW();
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // Go to absolute address (Not indir)
- regs.clock += 8;
-}
-
-static void OpBE(void) // LDX ABS
-{
-// addr = FetchW();
-// regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.x = RdMemW(FetchW());
-
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 6;
-}
-
-static void OpBF(void) // STX ABS
-{
-// addr = FetchW();
-// regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
- WrMemW(FetchW(), regs.x);
-
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 6;
-}
-
-static void OpC0(void) // SUBB #
- {
- tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 2;
- }
-static void OpC1(void) // CMPB #
- {
- tmp = regs.RdMem(regs.pc++);
- uint8 db = regs.b - tmp;
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpC2(void) // SBCB #
-{
- tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void OpC4(void) // ANDB #
- {
- regs.b &= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpC5(void) // BITB #
-{
- tmp = regs.b & regs.RdMem(regs.pc++);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (tmp == 0) regs.cc |= 0x04; // Set Zero flag
- if (tmp&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 2;
-}
-static void OpC6(void) // LDB #
-{
- regs.b = regs.RdMem(regs.pc++);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.b == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.b&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 2;
-}
-static void OpC8(void) // EORB #
- {
- regs.b ^= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpCA(void) // ORB #
- {
- regs.b |= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpCC(void) // LDD #
-{
- regs.a = regs.RdMem(regs.pc++); regs.b = regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 3;
-}
-static void OpCE(void) // LDU #
-{
- regs.u = FetchW();
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 3;
-}
-static void OpD0(void) // SUBB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpD1(void) // CMPB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- uint8 db = regs.b - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpD2(void) // SBCB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpD4(void) // ANDB DP
- {
- regs.b &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpD5(void) // BITB DP
- {
- tmp = regs.b & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpD6(void) // LDB DP
-{
- regs.b = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpD7(void) // STB DP
- {
- regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.b);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpD8(void) // EORB DP
- {
- regs.b ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpDA(void) // ORB DP
- {
- regs.b |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpDC(void) // LDD DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpDD(void) // STD DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
- regs.cc &= 0xFD; // CLV
- ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpDE(void) // LDU DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpDF(void) // STU DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpE0(void) // SUBB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpE1(void) // CMPB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- uint8 db = regs.b - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpE2(void) // SBCB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpE4(void) // ANDB IDX
- {
- regs.b &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpE5(void) // BITB IDX
- {
- tmp = regs.b & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpE6(void) // LDB IDX
- {
- regs.b = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpE7(void) // STB IDX
-{
- regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.b);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.b == 0) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.b&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpE8(void) // EORB IDX
- {
- regs.b ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpEA(void) // ORB IDX
- {
- regs.b |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpEC(void) // LDD IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpED(void) // STD IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
- regs.cc &= 0xF1; // CLV CLZ CLZ
- if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpEE(void) // LDU IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 5;
-}
-static void OpEF(void) // STU IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 5;
-}
-static void OpF0(void) // SUBB ABS
- {
- tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- }
-static void OpF1(void) // CMPB ABS
- {
- tmp = regs.RdMem(FetchW());
- uint8 db = regs.b - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
- }
-static void OpF2(void) // SBCB ABS
-{
- tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
-}
-static void OpF4(void) // ANDB ABS
- {
- regs.b &= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF5(void) // BITB ABS
- {
- tmp = regs.b & regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF6(void) // LDB ABS
- {
- regs.b = regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF7(void) // STB ABS
- {
- regs.WrMem(FetchW(), regs.b);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF8(void) // EORB ABS
- {
- regs.b ^= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpFA(void) // ORB ABS
- {
- regs.b |= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpFC(void) // LDD ABS
- {
- addr = FetchW();
- regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void OpFD(void) // STD ABS
- {
- addr = FetchW();
- regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
- regs.cc &= 0xFD; // CLV
- ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void OpFE(void) // LDU ABS
- {
- addr = FetchW();
- regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void OpFF(void) // STU ABS
- {
- addr = FetchW();
- regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-
-//
-// Page one opcodes' execute code
-//
-
-static void Op1021(void) // LBRN
-{
- addr = FetchW();
-
- regs.clock += 5;
-}
-
-static void Op1022(void) // LBHI
-{
- uint16 word = FetchW();
-
- if (!((regs.cc & 0x01) | (regs.cc & 0x04)))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op1023(void) // LBLS
-{
- uint16 word = FetchW();
-
- if ((regs.cc & 0x01) | (regs.cc & 0x04))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op1024(void) // LBCC (LBHS)
-{
- uint16 word = FetchW();
-
- if (!(regs.cc & 0x01))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op1025(void) // LBCS (LBLO)
-{
- uint16 word = FetchW();
-
- if (regs.cc & 0x01)
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op1026(void) // LBNE
-{
- uint16 word = FetchW();
-
- if (!(regs.cc & 0x04))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op1027(void) // LBEQ
-{
- uint16 word = FetchW();
-
- if (regs.cc & 0x04)
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op1028(void) // LBVC
-{
- uint16 word = FetchW();
-
- if (!(regs.cc & 0x02))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op1029(void) // LBVS
-{
- uint16 word = FetchW();
-
- if (regs.cc & 0x02)
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op102A(void) // LBPL
-{
- uint16 word = FetchW();
-
- if (!(regs.cc & 0x08))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op102B(void) // LBMI
-{
- uint16 word = FetchW();
-
- if (regs.cc & 0x08)
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op102C(void) // LBGE
-{
- uint16 word = FetchW();
-
- if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op102D(void) // LBLT
-{
- uint16 word = FetchW();
-
- if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op102E(void) // LBGT
-{
- uint16 word = FetchW();
-
- if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op102F(void) // LBLE
-{
- uint16 word = FetchW();
-
- if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
- regs.pc += word;
-
- regs.clock += 5;
-}
-
-static void Op103F(void) // SWI2 (Not yet implemented)
-{
- regs.clock += 20;
-}
-static void Op1083(void) // CMPD #
- {
- addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b;
- uint16 dw = dr - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((dr^addr^dw^((uint16)regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 5;
- }
-static void Op108C(void) // CMPY #
- {
- addr = FetchW();
- uint16 dw = regs.y - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.y^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 5;
- }
-static void Op108E(void) // LDY #
- {
- regs.y = FetchW();
- regs.cc &= 0xFD; // CLV
- (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op1093(void) // CMPD DP
- {
- uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++), dr = (regs.a<<8)|regs.b;
- addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- uint16 dw = dr - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((dr^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 7;
- }
-static void Op109C(void) // CMPY DP
- {
- uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
- addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- uint16 dw = regs.y - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.y^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 7;
- }
-
-static void Op109E(void) // LDY DP
- {
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-
-static void Op109F(void) // STY DP
- {
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op10A3(void) // CMPD IDX
-{
- uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++)), dr = (regs.a<<8)|regs.b;
- addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- uint16 dw = dr - addr;
- regs.cc &= 0xF0; // CLC CLV CLZ CLN
- if (dr < addr) regs.cc |= 0x01; // Set Carry flag
- if ((dr^addr^dw^(regs.cc<<15))&0x8000) regs.cc |= 0x02; // Set oVerflow
- if (dw == 0) regs.cc |= 0x04; // Set Zero flag
- if (dw&0x8000) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 7;
-}
-static void Op10AC(void) // CMPY IDX
- {
- uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++));
- addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- uint16 dw = regs.y - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.y^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 7;
- }
-static void Op10AE(void) // LDY IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.y == 0) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.y&0x8000) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op10AF(void) // STY IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op10B3(void) // CMPD ABS
- {
- addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b;
- uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = dr - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (dr < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^dr^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 8;
- }
-static void Op10BC(void) // CMPY ABS
- {
- addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.y - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.y < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.y^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 8;
- }
-static void Op10BE(void) // LDY ABS
- {
- addr = FetchW();
- regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op10BF(void) // STY ABS
- {
- addr = FetchW();
- regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op10CE(void) // LDS #
- {
- regs.s = FetchW();
- regs.cc &= 0xFD; // CLV
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op10DE(void) // LDS DP
- {
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op10DF(void) // STS DP
- {
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op10EE(void) // LDS IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op10EF(void) // STS IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op10FE(void) // LDS ABS
- {
- addr = FetchW();
- regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op10FF(void) // STS ABS
-{
- addr = FetchW();
- regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
-}
-
-//
-// Page two opcodes' execute code
-//
-
-static void Op113F(void) // SWI3
- {
- regs.clock += 20;
- }
-static void Op1183(void) // CMPU #
- {
- addr = FetchW();
- uint16 dw = regs.u - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 5;
- }
-static void Op118C(void) // CMPS #
- {
- addr = FetchW();
- uint16 dw = regs.s - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 5;
- }
-static void Op1193(void) // CMPU DP
- {
- uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
- addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- uint16 dw = regs.u - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 7;
- }
-static void Op119C(void) // CMPS DP
- {
- uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
- addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
- uint16 dw = regs.s - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 7;
- }
-static void Op11A3(void) // CMPU IDX
- {
- uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
- addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
- uint16 dw = regs.u - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 7;
- }
-static void Op11AC(void) // CMPS IDX
- {
- uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
- addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
- uint16 dw = regs.s - addr;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 7;
- }
-static void Op11B3(void) // CMPU ABS
- {
- addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.u - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.u < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.u^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 8;
- }
-
-static void Op11BC(void) // CMPS ABS
-{
- addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.s - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.s < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- (((regs.cc<<15)^regs.s^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 8;
-}
-#endif
-
//temp, for testing...
#ifdef __DEBUG__
-static uint8 backTrace[256];
-static uint16 btPC[256];
+static uint8_t backTrace[256];
+static uint16_t btPC[256];
static int btPtr = 0;//*/
#endif
static void Op__(void) // Illegal opcode
static void Op10(void)
{
// exec_op1[regs.RdMem(regs.pc++)]();
- uint8 opcode = regs.RdMem(regs.pc++);
+ uint8_t opcode = regs.RdMem(regs.pc++);
exec_op1[opcode]();
regs.clock += page1Cycles[opcode];
}
static void Op11(void)
{
// exec_op2[regs.RdMem(regs.pc++)]();
- uint8 opcode = regs.RdMem(regs.pc++);
+ uint8_t opcode = regs.RdMem(regs.pc++);
exec_op2[opcode]();
regs.clock += page2Cycles[opcode];
}
//
// Internal "memcpy" (so we don't have to link with any external libraries!)
//
-static void myMemcpy(void * dst, void * src, uint32 size)
+static void myMemcpy(void * dst, void * src, uint32_t size)
{
- uint8 * d = (uint8 *)dst, * s = (uint8 *)src;
+ uint8_t * d = (uint8_t *)dst, * s = (uint8_t *)src;
- for(uint32 i=0; i<size; i++)
+ for(uint32_t i=0; i<size; i++)
d[i] = s[i];
}
#ifdef DEBUG_ILLEGAL
#include "log.h"
#include "dis6809.h"
-uint8 btPtr = 0;
-uint8 backTrace[256];
+uint8_t btPtr = 0;
+uint8_t backTrace[256];
V6809REGS btRegs[256];
bool tripped = false;
#endif
-void Execute6809(V6809REGS * context, uint32 cycles)
+void Execute6809(V6809REGS * context, uint32_t cycles)
{
// If this is not in place, the clockOverrun calculations can cause the V6809 to get
// stuck in an infinite loop.
return;
myMemcpy(®s, context, sizeof(V6809REGS));
- UNPACK_FLAGS; // Explode flags register into individual uint8s
+ UNPACK_FLAGS; // Explode flags register into individual uint8_ts
// Execute here...
// through we remove them from the cycles passed in in order to come out
// approximately even. Over the long run, this unevenness in execution times
// evens out.
- uint64 endCycles = regs.clock + (uint64)(cycles - regs.clockOverrun);
+ uint64_t endCycles = regs.clock + (uint64_t)(cycles - regs.clockOverrun);
while (regs.clock < endCycles)
{
WriteLog("V6809: Executed illegal instruction!!!!\n\nBacktrace:\n\n");
regs.cpuFlags &= ~V6809_STATE_ILLEGAL_INST;
- for(uint16 i=btPtr; i<btPtr+256; i++)
+ for(uint16_t i=btPtr; i<btPtr+256; i++)
{
Decode6809(btRegs[i & 0xFF].pc);
// Note that these values are *before* execution, so stale...
btPtr = (btPtr + 1) & 0xFF;//*/
#endif
// exec_op0[regs.RdMem(regs.pc++)]();
- uint8 opcode = regs.RdMem(regs.pc++);
+ uint8_t opcode = regs.RdMem(regs.pc++);
exec_op0[opcode]();
regs.clock += page0Cycles[opcode];
// Handle any pending interrupts
// Hmm, this is bad and only works when flags are changed OUTSIDE of the running context...
-// uint32 flags = context->cpuFlags;
- uint32 flags = regs.cpuFlags;
+// uint32_t flags = context->cpuFlags;
+ uint32_t flags = regs.cpuFlags;
if (flags & V6809_ASSERT_LINE_RESET) // *** RESET handler ***
{
}
}
#ifdef __DEBUG__
-if (disasm) WriteLog("\tCC=%s%s%s%s%s%s%s%s A=%02X B=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+if (disasm) WriteLog("CC=%s%s%s%s%s%s%s%s A=%02X B=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
(flagE ? "E" : "-"), (flagF ? "F" : "-"), (flagH ? "H" : "-"), (flagI ? "I" : "-"),
(flagN ? "N" : "-"), (flagZ ? "Z" : "-"), (flagV ? "V" : "-"), (flagC ? "C" : "-"),
regs.a, regs.b, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
}
// Keep track of how much we overran so we can adjust on the next run...
- regs.clockOverrun = (uint32)(regs.clock - endCycles);
+ regs.clockOverrun = (uint32_t)(regs.clock - endCycles);
regs.cc = PACK_FLAGS; // Mash flags back into the CC register
myMemcpy(context, ®s, sizeof(V6809REGS));
//
// Get the clock of the currently executing CPU
//
-uint64 GetCurrentV6809Clock(void)
+uint64_t GetCurrentV6809Clock(void)
{
return regs.clock;
}
//
// Get the PC of the currently executing CPU
//
-uint16 GetCurrentV6809PC(void)
+uint16_t GetCurrentV6809PC(void)
{
return regs.pc;
}
// Set a line of the currently executing CPU
-void SetLineOfCurrentV6809(uint32 line)
+void SetLineOfCurrentV6809(uint32_t line)
{
regs.cpuFlags |= line;
}
// Clear a line of the currently executing CPU
-void ClearLineOfCurrentV6809(uint32 line)
+void ClearLineOfCurrentV6809(uint32_t line)
{
#ifdef __DEBUG__
if (disasm)
projects / stargem2 / blobdiff