5 Test: Operand=01111111 prior to execution?
6 Test: Set equal to result or N(+)C after shift has occurred.
7 Test: Sign bit of most significant byte or result=1?
- 8 Test: 2's compliment overflow from subtraction of least
+ 8 Test: 2's compliment overflow from subtraction of least
significant bytes?
9 Test: Result less than zero? (Bit 15=1)
A Load Condition Code Register from Stack.
- B Set when interrupt occurs. If previously set, a NMI is
+ B Set when interrupt occurs. If previously set, a NMI is
required to exit the wait state.
C Set according to the contents of Accumulator A.
*2 +-----------------+
+> C -> 76543210 -+
- *3 C <- 76543210 <- 0(Data)
+ *3 C <- 76543210 <- 0(Data)
+-+
- *4 À>76543210 -> C
+ *4 �>76543210 -> C
*5 (Data)0 -> 76543210 -> C
regs.pc = RdMemW(0xFFF8); // And do it!
regs.clock += 0; // How many???
+#warning "IRQ/NMI lines should not be cleared here... !!! FIX !!!"
context->cpuFlags &= ~V6808_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
regs.cpuFlags &= ~V6808_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
}