#define SET_N(r) (regs.cc = ((r) & 0x80 ? regs.cc | FLAG_N : regs.cc & ~FLAG_N))
//Not sure that this code is computing the carry correctly... Investigate! [Seems to be]
-#define SET_C_ADD(a,b) (regs.cc = ((uint8)(b) > (uint8)(~(a)) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
-//#define SET_C_SUB(a,b) (regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
-#define SET_C_CMP(a,b) (regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_C_ADD(a,b) (regs.cc = ((uint8_t)(b) > (uint8_t)(~(a)) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+//#define SET_C_SUB(a,b) (regs.cc = ((uint8_t)(b) >= (uint8_t)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_C_CMP(a,b) (regs.cc = ((uint8_t)(b) >= (uint8_t)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
#define SET_ZN(r) SET_N(r); SET_Z(r)
#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
//#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b)
#define READ_IND_ZP_Y regs.RdMem(EA_IND_ZP_Y)
#define READ_IND_ZP regs.RdMem(EA_IND_ZP)
-#define READ_IMM_WB(v) uint16 addr = EA_IMM; v = regs.RdMem(addr)
-#define READ_ZP_WB(v) uint16 addr = EA_ZP; v = regs.RdMem(addr)
-#define READ_ZP_X_WB(v) uint16 addr = EA_ZP_X; v = regs.RdMem(addr)
-#define READ_ABS_WB(v) uint16 addr = EA_ABS; v = regs.RdMem(addr)
-#define READ_ABS_X_WB(v) uint16 addr = EA_ABS_X; v = regs.RdMem(addr)
-#define READ_ABS_Y_WB(v) uint16 addr = EA_ABS_Y; v = regs.RdMem(addr)
-#define READ_IND_ZP_X_WB(v) uint16 addr = EA_IND_ZP_X; v = regs.RdMem(addr)
-#define READ_IND_ZP_Y_WB(v) uint16 addr = EA_IND_ZP_Y; v = regs.RdMem(addr)
-#define READ_IND_ZP_WB(v) uint16 addr = EA_IND_ZP; v = regs.RdMem(addr)
+#define READ_IMM_WB(v) uint16_t addr = EA_IMM; v = regs.RdMem(addr)
+#define READ_ZP_WB(v) uint16_t addr = EA_ZP; v = regs.RdMem(addr)
+#define READ_ZP_X_WB(v) uint16_t addr = EA_ZP_X; v = regs.RdMem(addr)
+#define READ_ABS_WB(v) uint16_t addr = EA_ABS; v = regs.RdMem(addr)
+#define READ_ABS_X_WB(v) uint16_t addr = EA_ABS_X; v = regs.RdMem(addr)
+#define READ_ABS_Y_WB(v) uint16_t addr = EA_ABS_Y; v = regs.RdMem(addr)
+#define READ_IND_ZP_X_WB(v) uint16_t addr = EA_IND_ZP_X; v = regs.RdMem(addr)
+#define READ_IND_ZP_Y_WB(v) uint16_t addr = EA_IND_ZP_Y; v = regs.RdMem(addr)
+#define READ_IND_ZP_WB(v) uint16_t addr = EA_IND_ZP; v = regs.RdMem(addr)
#define WRITE_BACK(d) regs.WrMem(addr, (d))
//Also this doesn't take into account the extra cycle it takes when an indirect fetch
//(ABS, ABS X/Y, ZP) crosses a page boundary, or extra cycle for BCD add/subtract...
#warning "Cycle counts are not accurate--!!! FIX !!!"
-static uint8 CPUCycles[256] = {
+static uint8_t CPUCycles[256] = {
+#if 0
7, 6, 1, 1, 5, 3, 5, 1, 3, 2, 2, 1, 6, 4, 6, 1,
2, 5, 5, 1, 5, 4, 6, 1, 2, 4, 2, 1, 6, 4, 6, 1,
6, 6, 1, 1, 3, 3, 5, 1, 4, 2, 2, 1, 4, 4, 6, 1,
2, 5, 5, 1, 1, 4, 6, 1, 2, 4, 3, 1, 1, 4, 6, 1,
2, 6, 1, 1, 3, 3, 5, 1, 2, 2, 2, 1, 4, 4, 6, 1,
2, 5, 5, 1, 1, 4, 6, 1, 2, 4, 4, 1, 1, 4, 6, 1 };
+#else
+ 7, 6, 2, 2, 5, 3, 5, 2, 3, 2, 2, 2, 6, 4, 6, 2,
+ 2, 5, 5, 2, 5, 4, 6, 2, 2, 4, 2, 2, 6, 4, 6, 2,
+ 6, 6, 2, 2, 3, 3, 5, 2, 4, 2, 2, 2, 4, 2, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 2, 2, 4, 4, 6, 2,
+ 6, 6, 2, 2, 3, 3, 5, 2, 3, 2, 2, 2, 3, 4, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 3, 2, 8, 4, 6, 2,
+ 6, 6, 2, 2, 3, 3, 5, 2, 4, 2, 2, 2, 6, 4, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 4, 2, 6, 4, 6, 2,
+ 2, 6, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 4, 4, 4, 2,
+ 2, 6, 5, 2, 4, 4, 4, 2, 2, 5, 2, 2, 4, 5, 5, 2,
+ 2, 6, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 4, 4, 4, 2,
+ 2, 5, 5, 2, 4, 4, 4, 2, 2, 4, 2, 2, 4, 4, 4, 2,
+ 2, 6, 2, 2, 3, 3, 5, 2, 2, 2, 2, 2, 4, 4, 5, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 3, 2, 4, 4, 6, 2,
+ 2, 6, 2, 2, 3, 3, 5, 2, 2, 2, 2, 2, 4, 4, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 4, 2, 4, 4, 6, 2 };
+#endif
+
+static uint8_t _6502Cycles[256] = {
+ 7, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6,
+ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 6, 7,
+ 6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 4, 2, 6, 6,
+ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 6, 7,
+ 6, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 3, 4, 6, 6,
+ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 6, 7,
+ 6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 6, 4, 6, 6,
+ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 6, 7,
+ 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4,
+ 2, 6, 2, 6, 4, 4, 4, 4, 2, 5, 2, 5, 5, 5, 5, 5,
+ 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4,
+ 2, 5, 2, 5, 4, 4, 4, 4, 2, 4, 2, 4, 4, 4, 4, 4,
+ 2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 5, 6,
+ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 6, 7,
+ 2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6,
+ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 6, 7 };
+
+static uint8_t _65C02Cycles[256] = {
+ 7, 6, 2, 2, 5, 3, 5, 2, 3, 2, 2, 2, 6, 4, 6, 2,
+ 2, 5, 5, 2, 5, 4, 6, 2, 2, 4, 2, 2, 6, 4, 6, 2,
+ 6, 6, 2, 2, 3, 3, 5, 2, 4, 2, 2, 2, 4, 2, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 2, 2, 4, 4, 6, 2,
+ 6, 6, 2, 2, 3, 3, 5, 2, 3, 2, 2, 2, 3, 4, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 3, 2, 8, 4, 6, 2,
+ 6, 6, 2, 2, 3, 3, 5, 2, 4, 2, 2, 2, 6, 4, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 4, 2, 6, 4, 6, 2,
+ 2, 6, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 4, 4, 4, 2,
+ 2, 6, 5, 2, 4, 4, 4, 2, 2, 5, 2, 2, 4, 5, 5, 2,
+ 2, 6, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 4, 4, 4, 2,
+ 2, 5, 5, 2, 4, 4, 4, 2, 2, 4, 2, 2, 4, 4, 4, 2,
+ 2, 6, 2, 2, 3, 3, 5, 2, 2, 2, 2, 2, 4, 4, 5, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 3, 2, 4, 4, 6, 2,
+ 2, 6, 2, 2, 3, 3, 5, 2, 2, 2, 2, 2, 4, 4, 6, 2,
+ 2, 5, 5, 2, 4, 4, 6, 2, 2, 4, 4, 2, 4, 4, 6, 2 };
+
+#if 0
+// ExtraCycles:
+// +1 if branch taken
+// +1 if page boundary crossed
+#define BRANCH_TAKEN { \
+ base = regs.pc; \
+ regs.pc += addr; \
+ if ((base ^ regs.pc) & 0xFF00) \
+ uExtraCycles=2; \
+ else \
+ uExtraCycles=1; \
+ }
+
+{
+ oldpc = regs.pc;
+ regs.pc += v;
+ if ((oldc ^ regs.pc) & 0xFF00)
+ regs.clock++;
+ regs.clock++;
+}
+#endif
+
+/*
+6502 cycles (includes illegal opcodes):
+
+ case 0x00: BRK CYC(7) break;
+ case 0x01: INDX ORA CYC(6) break;
+ case 0x02: INV HLT CYC(2) break;
+ case 0x03: INV INDX ASO CYC(8) break;
+ case 0x04: INV ZPG NOP CYC(3) break;
+ case 0x05: ZPG ORA CYC(3) break;
+ case 0x06: ZPG ASL_NMOS CYC(5) break;
+ case 0x07: INV ZPG ASO CYC(5) break;
+ case 0x08: PHP CYC(3) break;
+ case 0x09: IMM ORA CYC(2) break;
+ case 0x0A: ASLA CYC(2) break;
+ case 0x0B: INV IMM ANC CYC(2) break;
+ case 0x0C: INV ABSX NOP CYC(4) break;
+ case 0x0D: ABS ORA CYC(4) break;
+ case 0x0E: ABS ASL_NMOS CYC(6) break;
+ case 0x0F: INV ABS ASO CYC(6) break;
+ case 0x10: REL BPL CYC(2) break;
+ case 0x11: INDY ORA CYC(5) break;
+ case 0x12: INV HLT CYC(2) break;
+ case 0x13: INV INDY ASO CYC(8) break;
+ case 0x14: INV ZPGX NOP CYC(4) break;
+ case 0x15: ZPGX ORA CYC(4) break;
+ case 0x16: ZPGX ASL_NMOS CYC(6) break;
+ case 0x17: INV ZPGX ASO CYC(6) break;
+ case 0x18: CLC CYC(2) break;
+ case 0x19: ABSY ORA CYC(4) break;
+ case 0x1A: INV NOP CYC(2) break;
+ case 0x1B: INV ABSY ASO CYC(7) break;
+ case 0x1C: INV ABSX NOP CYC(4) break;
+ case 0x1D: ABSX ORA CYC(4) break;
+ case 0x1E: ABSX ASL_NMOS CYC(6) break;
+ case 0x1F: INV ABSX ASO CYC(7) break;
+ case 0x20: ABS JSR CYC(6) break;
+ case 0x21: INDX AND CYC(6) break;
+ case 0x22: INV HLT CYC(2) break;
+ case 0x23: INV INDX RLA CYC(8) break;
+ case 0x24: ZPG BIT CYC(3) break;
+ case 0x25: ZPG AND CYC(3) break;
+ case 0x26: ZPG ROL_NMOS CYC(5) break;
+ case 0x27: INV ZPG RLA CYC(5) break;
+ case 0x28: PLP CYC(4) break;
+ case 0x29: IMM AND CYC(2) break;
+ case 0x2A: ROLA CYC(2) break;
+ case 0x2B: INV IMM ANC CYC(2) break;
+ case 0x2C: ABS BIT CYC(4) break;
+ case 0x2D: ABS AND CYC(2) break;
+ case 0x2E: ABS ROL_NMOS CYC(6) break;
+ case 0x2F: INV ABS RLA CYC(6) break;
+ case 0x30: REL BMI CYC(2) break;
+ case 0x31: INDY AND CYC(5) break;
+ case 0x32: INV HLT CYC(2) break;
+ case 0x33: INV INDY RLA CYC(8) break;
+ case 0x34: INV ZPGX NOP CYC(4) break;
+ case 0x35: ZPGX AND CYC(4) break;
+ case 0x36: ZPGX ROL_NMOS CYC(6) break;
+ case 0x37: INV ZPGX RLA CYC(6) break;
+ case 0x38: SEC CYC(2) break;
+ case 0x39: ABSY AND CYC(4) break;
+ case 0x3A: INV NOP CYC(2) break;
+ case 0x3B: INV ABSY RLA CYC(7) break;
+ case 0x3C: INV ABSX NOP CYC(4) break;
+ case 0x3D: ABSX AND CYC(4) break;
+ case 0x3E: ABSX ROL_NMOS CYC(6) break;
+ case 0x3F: INV ABSX RLA CYC(7) break;
+ case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
+ case 0x41: INDX EOR CYC(6) break;
+ case 0x42: INV HLT CYC(2) break;
+ case 0x43: INV INDX LSE CYC(8) break;
+ case 0x44: INV ZPG NOP CYC(3) break;
+ case 0x45: ZPG EOR CYC(3) break;
+ case 0x46: ZPG LSR_NMOS CYC(5) break;
+ case 0x47: INV ZPG LSE CYC(5) break;
+ case 0x48: PHA CYC(3) break;
+ case 0x49: IMM EOR CYC(2) break;
+ case 0x4A: LSRA CYC(2) break;
+ case 0x4B: INV IMM ALR CYC(2) break;
+ case 0x4C: ABS JMP CYC(3) break;
+ case 0x4D: ABS EOR CYC(4) break;
+ case 0x4E: ABS LSR_NMOS CYC(6) break;
+ case 0x4F: INV ABS LSE CYC(6) break;
+ case 0x50: REL BVC CYC(2) break;
+ case 0x51: INDY EOR CYC(5) break;
+ case 0x52: INV HLT CYC(2) break;
+ case 0x53: INV INDY LSE CYC(8) break;
+ case 0x54: INV ZPGX NOP CYC(4) break;
+ case 0x55: ZPGX EOR CYC(4) break;
+ case 0x56: ZPGX LSR_NMOS CYC(6) break;
+ case 0x57: INV ZPGX LSE CYC(6) break;
+ case 0x58: CLI CYC(2) break;
+ case 0x59: ABSY EOR CYC(4) break;
+ case 0x5A: INV NOP CYC(2) break;
+ case 0x5B: INV ABSY LSE CYC(7) break;
+ case 0x5C: INV ABSX NOP CYC(4) break;
+ case 0x5D: ABSX EOR CYC(4) break;
+ case 0x5E: ABSX LSR_NMOS CYC(6) break;
+ case 0x5F: INV ABSX LSE CYC(7) break;
+ case 0x60: RTS CYC(6) break;
+ case 0x61: INDX ADC_NMOS CYC(6) break;
+ case 0x62: INV HLT CYC(2) break;
+ case 0x63: INV INDX RRA CYC(8) break;
+ case 0x64: INV ZPG NOP CYC(3) break;
+ case 0x65: ZPG ADC_NMOS CYC(3) break;
+ case 0x66: ZPG ROR_NMOS CYC(5) break;
+ case 0x67: INV ZPG RRA CYC(5) break;
+ case 0x68: PLA CYC(4) break;
+ case 0x69: IMM ADC_NMOS CYC(2) break;
+ case 0x6A: RORA CYC(2) break;
+ case 0x6B: INV IMM ARR CYC(2) break;
+ case 0x6C: IABSNMOS JMP CYC(6) break;
+ case 0x6D: ABS ADC_NMOS CYC(4) break;
+ case 0x6E: ABS ROR_NMOS CYC(6) break;
+ case 0x6F: INV ABS RRA CYC(6) break;
+ case 0x70: REL BVS CYC(2) break;
+ case 0x71: INDY ADC_NMOS CYC(5) break;
+ case 0x72: INV HLT CYC(2) break;
+ case 0x73: INV INDY RRA CYC(8) break;
+ case 0x74: INV ZPGX NOP CYC(4) break;
+ case 0x75: ZPGX ADC_NMOS CYC(4) break;
+ case 0x76: ZPGX ROR_NMOS CYC(6) break;
+ case 0x77: INV ZPGX RRA CYC(6) break;
+ case 0x78: SEI CYC(2) break;
+ case 0x79: ABSY ADC_NMOS CYC(4) break;
+ case 0x7A: INV NOP CYC(2) break;
+ case 0x7B: INV ABSY RRA CYC(7) break;
+ case 0x7C: INV ABSX NOP CYC(4) break;
+ case 0x7D: ABSX ADC_NMOS CYC(4) break;
+ case 0x7E: ABSX ROR_NMOS CYC(6) break;
+ case 0x7F: INV ABSX RRA CYC(7) break;
+ case 0x80: INV IMM NOP CYC(2) break;
+ case 0x81: INDX STA CYC(6) break;
+ case 0x82: INV IMM NOP CYC(2) break;
+ case 0x83: INV INDX AXS CYC(6) break;
+ case 0x84: ZPG STY CYC(3) break;
+ case 0x85: ZPG STA CYC(3) break;
+ case 0x86: ZPG STX CYC(3) break;
+ case 0x87: INV ZPG AXS CYC(3) break;
+ case 0x88: DEY CYC(2) break;
+ case 0x89: INV IMM NOP CYC(2) break;
+ case 0x8A: TXA CYC(2) break;
+ case 0x8B: INV IMM XAA CYC(2) break;
+ case 0x8C: ABS STY CYC(4) break;
+ case 0x8D: ABS STA CYC(4) break;
+ case 0x8E: ABS STX CYC(4) break;
+ case 0x8F: INV ABS AXS CYC(4) break;
+ case 0x90: REL BCC CYC(2) break;
+ case 0x91: INDY STA CYC(6) break;
+ case 0x92: INV HLT CYC(2) break;
+ case 0x93: INV INDY AXA CYC(6) break;
+ case 0x94: ZPGX STY CYC(4) break;
+ case 0x95: ZPGX STA CYC(4) break;
+ case 0x96: ZPGY STX CYC(4) break;
+ case 0x97: INV ZPGY AXS CYC(4) break;
+ case 0x98: TYA CYC(2) break;
+ case 0x99: ABSY STA CYC(5) break;
+ case 0x9A: TXS CYC(2) break;
+ case 0x9B: INV ABSY TAS CYC(5) break;
+ case 0x9C: INV ABSX SAY CYC(5) break;
+ case 0x9D: ABSX STA CYC(5) break;
+ case 0x9E: INV ABSY XAS CYC(5) break;
+ case 0x9F: INV ABSY AXA CYC(5) break;
+ case 0xA0: IMM LDY CYC(2) break;
+ case 0xA1: INDX LDA CYC(6) break;
+ case 0xA2: IMM LDX CYC(2) break;
+ case 0xA3: INV INDX LAX CYC(6) break;
+ case 0xA4: ZPG LDY CYC(3) break;
+ case 0xA5: ZPG LDA CYC(3) break;
+ case 0xA6: ZPG LDX CYC(3) break;
+ case 0xA7: INV ZPG LAX CYC(3) break;
+ case 0xA8: TAY CYC(2) break;
+ case 0xA9: IMM LDA CYC(2) break;
+ case 0xAA: TAX CYC(2) break;
+ case 0xAB: INV IMM OAL CYC(2) break;
+ case 0xAC: ABS LDY CYC(4) break;
+ case 0xAD: ABS LDA CYC(4) break;
+ case 0xAE: ABS LDX CYC(4) break;
+ case 0xAF: INV ABS LAX CYC(4) break;
+ case 0xB0: REL BCS CYC(2) break;
+ case 0xB1: INDY LDA CYC(5) break;
+ case 0xB2: INV HLT CYC(2) break;
+ case 0xB3: INV INDY LAX CYC(5) break;
+ case 0xB4: ZPGX LDY CYC(4) break;
+ case 0xB5: ZPGX LDA CYC(4) break;
+ case 0xB6: ZPGY LDX CYC(4) break;
+ case 0xB7: INV ZPGY LAX CYC(4) break;
+ case 0xB8: CLV CYC(2) break;
+ case 0xB9: ABSY LDA CYC(4) break;
+ case 0xBA: TSX CYC(2) break;
+ case 0xBB: INV ABSY LAS CYC(4) break;
+ case 0xBC: ABSX LDY CYC(4) break;
+ case 0xBD: ABSX LDA CYC(4) break;
+ case 0xBE: ABSY LDX CYC(4) break;
+ case 0xBF: INV ABSY LAX CYC(4) break;
+ case 0xC0: IMM CPY CYC(2) break;
+ case 0xC1: INDX CMP CYC(6) break;
+ case 0xC2: INV IMM NOP CYC(2) break;
+ case 0xC3: INV INDX DCM CYC(8) break;
+ case 0xC4: ZPG CPY CYC(3) break;
+ case 0xC5: ZPG CMP CYC(3) break;
+ case 0xC6: ZPG DEC_NMOS CYC(5) break;
+ case 0xC7: INV ZPG DCM CYC(5) break;
+ case 0xC8: INY CYC(2) break;
+ case 0xC9: IMM CMP CYC(2) break;
+ case 0xCA: DEX CYC(2) break;
+ case 0xCB: INV IMM SAX CYC(2) break;
+ case 0xCC: ABS CPY CYC(4) break;
+ case 0xCD: ABS CMP CYC(4) break;
+ case 0xCE: ABS DEC_NMOS CYC(5) break;
+ case 0xCF: INV ABS DCM CYC(6) break;
+ case 0xD0: REL BNE CYC(2) break;
+ case 0xD1: INDY CMP CYC(5) break;
+ case 0xD2: INV HLT CYC(2) break;
+ case 0xD3: INV INDY DCM CYC(8) break;
+ case 0xD4: INV ZPGX NOP CYC(4) break;
+ case 0xD5: ZPGX CMP CYC(4) break;
+ case 0xD6: ZPGX DEC_NMOS CYC(6) break;
+ case 0xD7: INV ZPGX DCM CYC(6) break;
+ case 0xD8: CLD CYC(2) break;
+ case 0xD9: ABSY CMP CYC(4) break;
+ case 0xDA: INV NOP CYC(2) break;
+ case 0xDB: INV ABSY DCM CYC(7) break;
+ case 0xDC: INV ABSX NOP CYC(4) break;
+ case 0xDD: ABSX CMP CYC(4) break;
+ case 0xDE: ABSX DEC_NMOS CYC(6) break;
+ case 0xDF: INV ABSX DCM CYC(7) break;
+ case 0xE0: IMM CPX CYC(2) break;
+ case 0xE1: INDX SBC_NMOS CYC(6) break;
+ case 0xE2: INV IMM NOP CYC(2) break;
+ case 0xE3: INV INDX INS CYC(8) break;
+ case 0xE4: ZPG CPX CYC(3) break;
+ case 0xE5: ZPG SBC_NMOS CYC(3) break;
+ case 0xE6: ZPG INC_NMOS CYC(5) break;
+ case 0xE7: INV ZPG INS CYC(5) break;
+ case 0xE8: INX CYC(2) break;
+ case 0xE9: IMM SBC_NMOS CYC(2) break;
+ case 0xEA: NOP CYC(2) break;
+ case 0xEB: INV IMM SBC_NMOS CYC(2) break;
+ case 0xEC: ABS CPX CYC(4) break;
+ case 0xED: ABS SBC_NMOS CYC(4) break;
+ case 0xEE: ABS INC_NMOS CYC(6) break;
+ case 0xEF: INV ABS INS CYC(6) break;
+ case 0xF0: REL BEQ CYC(2) break;
+ case 0xF1: INDY SBC_NMOS CYC(5) break;
+ case 0xF2: INV HLT CYC(2) break;
+ case 0xF3: INV INDY INS CYC(8) break;
+ case 0xF4: INV ZPGX NOP CYC(4) break;
+ case 0xF5: ZPGX SBC_NMOS CYC(4) break;
+ case 0xF6: ZPGX INC_NMOS CYC(6) break;
+ case 0xF7: INV ZPGX INS CYC(6) break;
+ case 0xF8: SED CYC(2) break;
+ case 0xF9: ABSY SBC_NMOS CYC(4) break;
+ case 0xFA: INV NOP CYC(2) break;
+ case 0xFB: INV ABSY INS CYC(7) break;
+ case 0xFC: INV ABSX NOP CYC(4) break;
+ case 0xFD: ABSX SBC_NMOS CYC(4) break;
+ case 0xFE: ABSX INC_NMOS CYC(6) break;
+ case 0xFF: INV ABSX INS CYC(7) break;
+
+
+65C02 opcodes: (all illegal are NOP, but have cycle counts)
+
+ case 0x00: BRK CYC(7) break;
+ case 0x01: INDX ORA CYC(6) break;
+ case 0x02: INV IMM NOP CYC(2) break;
+ case 0x03: INV NOP CYC(2) break;
+ case 0x04: ZPG TSB CYC(5) break;
+ case 0x05: ZPG ORA CYC(3) break;
+ case 0x06: ZPG ASL_CMOS CYC(5) break;
+ case 0x07: INV NOP CYC(2) break;
+ case 0x08: PHP CYC(3) break;
+ case 0x09: IMM ORA CYC(2) break;
+ case 0x0A: ASLA CYC(2) break;
+ case 0x0B: INV NOP CYC(2) break;
+ case 0x0C: ABS TSB CYC(6) break;
+ case 0x0D: ABS ORA CYC(4) break;
+ case 0x0E: ABS ASL_CMOS CYC(6) break;
+ case 0x0F: INV NOP CYC(2) break;
+ case 0x10: REL BPL CYC(2) break;
+ case 0x11: INDY ORA CYC(5) break;
+ case 0x12: IZPG ORA CYC(5) break;
+ case 0x13: INV NOP CYC(2) break;
+ case 0x14: ZPG TRB CYC(5) break;
+ case 0x15: ZPGX ORA CYC(4) break;
+ case 0x16: ZPGX ASL_CMOS CYC(6) break;
+ case 0x17: INV NOP CYC(2) break;
+ case 0x18: CLC CYC(2) break;
+ case 0x19: ABSY ORA CYC(4) break;
+ case 0x1A: INA CYC(2) break;
+ case 0x1B: INV NOP CYC(2) break;
+ case 0x1C: ABS TRB CYC(6) break;
+ case 0x1D: ABSX ORA CYC(4) break;
+ case 0x1E: ABSX ASL_CMOS CYC(6) break;
+ case 0x1F: INV NOP CYC(2) break;
+ case 0x20: ABS JSR CYC(6) break;
+ case 0x21: INDX AND CYC(6) break;
+ case 0x22: INV IMM NOP CYC(2) break;
+ case 0x23: INV NOP CYC(2) break;
+ case 0x24: ZPG BIT CYC(3) break;
+ case 0x25: ZPG AND CYC(3) break;
+ case 0x26: ZPG ROL_CMOS CYC(5) break;
+ case 0x27: INV NOP CYC(2) break;
+ case 0x28: PLP CYC(4) break;
+ case 0x29: IMM AND CYC(2) break;
+ case 0x2A: ROLA CYC(2) break;
+ case 0x2B: INV NOP CYC(2) break;
+ case 0x2C: ABS BIT CYC(4) break;
+ case 0x2D: ABS AND CYC(2) break;
+ case 0x2E: ABS ROL_CMOS CYC(6) break;
+ case 0x2F: INV NOP CYC(2) break;
+ case 0x30: REL BMI CYC(2) break;
+ case 0x31: INDY AND CYC(5) break;
+ case 0x32: IZPG AND CYC(5) break;
+ case 0x33: INV NOP CYC(2) break;
+ case 0x34: ZPGX BIT CYC(4) break;
+ case 0x35: ZPGX AND CYC(4) break;
+ case 0x36: ZPGX ROL_CMOS CYC(6) break;
+ case 0x37: INV NOP CYC(2) break;
+ case 0x38: SEC CYC(2) break;
+ case 0x39: ABSY AND CYC(4) break;
+ case 0x3A: DEA CYC(2) break;
+ case 0x3B: INV NOP CYC(2) break;
+ case 0x3C: ABSX BIT CYC(4) break;
+ case 0x3D: ABSX AND CYC(4) break;
+ case 0x3E: ABSX ROL_CMOS CYC(6) break;
+ case 0x3F: INV NOP CYC(2) break;
+ case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
+ case 0x41: INDX EOR CYC(6) break;
+ case 0x42: INV IMM NOP CYC(2) break;
+ case 0x43: INV NOP CYC(2) break;
+ case 0x44: INV ZPG NOP CYC(3) break;
+ case 0x45: ZPG EOR CYC(3) break;
+ case 0x46: ZPG LSR_CMOS CYC(5) break;
+ case 0x47: INV NOP CYC(2) break;
+ case 0x48: PHA CYC(3) break;
+ case 0x49: IMM EOR CYC(2) break;
+ case 0x4A: LSRA CYC(2) break;
+ case 0x4B: INV NOP CYC(2) break;
+ case 0x4C: ABS JMP CYC(3) break;
+ case 0x4D: ABS EOR CYC(4) break;
+ case 0x4E: ABS LSR_CMOS CYC(6) break;
+ case 0x4F: INV NOP CYC(2) break;
+ case 0x50: REL BVC CYC(2) break;
+ case 0x51: INDY EOR CYC(5) break;
+ case 0x52: IZPG EOR CYC(5) break;
+ case 0x53: INV NOP CYC(2) break;
+ case 0x54: INV ZPGX NOP CYC(4) break;
+ case 0x55: ZPGX EOR CYC(4) break;
+ case 0x56: ZPGX LSR_CMOS CYC(6) break;
+ case 0x57: INV NOP CYC(2) break;
+ case 0x58: CLI CYC(2) break;
+ case 0x59: ABSY EOR CYC(4) break;
+ case 0x5A: PHY CYC(3) break;
+ case 0x5B: INV NOP CYC(2) break;
+ case 0x5C: INV ABSX NOP CYC(8) break;
+ case 0x5D: ABSX EOR CYC(4) break;
+ case 0x5E: ABSX LSR_CMOS CYC(6) break;
+ case 0x5F: INV NOP CYC(2) break;
+ case 0x60: RTS CYC(6) break;
+ case 0x61: INDX ADC_CMOS CYC(6) break;
+ case 0x62: INV IMM NOP CYC(2) break;
+ case 0x63: INV NOP CYC(2) break;
+ case 0x64: ZPG STZ CYC(3) break;
+ case 0x65: ZPG ADC_CMOS CYC(3) break;
+ case 0x66: ZPG ROR_CMOS CYC(5) break;
+ case 0x67: INV NOP CYC(2) break;
+ case 0x68: PLA CYC(4) break;
+ case 0x69: IMM ADC_CMOS CYC(2) break;
+ case 0x6A: RORA CYC(2) break;
+ case 0x6B: INV NOP CYC(2) break;
+ case 0x6C: IABSCMOS JMP CYC(6) break;
+ case 0x6D: ABS ADC_CMOS CYC(4) break;
+ case 0x6E: ABS ROR_CMOS CYC(6) break;
+ case 0x6F: INV NOP CYC(2) break;
+ case 0x70: REL BVS CYC(2) break;
+ case 0x71: INDY ADC_CMOS CYC(5) break;
+ case 0x72: IZPG ADC_CMOS CYC(5) break;
+ case 0x73: INV NOP CYC(2) break;
+ case 0x74: ZPGX STZ CYC(4) break;
+ case 0x75: ZPGX ADC_CMOS CYC(4) break;
+ case 0x76: ZPGX ROR_CMOS CYC(6) break;
+ case 0x77: INV NOP CYC(2) break;
+ case 0x78: SEI CYC(2) break;
+ case 0x79: ABSY ADC_CMOS CYC(4) break;
+ case 0x7A: PLY CYC(4) break;
+ case 0x7B: INV NOP CYC(2) break;
+ case 0x7C: IABSX JMP CYC(6) break;
+ case 0x7D: ABSX ADC_CMOS CYC(4) break;
+ case 0x7E: ABSX ROR_CMOS CYC(6) break;
+ case 0x7F: INV NOP CYC(2) break;
+ case 0x80: REL BRA CYC(2) break;
+ case 0x81: INDX STA CYC(6) break;
+ case 0x82: INV IMM NOP CYC(2) break;
+ case 0x83: INV NOP CYC(2) break;
+ case 0x84: ZPG STY CYC(3) break;
+ case 0x85: ZPG STA CYC(3) break;
+ case 0x86: ZPG STX CYC(3) break;
+ case 0x87: INV NOP CYC(2) break;
+ case 0x88: DEY CYC(2) break;
+ case 0x89: IMM BITI CYC(2) break;
+ case 0x8A: TXA CYC(2) break;
+ case 0x8B: INV NOP CYC(2) break;
+ case 0x8C: ABS STY CYC(4) break;
+ case 0x8D: ABS STA CYC(4) break;
+ case 0x8E: ABS STX CYC(4) break;
+ case 0x8F: INV NOP CYC(2) break;
+ case 0x90: REL BCC CYC(2) break;
+ case 0x91: INDY STA CYC(6) break;
+ case 0x92: IZPG STA CYC(5) break;
+ case 0x93: INV NOP CYC(2) break;
+ case 0x94: ZPGX STY CYC(4) break;
+ case 0x95: ZPGX STA CYC(4) break;
+ case 0x96: ZPGY STX CYC(4) break;
+ case 0x97: INV NOP CYC(2) break;
+ case 0x98: TYA CYC(2) break;
+ case 0x99: ABSY STA CYC(5) break;
+ case 0x9A: TXS CYC(2) break;
+ case 0x9B: INV NOP CYC(2) break;
+ case 0x9C: ABS STZ CYC(4) break;
+ case 0x9D: ABSX STA CYC(5) break;
+ case 0x9E: ABSX STZ CYC(5) break;
+ case 0x9F: INV NOP CYC(2) break;
+ case 0xA0: IMM LDY CYC(2) break;
+ case 0xA1: INDX LDA CYC(6) break;
+ case 0xA2: IMM LDX CYC(2) break;
+ case 0xA3: INV NOP CYC(2) break;
+ case 0xA4: ZPG LDY CYC(3) break;
+ case 0xA5: ZPG LDA CYC(3) break;
+ case 0xA6: ZPG LDX CYC(3) break;
+ case 0xA7: INV NOP CYC(2) break;
+ case 0xA8: TAY CYC(2) break;
+ case 0xA9: IMM LDA CYC(2) break;
+ case 0xAA: TAX CYC(2) break;
+ case 0xAB: INV NOP CYC(2) break;
+ case 0xAC: ABS LDY CYC(4) break;
+ case 0xAD: ABS LDA CYC(4) break;
+ case 0xAE: ABS LDX CYC(4) break;
+ case 0xAF: INV NOP CYC(2) break;
+ case 0xB0: REL BCS CYC(2) break;
+ case 0xB1: INDY LDA CYC(5) break;
+ case 0xB2: IZPG LDA CYC(5) break;
+ case 0xB3: INV NOP CYC(2) break;
+ case 0xB4: ZPGX LDY CYC(4) break;
+ case 0xB5: ZPGX LDA CYC(4) break;
+ case 0xB6: ZPGY LDX CYC(4) break;
+ case 0xB7: INV NOP CYC(2) break;
+ case 0xB8: CLV CYC(2) break;
+ case 0xB9: ABSY LDA CYC(4) break;
+ case 0xBA: TSX CYC(2) break;
+ case 0xBB: INV NOP CYC(2) break;
+ case 0xBC: ABSX LDY CYC(4) break;
+ case 0xBD: ABSX LDA CYC(4) break;
+ case 0xBE: ABSY LDX CYC(4) break;
+ case 0xBF: INV NOP CYC(2) break;
+ case 0xC0: IMM CPY CYC(2) break;
+ case 0xC1: INDX CMP CYC(6) break;
+ case 0xC2: INV IMM NOP CYC(2) break;
+ case 0xC3: INV NOP CYC(2) break;
+ case 0xC4: ZPG CPY CYC(3) break;
+ case 0xC5: ZPG CMP CYC(3) break;
+ case 0xC6: ZPG DEC_CMOS CYC(5) break;
+ case 0xC7: INV NOP CYC(2) break;
+ case 0xC8: INY CYC(2) break;
+ case 0xC9: IMM CMP CYC(2) break;
+ case 0xCA: DEX CYC(2) break;
+ case 0xCB: INV NOP CYC(2) break;
+ case 0xCC: ABS CPY CYC(4) break;
+ case 0xCD: ABS CMP CYC(4) break;
+ case 0xCE: ABS DEC_CMOS CYC(5) break;
+ case 0xCF: INV NOP CYC(2) break;
+ case 0xD0: REL BNE CYC(2) break;
+ case 0xD1: INDY CMP CYC(5) break;
+ case 0xD2: IZPG CMP CYC(5) break;
+ case 0xD3: INV NOP CYC(2) break;
+ case 0xD4: INV ZPGX NOP CYC(4) break;
+ case 0xD5: ZPGX CMP CYC(4) break;
+ case 0xD6: ZPGX DEC_CMOS CYC(6) break;
+ case 0xD7: INV NOP CYC(2) break;
+ case 0xD8: CLD CYC(2) break;
+ case 0xD9: ABSY CMP CYC(4) break;
+ case 0xDA: PHX CYC(3) break;
+ case 0xDB: INV NOP CYC(2) break;
+ case 0xDC: INV ABSX NOP CYC(4) break;
+ case 0xDD: ABSX CMP CYC(4) break;
+ case 0xDE: ABSX DEC_CMOS CYC(6) break;
+ case 0xDF: INV NOP CYC(2) break;
+ case 0xE0: IMM CPX CYC(2) break;
+ case 0xE1: INDX SBC_CMOS CYC(6) break;
+ case 0xE2: INV IMM NOP CYC(2) break;
+ case 0xE3: INV NOP CYC(2) break;
+ case 0xE4: ZPG CPX CYC(3) break;
+ case 0xE5: ZPG SBC_CMOS CYC(3) break;
+ case 0xE6: ZPG INC_CMOS CYC(5) break;
+ case 0xE7: INV NOP CYC(2) break;
+ case 0xE8: INX CYC(2) break;
+ case 0xE9: IMM SBC_CMOS CYC(2) break;
+ case 0xEA: NOP CYC(2) break;
+ case 0xEB: INV NOP CYC(2) break;
+ case 0xEC: ABS CPX CYC(4) break;
+ case 0xED: ABS SBC_CMOS CYC(4) break;
+ case 0xEE: ABS INC_CMOS CYC(6) break;
+ case 0xEF: INV NOP CYC(2) break;
+ case 0xF0: REL BEQ CYC(2) break;
+ case 0xF1: INDY SBC_CMOS CYC(5) break;
+ case 0xF2: IZPG SBC_CMOS CYC(5) break;
+ case 0xF3: INV NOP CYC(2) break;
+ case 0xF4: INV ZPGX NOP CYC(4) break;
+ case 0xF5: ZPGX SBC_CMOS CYC(4) break;
+ case 0xF6: ZPGX INC_CMOS CYC(6) break;
+ case 0xF7: INV NOP CYC(2) break;
+ case 0xF8: SED CYC(2) break;
+ case 0xF9: ABSY SBC_CMOS CYC(4) break;
+ case 0xFA: PLX CYC(4) break;
+ case 0xFB: INV NOP CYC(2) break;
+ case 0xFC: INV ABSX NOP CYC(4) break;
+ case 0xFD: ABSX SBC_CMOS CYC(4) break;
+ case 0xFE: ABSX INC_CMOS CYC(6) break;
+ case 0xFF: INV NOP CYC(2) break;
+*/
// Private function prototypes
-static uint16 RdMemW(uint16);
-static uint16 FetchMemW(uint16 addr);
+static uint16_t RdMemW(uint16_t);
+static uint16_t FetchMemW(uint16_t addr);
//
-// Read a uint16 out of 65C02 memory (big endian format)
+// Read a uint16_t out of 65C02 memory (big endian format)
//
-static inline uint16 RdMemW(uint16 address)
+static inline uint16_t RdMemW(uint16_t address)
{
- return (uint16)(regs.RdMem(address + 1) << 8) | regs.RdMem(address + 0);
+ return (uint16_t)(regs.RdMem(address + 1) << 8) | regs.RdMem(address + 0);
}
//
-// Read a uint16 out of 65C02 memory (big endian format) and increment PC
+// Read a uint16_t out of 65C02 memory (big endian format) and increment PC
//
-static inline uint16 FetchMemW(uint16 address)
+static inline uint16_t FetchMemW(uint16_t address)
{
regs.pc += 2;
- return (uint16)(regs.RdMem(address + 1) << 8) | regs.RdMem(address + 0);
+ return (uint16_t)(regs.RdMem(address + 1) << 8) | regs.RdMem(address + 0);
}
//This is non-optimal, but it works--optimize later. :-)
#define OP_ADC_HANDLER(m) \
- uint16 sum = (uint16)regs.a + (m) + (uint16)(regs.cc & FLAG_C); \
+ uint16_t sum = (uint16_t)regs.a + (m) + (uint16_t)(regs.cc & FLAG_C); \
\
if (regs.cc & FLAG_D) \
{ \
static void Op69(void) // ADC #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_ADC_HANDLER(m);
}
static void Op65(void) // ADC ZP
{
- uint16 m = READ_ZP;
+ uint16_t m = READ_ZP;
OP_ADC_HANDLER(m);
}
static void Op75(void) // ADC ZP, X
{
- uint16 m = READ_ZP_X;
+ uint16_t m = READ_ZP_X;
OP_ADC_HANDLER(m);
}
static void Op6D(void) // ADC ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_ADC_HANDLER(m);
}
static void Op7D(void) // ADC ABS, X
{
- uint16 m = READ_ABS_X;
+ uint16_t m = READ_ABS_X;
OP_ADC_HANDLER(m);
}
static void Op79(void) // ADC ABS, Y
{
- uint16 m = READ_ABS_Y;
+ uint16_t m = READ_ABS_Y;
OP_ADC_HANDLER(m);
}
static void Op61(void) // ADC (ZP, X)
{
- uint16 m = READ_IND_ZP_X;
+ uint16_t m = READ_IND_ZP_X;
OP_ADC_HANDLER(m);
}
static void Op71(void) // ADC (ZP), Y
{
- uint16 m = READ_IND_ZP_Y;
+ uint16_t m = READ_IND_ZP_Y;
OP_ADC_HANDLER(m);
}
static void Op72(void) // ADC (ZP)
{
- uint16 m = READ_IND_ZP;
+ uint16_t m = READ_IND_ZP;
OP_ADC_HANDLER(m);
}
static void Op29(void) // AND #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_AND_HANDLER(m);
}
static void Op25(void) // AND ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_AND_HANDLER(m);
}
static void Op35(void) // AND ZP, X
{
- uint8 m = READ_ZP_X;
+ uint8_t m = READ_ZP_X;
OP_AND_HANDLER(m);
}
static void Op2D(void) // AND ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_AND_HANDLER(m);
}
static void Op3D(void) // AND ABS, X
{
- uint8 m = READ_ABS_X;
+ uint8_t m = READ_ABS_X;
OP_AND_HANDLER(m);
}
static void Op39(void) // AND ABS, Y
{
- uint8 m = READ_ABS_Y;
+ uint8_t m = READ_ABS_Y;
OP_AND_HANDLER(m);
}
static void Op21(void) // AND (ZP, X)
{
- uint8 m = READ_IND_ZP_X;
+ uint8_t m = READ_IND_ZP_X;
OP_AND_HANDLER(m);
}
static void Op31(void) // AND (ZP), Y
{
- uint8 m = READ_IND_ZP_Y;
+ uint8_t m = READ_IND_ZP_Y;
OP_AND_HANDLER(m);
}
static void Op32(void) // AND (ZP)
{
- uint8 m = READ_IND_ZP;
+ uint8_t m = READ_IND_ZP;
OP_AND_HANDLER(m);
}
/*static void Op78(void) // LSL ABS
{
- uint8 tmp; uint16 addr;
+ uint8_t tmp; uint16_t addr;
addr = FetchW();
tmp = regs.RdMem(addr);
(tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into Carry
static void Op06(void) // ASL ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op16(void) // ASL ZP, X
{
- uint8 m;
+ uint8_t m;
READ_ZP_X_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op0E(void) // ASL ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op1E(void) // ASL ABS, X
{
- uint8 m;
+ uint8_t m;
READ_ABS_X_WB(m);
OP_ASL_HANDLER(m);
WRITE_BACK(m);
static void Op0F(void) // BBR0
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x01))
regs.pc += m;
static void Op1F(void) // BBR1
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x02))
regs.pc += m;
static void Op2F(void) // BBR2
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x04))
regs.pc += m;
static void Op3F(void) // BBR3
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x08))
regs.pc += m;
static void Op4F(void) // BBR4
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x10))
regs.pc += m;
static void Op5F(void) // BBR5
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x20))
regs.pc += m;
static void Op6F(void) // BBR6
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x40))
regs.pc += m;
static void Op7F(void) // BBR7
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.a & 0x80))
regs.pc += m;
static void Op8F(void) // BBS0
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x01)
regs.pc += m;
static void Op9F(void) // BBS1
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x02)
regs.pc += m;
static void OpAF(void) // BBS2
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x04)
regs.pc += m;
static void OpBF(void) // BBS3
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x08)
regs.pc += m;
static void OpCF(void) // BBS4
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x10)
regs.pc += m;
static void OpDF(void) // BBS5
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x20)
regs.pc += m;
static void OpEF(void) // BBS6
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x40)
regs.pc += m;
static void OpFF(void) // BBS7
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.a & 0x80)
regs.pc += m;
BEQ Relative BEQ Oper F0 2 2
*/
+// Branch taken adds a cycle, crossing page adds one more
+
+#define HANDLE_BRANCH_TAKEN(m) \
+{ \
+ uint16_t oldpc = regs.pc; \
+ regs.pc += m; \
+ regs.clock++; \
+ if ((oldpc ^ regs.pc) & 0xFF00) \
+ regs.clock++; \
+}
+
// Branch opcodes
static void Op90(void) // BCC
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.cc & FLAG_C))
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
}
static void OpB0(void) // BCS
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.cc & FLAG_C)
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
}
static void OpF0(void) // BEQ
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.cc & FLAG_Z)
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
}
/*
Z flag is set appropriately. */
#define OP_BIT_HANDLER(m) \
- int8 result = regs.a & (m); \
+ int8_t result = regs.a & (m); \
regs.cc &= ~(FLAG_N | FLAG_V); \
regs.cc |= ((m) & 0xC0); \
SET_Z(result)
static void Op89(void) // BIT #
{
- int8 m = READ_IMM;
- int8 result = regs.a & m;
+ int8_t m = READ_IMM;
+ int8_t result = regs.a & m;
SET_Z(result);
}
static void Op24(void) // BIT ZP
{
- int8 m = READ_ZP;
+ int8_t m = READ_ZP;
OP_BIT_HANDLER(m);
}
static void Op34(void) // BIT ZP, X
{
- uint8 m = READ_ZP_X;
+ uint8_t m = READ_ZP_X;
OP_BIT_HANDLER(m);
}
static void Op2C(void) // BIT ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_BIT_HANDLER(m);
}
static void Op3C(void) // BIT ABS, X
{
- uint8 m = READ_ABS_X;
+ uint8_t m = READ_ABS_X;
OP_BIT_HANDLER(m);
}
static void Op30(void) // BMI
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.cc & FLAG_N)
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
+// regs.pc += m;
}
static void OpD0(void) // BNE
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.cc & FLAG_Z))
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
+// regs.pc += m;
}
static void Op10(void) // BPL
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.cc & FLAG_N))
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
+// regs.pc += m;
}
static void Op80(void) // BRA
{
- int16 m = (int16)(int8)READ_IMM;
- regs.pc += m;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
+ HANDLE_BRANCH_TAKEN(m)
+// regs.pc += m;
}
/*
static void Op50(void) // BVC
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (!(regs.cc & FLAG_V))
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
+// regs.pc += m;
}
static void Op70(void) // BVS
{
- int16 m = (int16)(int8)READ_IMM;
+ int16_t m = (int16_t)(int8_t)READ_IMM;
if (regs.cc & FLAG_V)
- regs.pc += m;
+ HANDLE_BRANCH_TAKEN(m)
+// regs.pc += m;
}
/*
*/
#define OP_CMP_HANDLER(m) \
- uint8 result = regs.a - (m); \
+ uint8_t result = regs.a - (m); \
SET_ZNC_CMP(m, regs.a, result)
static void OpC9(void) // CMP #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_CMP_HANDLER(m);
}
static void OpC5(void) // CMP ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_CMP_HANDLER(m);
}
static void OpD5(void) // CMP ZP, X
{
- uint8 m = READ_ZP_X;
+ uint8_t m = READ_ZP_X;
OP_CMP_HANDLER(m);
}
static void OpCD(void) // CMP ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_CMP_HANDLER(m);
}
static void OpDD(void) // CMP ABS, X
{
- uint8 m = READ_ABS_X;
+ uint8_t m = READ_ABS_X;
OP_CMP_HANDLER(m);
}
static void OpD9(void) // CMP ABS, Y
{
- uint8 m = READ_ABS_Y;
+ uint8_t m = READ_ABS_Y;
OP_CMP_HANDLER(m);
}
static void OpC1(void) // CMP (ZP, X)
{
- uint8 m = READ_IND_ZP_X;
+ uint8_t m = READ_IND_ZP_X;
OP_CMP_HANDLER(m);
}
static void OpD1(void) // CMP (ZP), Y
{
- uint8 m = READ_IND_ZP_Y;
+ uint8_t m = READ_IND_ZP_Y;
OP_CMP_HANDLER(m);
}
static void OpD2(void) // CMP (ZP)
{
- uint8 m = READ_IND_ZP;
+ uint8_t m = READ_IND_ZP;
OP_CMP_HANDLER(m);
}
// CPX opcodes
#define OP_CPX_HANDLER(m) \
- uint8 result = regs.x - (m); \
+ uint8_t result = regs.x - (m); \
SET_ZNC_CMP(m, regs.x, result)
static void OpE0(void) // CPX #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_CPX_HANDLER(m);
}
static void OpE4(void) // CPX ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_CPX_HANDLER(m);
}
static void OpEC(void) // CPX ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_CPX_HANDLER(m);
}
// CPY opcodes
#define OP_CPY_HANDLER(m) \
- uint8 result = regs.y - (m); \
+ uint8_t result = regs.y - (m); \
SET_ZNC_CMP(m, regs.y, result)
static void OpC0(void) // CPY #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_CPY_HANDLER(m);
}
static void OpC4(void) // CPY ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_CPY_HANDLER(m);
}
static void OpCC(void) // CPY ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_CPY_HANDLER(m);
}
static void OpC6(void) // DEC ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void OpD6(void) // DEC ZP, X
{
- uint8 m;
+ uint8_t m;
READ_ZP_X_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void OpCE(void) // DEC ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void OpDE(void) // DEC ABS, X
{
- uint8 m;
+ uint8_t m;
READ_ABS_X_WB(m);
OP_DEC_HANDLER(m);
WRITE_BACK(m);
static void Op49(void) // EOR #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_EOR_HANDLER(m);
}
static void Op45(void) // EOR ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_EOR_HANDLER(m);
}
static void Op55(void) // EOR ZP, X
{
- uint8 m = READ_ZP_X;
+ uint8_t m = READ_ZP_X;
OP_EOR_HANDLER(m);
}
static void Op4D(void) // EOR ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_EOR_HANDLER(m);
}
static void Op5D(void) // EOR ABS, X
{
- uint8 m = READ_ABS_X;
+ uint8_t m = READ_ABS_X;
OP_EOR_HANDLER(m);
}
static void Op59(void) // EOR ABS, Y
{
- uint8 m = READ_ABS_Y;
+ uint8_t m = READ_ABS_Y;
OP_EOR_HANDLER(m);
}
static void Op41(void) // EOR (ZP, X)
{
- uint8 m = READ_IND_ZP_X;
+ uint8_t m = READ_IND_ZP_X;
OP_EOR_HANDLER(m);
}
static void Op51(void) // EOR (ZP), Y
{
- uint8 m = READ_IND_ZP_Y;
+ uint8_t m = READ_IND_ZP_Y;
OP_EOR_HANDLER(m);
}
static void Op52(void) // EOR (ZP)
{
- uint8 m = READ_IND_ZP;
+ uint8_t m = READ_IND_ZP;
OP_EOR_HANDLER(m);
}
static void OpE6(void) // INC ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void OpF6(void) // INC ZP, X
{
- uint8 m;
+ uint8_t m;
READ_ZP_X_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void OpEE(void) // INC ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void OpFE(void) // INC ABS, X
{
- uint8 m;
+ uint8_t m;
READ_ABS_X_WB(m);
OP_INC_HANDLER(m);
WRITE_BACK(m);
static void Op6C(void) // JMP (ABS)
{
-// uint16 addr = RdMemW(regs.pc);
+// uint16_t addr = RdMemW(regs.pc);
//#ifdef __DEBUG__
//WriteLog("\n[JMP ABS]: addr fetched = %04X, bytes at %04X = %02X %02X (RdMemw=%04X)\n",
// addr, addr, regs.RdMem(addr), regs.RdMem(addr+1), RdMemW(addr));
//This is not jumping to the correct address... !!! FIX !!! [DONE]
static void Op20(void) // JSR
{
- uint16 addr = RdMemW(regs.pc);
+ uint16_t addr = RdMemW(regs.pc);
regs.pc++; // Since it pushes return address - 1...
regs.WrMem(0x0100 + regs.sp--, regs.pc >> 8);
regs.WrMem(0x0100 + regs.sp--, regs.pc & 0xFF);
static void OpA9(void) // LDA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_LDA_HANDLER(m);
}
static void OpA5(void) // LDA ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_LDA_HANDLER(m);
}
static void OpB5(void) // LDA ZP, X
{
- uint8 m = READ_ZP_X;
+ uint8_t m = READ_ZP_X;
OP_LDA_HANDLER(m);
}
static void OpAD(void) // LDA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_LDA_HANDLER(m);
}
static void OpBD(void) // LDA ABS, X
{
- uint8 m = READ_ABS_X;
+ uint8_t m = READ_ABS_X;
OP_LDA_HANDLER(m);
}
static void OpB9(void) // LDA ABS, Y
{
- uint8 m = READ_ABS_Y;
+ uint8_t m = READ_ABS_Y;
OP_LDA_HANDLER(m);
}
static void OpA1(void) // LDA (ZP, X)
{
- uint8 m = READ_IND_ZP_X;
+ uint8_t m = READ_IND_ZP_X;
OP_LDA_HANDLER(m);
}
static void OpB1(void) // LDA (ZP), Y
{
- uint8 m = READ_IND_ZP_Y;
+ uint8_t m = READ_IND_ZP_Y;
OP_LDA_HANDLER(m);
}
static void OpB2(void) // LDA (ZP)
{
- uint8 m = READ_IND_ZP;
+ uint8_t m = READ_IND_ZP;
OP_LDA_HANDLER(m);
}
static void OpA2(void) // LDX #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_LDX_HANDLER(m);
}
static void OpA6(void) // LDX ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_LDX_HANDLER(m);
}
static void OpB6(void) // LDX ZP, Y
{
- uint8 m = READ_ZP_Y;
+ uint8_t m = READ_ZP_Y;
OP_LDX_HANDLER(m);
}
static void OpAE(void) // LDX ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_LDX_HANDLER(m);
}
static void OpBE(void) // LDX ABS, Y
{
- uint8 m = READ_ABS_Y;
+ uint8_t m = READ_ABS_Y;
OP_LDX_HANDLER(m);
}
static void OpA0(void) // LDY #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_LDY_HANDLER(m);
}
static void OpA4(void) // LDY ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_LDY_HANDLER(m);
}
static void OpB4(void) // LDY ZP, X
{
- uint8 m = READ_ZP_X;
+ uint8_t m = READ_ZP_X;
OP_LDY_HANDLER(m);
}
static void OpAC(void) // LDY ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_LDY_HANDLER(m);
}
static void OpBC(void) // LDY ABS, X
{
- uint8 m = READ_ABS_X;
+ uint8_t m = READ_ABS_X;
OP_LDY_HANDLER(m);
}
static void Op46(void) // LSR ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op56(void) // LSR ZP, X
{
- uint8 m;
+ uint8_t m;
READ_ZP_X_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op4E(void) // LSR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op5E(void) // LSR ABS, X
{
- uint8 m;
+ uint8_t m;
READ_ABS_X_WB(m);
OP_LSR_HANDLER(m);
WRITE_BACK(m);
static void Op09(void) // ORA #
{
- uint8 m = READ_IMM;
+ uint8_t m = READ_IMM;
OP_ORA_HANDLER(m);
}
static void Op05(void) // ORA ZP
{
- uint8 m = READ_ZP;
+ uint8_t m = READ_ZP;
OP_ORA_HANDLER(m);
}
static void Op15(void) // ORA ZP, X
{
- uint8 m = READ_ZP_X;
+ uint8_t m = READ_ZP_X;
OP_ORA_HANDLER(m);
}
static void Op0D(void) // ORA ABS
{
- uint8 m = READ_ABS;
+ uint8_t m = READ_ABS;
OP_ORA_HANDLER(m);
}
static void Op1D(void) // ORA ABS, X
{
- uint8 m = READ_ABS_X;
+ uint8_t m = READ_ABS_X;
OP_ORA_HANDLER(m);
}
static void Op19(void) // ORA ABS, Y
{
- uint8 m = READ_ABS_Y;
+ uint8_t m = READ_ABS_Y;
OP_ORA_HANDLER(m);
}
static void Op01(void) // ORA (ZP, X)
{
- uint8 m = READ_IND_ZP_X;
+ uint8_t m = READ_IND_ZP_X;
OP_ORA_HANDLER(m);
}
static void Op11(void) // ORA (ZP), Y
{
- uint8 m = READ_IND_ZP_Y;
+ uint8_t m = READ_IND_ZP_Y;
OP_ORA_HANDLER(m);
}
static void Op12(void) // ORA (ZP)
{
- uint8 m = READ_IND_ZP;
+ uint8_t m = READ_IND_ZP;
OP_ORA_HANDLER(m);
}
static void Op07(void) // RMB0 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0xFE;
WRITE_BACK(m);
static void Op17(void) // RMB1 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0xFD;
WRITE_BACK(m);
static void Op27(void) // RMB2 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0xFB;
WRITE_BACK(m);
static void Op37(void) // RMB3 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0xF7;
WRITE_BACK(m);
static void Op47(void) // RMB4 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0xEF;
WRITE_BACK(m);
static void Op57(void) // RMB5 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0xDF;
WRITE_BACK(m);
static void Op67(void) // RMB6 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0xBF;
WRITE_BACK(m);
static void Op77(void) // RMB7 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m &= 0x7F;
WRITE_BACK(m);
// ROL opcodes
#define OP_ROL_HANDLER(m) \
- uint8 tmp = regs.cc & 0x01; \
+ uint8_t tmp = regs.cc & 0x01; \
regs.cc = ((m) & 0x80 ? regs.cc | FLAG_C : regs.cc & ~FLAG_C); \
(m) = ((m) << 1) | tmp; \
SET_ZN((m))
static void Op26(void) // ROL ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
static void Op36(void) // ROL ZP, X
{
- uint8 m;
+ uint8_t m;
READ_ZP_X_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
static void Op2E(void) // ROL ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
static void Op3E(void) // ROL ABS, X
{
- uint8 m;
+ uint8_t m;
READ_ABS_X_WB(m);
OP_ROL_HANDLER(m);
WRITE_BACK(m);
// ROR opcodes
#define OP_ROR_HANDLER(m) \
- uint8 tmp = (regs.cc & 0x01) << 7; \
+ uint8_t tmp = (regs.cc & 0x01) << 7; \
regs.cc = ((m) & 0x01 ? regs.cc | FLAG_C : regs.cc & ~FLAG_C); \
(m) = ((m) >> 1) | tmp; \
SET_ZN((m))
static void Op66(void) // ROR ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op76(void) // ROR ZP, X
{
- uint8 m;
+ uint8_t m;
READ_ZP_X_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op6E(void) // ROR ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op7E(void) // ROR ABS, X
{
- uint8 m;
+ uint8_t m;
READ_ABS_X_WB(m);
OP_ROR_HANDLER(m);
WRITE_BACK(m);
static void Op40(void) // RTI
{
regs.cc = regs.RdMem(0x0100 + ++regs.sp);
+//clear I (seems to be the case, either that or clear it in the IRQ setup...)
+//I can't find *any* verification that this is the case.
+// regs.cc &= ~FLAG_I;
regs.pc = regs.RdMem(0x0100 + ++regs.sp);
- regs.pc |= (uint16)(regs.RdMem(0x0100 + ++regs.sp)) << 8;
+ regs.pc |= (uint16_t)(regs.RdMem(0x0100 + ++regs.sp)) << 8;
}
/*
static void Op60(void) // RTS
{
regs.pc = regs.RdMem(0x0100 + ++regs.sp);
- regs.pc |= (uint16)(regs.RdMem(0x0100 + ++regs.sp)) << 8;
+ regs.pc |= (uint16_t)(regs.RdMem(0x0100 + ++regs.sp)) << 8;
regs.pc++; // Since it pushes return address - 1...
//printf("*** RTS: PC = $%04X, SP= $1%02X\n", regs.pc, regs.sp);
//fflush(stdout);
//This is non-optimal, but it works--optimize later. :-)
//This is correct except for the BCD handling... !!! FIX !!! [Possibly DONE]
#define OP_SBC_HANDLER(m) \
- uint16 sum = (uint16)regs.a - (m) - (uint16)((regs.cc & FLAG_C) ^ 0x01); \
+ uint16_t sum = (uint16_t)regs.a - (m) - (uint16_t)((regs.cc & FLAG_C) ^ 0x01); \
\
if (regs.cc & FLAG_D) \
{ \
static void OpE9(void) // SBC #
{
- uint16 m = READ_IMM;
+ uint16_t m = READ_IMM;
OP_SBC_HANDLER(m);
}
static void OpE5(void) // SBC ZP
{
- uint16 m = READ_ZP;
+ uint16_t m = READ_ZP;
OP_SBC_HANDLER(m);
}
static void OpF5(void) // SBC ZP, X
{
- uint16 m = READ_ZP_X;
+ uint16_t m = READ_ZP_X;
OP_SBC_HANDLER(m);
}
static void OpED(void) // SBC ABS
{
- uint16 m = READ_ABS;
+ uint16_t m = READ_ABS;
OP_SBC_HANDLER(m);
}
static void OpFD(void) // SBC ABS, X
{
- uint16 m = READ_ABS_X;
+ uint16_t m = READ_ABS_X;
OP_SBC_HANDLER(m);
}
static void OpF9(void) // SBC ABS, Y
{
- uint16 m = READ_ABS_Y;
+ uint16_t m = READ_ABS_Y;
OP_SBC_HANDLER(m);
}
static void OpE1(void) // SBC (ZP, X)
{
- uint16 m = READ_IND_ZP_X;
+ uint16_t m = READ_IND_ZP_X;
OP_SBC_HANDLER(m);
}
static void OpF1(void) // SBC (ZP), Y
{
- uint16 m = READ_IND_ZP_Y;
+ uint16_t m = READ_IND_ZP_Y;
OP_SBC_HANDLER(m);
}
static void OpF2(void) // SBC (ZP)
{
- uint16 m = READ_IND_ZP;
+ uint16_t m = READ_IND_ZP;
OP_SBC_HANDLER(m);
}
static void Op87(void) // SMB0 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x01;
WRITE_BACK(m);
static void Op97(void) // SMB1 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x02;
WRITE_BACK(m);
static void OpA7(void) // SMB2 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x04;
WRITE_BACK(m);
static void OpB7(void) // SMB3 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x08;
WRITE_BACK(m);
static void OpC7(void) // SMB4 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x10;
WRITE_BACK(m);
static void OpD7(void) // SMB5 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x20;
WRITE_BACK(m);
static void OpE7(void) // SMB6 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x40;
WRITE_BACK(m);
static void OpF7(void) // SMB7 ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
m |= 0x80;
WRITE_BACK(m);
static void Op96(void)
{
- regs.WrMem(EA_ZP_X, regs.x);
+// BUG!!! [FIXED]
+//WAS: regs.WrMem(EA_ZP_X, regs.x);
+ regs.WrMem(EA_ZP_Y, regs.x);
}
static void Op8E(void)
static void Op14(void) // TRB ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_TRB_HANDLER(m);
WRITE_BACK(m);
static void Op1C(void) // TRB ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_TRB_HANDLER(m);
WRITE_BACK(m);
static void Op04(void) // TSB ZP
{
- uint8 m;
+ uint8_t m;
READ_ZP_WB(m);
OP_TSB_HANDLER(m);
WRITE_BACK(m);
static void Op0C(void) // TSB ABS
{
- uint8 m;
+ uint8_t m;
READ_ABS_WB(m);
OP_TSB_HANDLER(m);
WRITE_BACK(m);
OpF0, OpF1, OpF2, Op__, Op__, OpF5, OpF6, OpF7, OpF8, OpF9, OpFA, Op__, Op__, OpFD, OpFE, OpFF
};
+
//
// Internal "memcpy" (so we don't have to link with any external libraries!)
//
-static void myMemcpy(void * dst, void * src, uint32 size)
+static void myMemcpy(void * dst, void * src, uint32_t size)
{
- uint8 * d = (uint8 *)dst, * s = (uint8 *)src;
+ uint8_t * d = (uint8_t *)dst, * s = (uint8_t *)src;
- for(uint32 i=0; i<size; i++)
+ for(uint32_t i=0; i<size; i++)
d[i] = s[i];
}
//int instCount[256];
#ifdef __DEBUG__
bool dumpDis = false;
+//bool dumpDis = true;
#endif
+/*
+On //e, $FCAA is the delay routine. (seems to not have changed from ][+)
+*/
+
+
//Note: could enforce regs.clock to zero on starting the CPU with an Init() function...
//bleh.
-//static uint32 limit = 0;
-
+//static uint32_t limit = 0;
+// Or, we could just say that initializing the CPU struct is the responsibility
+// of the caller. :-)
+
+#define DO_BACKTRACE
+#ifdef DO_BACKTRACE
+#define BACKTRACE_SIZE 16384
+uint32_t btQueuePtr = 0;
+V65C02REGS btQueue[BACKTRACE_SIZE];
+uint8_t btQueueInst[BACKTRACE_SIZE][4];
+#endif
//
// Function to execute 65C02 for "cycles" cycles
//
-void Execute65C02(V65C02REGS * context, uint32 cycles)
+void Execute65C02(V65C02REGS * context, uint32_t cycles)
{
myMemcpy(®s, context, sizeof(V65C02REGS));
// Execute here...
-// NOTE: There *must* be some way of doing this without requiring the caller to subtract out
-// the previous run's cycles. !!! FIX !!!
-// Could try:
-// while (regs.clock < regs.clock + cycles) <-- won't work
-/*
- // This isn't as accurate as subtracting out cycles from regs.clock...
- // Unless limit is a static variable, adding cycles to it each time through...
- uint32 limit = regs.clock + cycles;
- while (regs.clock < limit)
-*/
-// but have wraparound to deal with. :-/
-/*
-Let's see...
-
- if (regs.clock + cycles > 0xFFFFFFFF)
- wraparound = true;
-*/
+ uint64_t endCycles = regs.clock + (uint64_t)cycles - regs.overflow;
- while (regs.clock < cycles)
+ while (regs.clock < endCycles)
{
#if 0
/*if (regs.pc == 0x4007)
dumpDis = false;
}//*/
#endif
+/*if (regs.pc == 0xBF4C)
+{
+ dumpDis = true;
+}//*/
+#if 0
+/*if (regs.pc == 0x0801)
+{
+ WriteLog("\n*** DISK BOOT subroutine...\n\n");
+ dumpDis = true;
+}//*/
+if (regs.pc == 0xE000)
+{
+#if 0
+ WriteLog("\n*** Dump of $E000 routine ***\n\n");
+
+ for(uint32_t addr=0xE000; addr<0xF000;)
+ {
+ addr += Decode65C02(addr);
+ WriteLog("\n");
+ }
+#endif
+ WriteLog("\n*** DISK part II subroutine...\n\n");
+ dumpDis = true;
+}//*/
+if (regs.pc == 0xD000)
+{
+ WriteLog("\n*** CUSTOM DISK READ subroutine...\n\n");
+ dumpDis = false;
+}//*/
+if (regs.pc == 0xD1BE)
+{
+// WriteLog("\n*** DISK part II subroutine...\n\n");
+ dumpDis = true;
+}//*/
+if (regs.pc == 0xD200)
+{
+ WriteLog("\n*** CUSTOM SCREEN subroutine...\n\n");
+ dumpDis = false;
+}//*/
+if (regs.pc == 0xD269)
+{
+// WriteLog("\n*** DISK part II subroutine...\n\n");
+ dumpDis = true;
+}//*/
+#endif
+//if (regs.pc == 0xE08E)
+/*if (regs.pc == 0xAD33)
+{
+ WriteLog("\n*** After loader ***\n\n");
+ dumpDis = true;
+}//*/
+/*if (regs.pc == 0x0418)
+{
+ WriteLog("\n*** CUSTOM DISK READ subroutine...\n\n");
+ dumpDis = false;
+}
+if (regs.pc == 0x0)
+{
+ dumpDis = true;
+}//*/
#ifdef __DEBUGMON__
//WAIT is commented out here because it's called by BELL1...
if (regs.pc == 0xFCA8)
dumpDis = false;
}
#endif
+#if 0
+// ProDOS debugging
+if (regs.pc == 0x2000)
+ dumpDis = true;
+#endif
#ifdef __DEBUG__
+static char disbuf[80];
if (dumpDis)
- Decode65C02(regs.pc);
+{
+ Decode65C02(disbuf, regs.pc);
+ WriteLog("%s", disbuf);
+}
#endif
- uint8 opcode = regs.RdMem(regs.pc++);
+ uint8_t opcode = regs.RdMem(regs.pc++);
//if (!(regs.cpuFlags & V65C02_STATE_ILLEGAL_INST))
//instCount[opcode]++;
regs.clock += CPUCycles[opcode];
#ifdef __DEBUG__
if (dumpDis)
- WriteLog(" [PC=%04X, SP=%04X, CC=%s%s-%s%s%s%s%s, A=%02X, X=%02X, Y=%02X]\n",
+ WriteLog(" [PC=%04X, SP=%04X, CC=%s%s.%s%s%s%s%s, A=%02X, X=%02X, Y=%02X]\n",
regs.pc, 0x0100 + regs.sp,
(regs.cc & FLAG_N ? "N" : "-"), (regs.cc & FLAG_V ? "V" : "-"),
(regs.cc & FLAG_B ? "B" : "-"), (regs.cc & FLAG_D ? "D" : "-"),
}
}
-//This is a lame way of doing it, but in the end the simplest--however, it destroys any
-//record of elasped CPU time. Not sure that it's important to keep track, but there it is.
- regs.clock -= cycles;
+ // If we went longer than the passed in cycles, make a note of it so we can
+ // subtract it out from a subsequent run. It's guaranteed to be positive,
+ // because the condition that exits the main loop above is written such
+ // that regs.clock has to be larger than endCycles to exit from it.
+ regs.overflow = regs.clock - endCycles;
myMemcpy(context, ®s, sizeof(V65C02REGS));
}
+
//
// Get the clock of the currently executing CPU
//
-uint32 GetCurrentV65C02Clock(void)
+uint64_t GetCurrentV65C02Clock(void)
{
return regs.clock;
}
+
projects / apple2 / blobdiff