Fix to M68K core vs. DSP thread sync problem.

[virtualjaguar] / src / gpu.cpp

diff --git a/src/gpu.cpp b/src/gpu.cpp
index c57b948d5088751dd169e4d20f0d5e89a7a11a3c..e5855fea7eda560f68fcdc186f74b781febaf36d 100644 (file)
--- a/src/gpu.cpp
+++ b/src/gpu.cpp
@@ -323,8 +323,8 @@ static uint32 gpu_div_control;
 // a bit before writing a result. I.e., if the result of an operation leaves a zero in
 // the carry flag, you don't have to zero gpu_flag_c before you can write that zero!
 static uint8 gpu_flag_z, gpu_flag_n, gpu_flag_c;
-static uint32 gpu_reg_bank_0[32];
-static uint32 gpu_reg_bank_1[32];
+uint32 gpu_reg_bank_0[32];
+uint32 gpu_reg_bank_1[32];
 static uint32 * gpu_reg;
 static uint32 * gpu_alternate_reg;
 
@@ -501,7 +501,11 @@ uint16 GPUReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
 uint32 GPUReadLong(uint32 offset, uint32 who/*=UNKNOWN*/)
 {
        if (offset >= 0xF02000 && offset <= 0xF020FF)
-               WriteLog("GPU: ReadLong--Attempt to read from GPU register file by %s!\n", whoName[who]);
+       {
+               WriteLog("GPU: ReadLong--Attempt to read from GPU register file (%X) by %s!\n", offset, whoName[who]);
+               uint32 reg = (offset & 0xFC) >> 2;
+               return (reg < 32 ? gpu_reg_bank_0[reg] : gpu_reg_bank_1[reg - 32]); 
+       }
 
 //     if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE + 0x1000))
        if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFC))
@@ -776,6 +780,7 @@ WriteLog("GPU: %s setting GPU PC to %08X %s\n", whoName[who], gpu_pc, (GPU_RUNNI
                        {
                                //WriteLog("asked to perform a single step (single step is %senabled)\n",(data&0x8)?"":"not ");
                        }
+
                        gpu_control = (gpu_control & 0xF7C0) | (data & (~0xF7C0));
 
                        // if gpu wasn't running but is now running, execute a few cycles