dsp_opcode_use[i] = 0;
}
+
void DSPReleaseTimeslice(void)
{
//This does absolutely nothing!!! !!! FIX !!!
dsp_releaseTimeSlice_flag = 1;
}
+
void dsp_build_branch_condition_table(void)
{
// Fill in the mirror table
}
}
+
uint8_t DSPReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF1A000 && offset <= 0xF1A0FF)
{
uint32_t data = DSPReadLong(offset & 0xFFFFFFFC, who);
- if ((offset&0x03)==0)
- return(data>>24);
- else
- if ((offset&0x03)==1)
- return((data>>16)&0xff);
- else
- if ((offset&0x03)==2)
- return((data>>8)&0xff);
- else
- if ((offset&0x03)==3)
- return(data&0xff);
+ if ((offset & 0x03) == 0)
+ return (data >> 24);
+ else if ((offset & 0x03) == 1)
+ return ((data >> 16) & 0xFF);
+ else if ((offset & 0x03) == 2)
+ return ((data >> 8) & 0xFF);
+ else if ((offset & 0x03) == 3)
+ return (data & 0xFF);
}
return JaguarReadByte(offset, who);
}
+
uint16_t DSPReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF1A000 && offset <= 0xF1A0FF)
return JaguarReadWord(offset, who);
}
+
uint32_t DSPReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF1A000 && offset <= 0xF1A0FF)
return JaguarReadLong(offset, who);
}
+
void DSPWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF1A000 && offset <= 0xF1A0FF)
WriteLog("DSP: WriteByte--Attempt to write to DSP register file by %s!\n", whoName[who]);
- if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
+ if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE + 0x2000))
{
offset -= DSP_WORK_RAM_BASE;
dsp_ram_8[offset] = data;
}*/
return;
}
- if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
+ if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE + 0x20))
{
uint32_t reg = offset & 0x1C;
int bytenum = offset & 0x03;
}
// WriteLog("dsp: writing %.2x at 0x%.8x\n",data,offset);
//Should this *ever* happen??? Shouldn't we be saying "unknown" here???
+// Well, yes, it can. There are 3 MMU users after all: 68K, GPU & DSP...!
JaguarWriteByte(offset, data, who);
}
+
void DSPWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF1A000 && offset <= 0xF1A0FF)
JaguarWriteWord(offset, data, who);
}
+
//bool badWrite = false;
void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/)
{
JaguarWriteLong(offset, data, who);
}
+
//
// Update the DSP register file pointers depending on REGPAGE bit
//
#endif
}
+
//
// Check for and handle any asserted DSP IRQs
//
FlushDSPPipeline();
}
+
//
// Non-pipelined version...
//
//!!!!!!!!
}
+
//
// Set the specified DSP IRQ line to a given state
//
// GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE);
}
+
bool DSPIsRunning(void)
{
return (DSP_RUNNING ? true : false);
}
+
void DSPInit(void)
{
// memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM");
DSPReset();
}
+
void DSPReset(void)
{
dsp_pc = 0x00F1B000;
*((uint32_t *)(&dsp_ram_8[i])) = rand();
}
+
void DSPDumpDisassembly(void)
{
char buffer[512];
}
}
+
void DSPDumpRegisters(void)
{
//Shoud add modulus, etc to dump here...
}
}
+
void DSPDone(void)
{
int i, j;