#include "cdintf.h" // System agnostic CD interface functions
#include "cdrom.h"
-#define CDROM_LOG // For CDROM logging, obviously
+//#define CDROM_LOG // For CDROM logging, obviously
/*
BUTCH equ $DFFF00 ; base of Butch=interrupt control register, R/W
static void CDROMBusWrite(uint16);
static uint16 CDROMBusRead(void);
-#define BUTCH 0x00 // base of Butch=interrupt control register, R/W
+#define BUTCH 0x00 // base of Butch == interrupt control register, R/W
#define DSCNTRL BUTCH + 0x04 // DSA control register, R/W
#define DS_DATA BUTCH + 0x0A // DSA TX/RX data, R/W
#define I2CNTRL BUTCH + 0x10 // i2s bus control register, R/W
//Also need to set up (save/restore) the CD's NVRAM
-extern bool GetRawTOC(void);
+//extern bool GetRawTOC(void);
void CDROMInit(void)
{
haveCDGoodness = CDIntfInit();
//
void BUTCHExec(uint32 cycles)
{
+#if 1
+// We're chickening out for now...
return;
+#else
extern uint8 * jerry_ram_8; // Hmm.
// For now, we just do the FIFO interrupt. Timing is also likely to be WRONG as well.
//I'm *sure* this is wrong--prolly need to generate DSP IRQs as well!
if (jerry_ram_8[0x23] & 0x3F) // Only generate an IRQ if enabled!
GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE);
+#endif
}
bool ButchIsReadyToSend(void)
{
+WriteLog("Butch is%s ready to send...\n", cdRam[I2CNTRL + 3] & 0x02 ? "" : " not");
+
return (cdRam[I2CNTRL + 3] & 0x02 ? true : false);
}