//
-// RMAC - Reboot's Macro Assembler for all Atari computers
+// RMAC - Renamed Macro Assembler for all Atari computers
// MACH.C - Code Generation
-// Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
+// Copyright (C) 199x Landon Dyer, 2011-2021 Reboot and Friends
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
// Source utilised with the kind permission of Landon Dyer
//
int movep = 0; // Global flag to indicate we're generating a movep instruction
// Function prototypes
-int m_unimp(WORD, WORD), m_badmode(WORD, WORD), m_bad6mode(WORD, WORD), m_bad6inst(WORD, WORD);
+int m_unimp(WORD, WORD), m_badmode(WORD, WORD);
int m_self(WORD, WORD);
int m_abcd(WORD, WORD);
int m_reg(WORD, WORD);
int m_chk2(WORD inst, WORD siz);
int m_cmp2(WORD inst, WORD siz);
int m_bkpt(WORD inst, WORD siz);
-int m_cpbr(WORD inst, WORD siz);
+int m_cpbcc(WORD inst, WORD siz);
int m_cpdbr(WORD inst, WORD siz);
int m_muls(WORD inst, WORD siz);
int m_move16a(WORD inst, WORD siz);
int m_cprest(WORD inst, WORD siz);
int m_movec(WORD inst, WORD siz);
int m_moves(WORD inst, WORD siz);
+int m_lpstop(WORD inst, WORD siz);
+int m_plpa(WORD inst, WORD siz);
// PMMU
int m_pbcc(WORD inst, WORD siz);
int m_pflusha(WORD inst, WORD siz);
int m_pflush(WORD inst, WORD siz);
int m_pflushr(WORD inst, WORD siz);
+int m_pflushan(WORD inst, WORD siz);
int m_pload(WORD inst, WORD siz, WORD extension);
int m_pmove(WORD inst, WORD siz);
int m_pmovefd(WORD inst, WORD siz);
-int m_ptest(WORD inst, WORD siz);
+int m_ptest(WORD inst, WORD siz, WORD extension);
+int m_ptestr(WORD inste, WORD siz);
+int m_ptestw(WORD inste, WORD siz);
int m_ptrapcc(WORD inst, WORD siz);
int m_ploadr(WORD inst, WORD siz);
int m_ploadw(WORD inst, WORD siz);
// FPU
int m_fabs(WORD inst, WORD siz);
+int m_fbcc(WORD inst, WORD siz);
int m_facos(WORD inst, WORD siz);
int m_fadd(WORD inst, WORD siz);
int m_fasin(WORD inst, WORD siz);
{
inst = B16(01010000, 01001000) | (((uint16_t)a0exval & 7) << 9) | (a0reg);
D_word(inst);
- warn("lea size(An),An converted to addq #size,An");
+
+ if (optim_warn_flag)
+ warn("lea size(An),An converted to addq #size,An");
+
return OK;
}
// a corner case, so kludge it
a0reg = a0reg + 8;
else if (am0 == PCDISP)
- //Another corner case (possibly!), so kludge ahoy
+ // Another corner case (possibly!), so kludge ahoy
inst |= am0; // Get ea0 into instr
+ else if (am0 == IMMED && am1 == MEMPOST)
+ {
+ // Added for addi/andi/cmpi/eori/ori/subi #xx,(bd,An,Dm)
+ inst |= a1reg | AINDEXED;
+ }
else if (am0 == IMMED)
inst |= am0 | a0reg; // Get ea0 into instr
else if (am0 == AM_CCR)
//
int m_adda(WORD inst, WORD siz)
{
- if (a0exattr & DEFINED)
+ if ((a0exattr & DEFINED) && (am0 == IMMED))
{
- if (CHECK_OPTS(OPT_ADDA_ADDQ))
- if (a0exval > 1 && a0exval <= 8)
+ if (CHECK_OPTS(OPT_ADDA_ADDQ))
+ {
+ if ((a0exval > 1) && (a0exval <= 8))
+ {
// Immediate is between 1 and 8 so let's convert to addq
return m_addq(B16(01010000, 00000000), siz);
- if (CHECK_OPTS(OPT_ADDA_LEA))
- if (a0exval > 8)
- {
- // Immediate is larger than 8 so let's convert to lea
- am0 = ADISP; // Change addressing mode
- a0reg = a1reg; // In ADISP a0reg is used instead of a1reg!
- return m_lea(B16(01000001, 11011000), SIZW);
+
+ if (optim_warn_flag)
+ warn("adda/suba size(An),An converted to addq/subq #size,An");
+ }
+ }
+
+ if (CHECK_OPTS(OPT_ADDA_LEA))
+ {
+ if ((a0exval > 8) && ((a0exval + 0x8000) < 0x10000))
+ {
+ // Immediate is larger than 8 and word size so let's convert to lea
+ am0 = ADISP; // Change addressing mode
+ a0reg = a1reg; // In ADISP a0reg is used instead of a1reg!
+
+ if (!(inst & (1 << 14)))
+ {
+ // We have a suba #x,AREG so let's negate the value
+ a0exval = -a0exval;
+ }
+
+ // We're going to rely on +o4 for this, so let's ensure that
+ // it's on, even just for this instruction
+ int return_value;
+ int temp_flag = optim_flags[OPT_LEA_ADDQ];
+ optim_flags[OPT_LEA_ADDQ] = 1; // Temporarily save switch state
+ return_value = m_lea(B16(01000001, 11011000), SIZW);
+ optim_flags[OPT_LEA_ADDQ] = temp_flag; // Restore switch state
+ return return_value;
+ }
}
}
if ((a1exattr & TDB) != cursect)
return error(rel_error);
- uint32_t v = a1exval - sloc;
+ uint32_t v = (uint32_t)a1exval - sloc;
if (v + 0x8000 > 0x10000)
return error(range_error);
WORD extra_addressing[16]=
{
- 0, // 0100 (bd,An,Xn)
- 0, // 0101 ([bd,An],Xn,od)
- 0x180, // 0102 ([bc,An,Xn],od) (111 110 110 111)
- 0, // 0103 (bd,PC,Xn)
- 0, // 0104 ([bd,PC],Xn,od)
- 0, // 0105 ([bc,PC,Xn],od)
+ 0x30, // 0100 (bd,An,Xn)
+ 0x30, // 0101 ([bd,An],Xn,od)
+ 0x30, // 0102 ([bc,An,Xn],od)
+ 0x30, // 0103 (bd,PC,Xn)
+ 0x30, // 0104 ([bd,PC],Xn,od)
+ 0x30, // 0105 ([bc,PC,Xn],od)
0, // 0106
0, // 0107
0, // 0110
{
m_moveq((WORD)0x7000, (WORD)0);
- if (sbra_flag)
+ if (optim_warn_flag)
warn("move.l #size,dx converted to moveq");
}
else
//
// Handle MOVE <C_ALL030> <C_ALTDATA>
-// MOVE <C_ALL030> <M_AREG>
+// MOVE <C_ALL030> <M_AREG>
//
int m_move30(WORD inst, WORD size)
{
int siz = (int)size;
- // TODO: is extra_addressing necessary/correct?
- //inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
- inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg;
+
+ if (am0 > ABASE)
+ inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
+ else
+ inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am1 - ABASE] << 3;
D_word(inst);
inst |= v & 0xFF;
D_word(inst);
- if (sbra_flag)
+ if (optim_warn_flag)
warn("Bcc.w/BSR.w converted to .s");
return OK;
{
// .B
AddFixup(FU_BBRA | FU_PCREL | FU_SEXT, sloc, a0expr);
- D_word(inst);
+ // So here we have a small issue: this bra.s could be zero offset, but
+ // we can never know. Because unless we know beforehand that the
+ // offset will be zero (i.e. "bra.s +0"), it's going to be a label
+ // below this instruction! We do have an optimisation flag that can
+ // check against this during fixups, but we cannot rely on the state
+ // of the flag after all the file(s) have been processed because its
+ // state might have changed multiple times during file parsing. (Yes,
+ // there's a very low chance that this will ever happen but it's not
+ // zero!). So, we can use the byte that is going to be filled during
+ // fixups to store the state of the optimisation flag and read it
+ // during that stage so each bra.s will have its state stored neatly.
+ // Sleazy? Eh, who cares, like this will ever happen ;)
+ // One final note: we'd better be damn sure that the flag's value is
+ // less than 256 or magical stuff will happen!
+ D_word(inst | optim_flags[OPT_NULL_BRA]);
return OK;
}
else
rmask = 0;
for(i=0x8000; i; i>>=1, w>>=1)
- rmask = (WORD)((rmask << 1) | w & 1);
+ rmask = (WORD)((rmask << 1) | (w & 1));
}
}
else
else
bfparam1 = bfval1 << 12;
- D_word((inst | am0 | a0reg | am1 | a1reg));
+ //D_word((inst | am0 | a0reg | am1 | a1reg));
+ if (inst == B16(11101111, 11000000))
+ {
+ // bfins special case
+ D_word((inst | am1 | a1reg));
+ }
+ else
+ {
+ D_word((inst | am0 | a0reg));
+ }
+
ea0gen(siz); // Generate EA
// Second instruction word - Dest register (if exists), Do, Offset, Dw, Width
- inst = bfparam1 | bfparam2;
+ if (inst == B16(11101111, 11000000))
+ {
+ // bfins special case
+ inst = bfparam1 | bfparam2;
- if (am1 == DREG)
- inst |= a1reg << 0;
+ if (am1 == DREG)
+ inst |= a0reg << 12;
- if (am0 == DREG)
- inst |= a0reg << 12;
+ D_word(inst);
+ }
+ else
+ {
+ inst = bfparam1 | bfparam2;
- D_word(inst);
+ if (am1 == DREG)
+ inst |= a0reg << 0;
+
+ if (am0 == DREG)
+ inst |= a1reg << 12;
+
+ D_word(inst);
+ }
return OK;
}
//
-// cpbcc(68020, 68030)
+// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc)), pbcc (68851)
//
-int m_cpbr(WORD inst, WORD siz)
+int m_fpbr(WORD inst, WORD siz)
{
- if ((activecpu & (CPU_68020 | CPU_68030)) == 0)
- return error(unsupport);
if (a0exattr & DEFINED)
{
return OK;
}
}
- else // SIZW/SIZN
+ else // SIZW/SIZN
{
if ((v + 0x8000) >= 0x10000)
return error(range_error);
}
+//
+// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc))
+//
+int m_cpbcc(WORD inst, WORD siz)
+{
+ if (!(activecpu & (CPU_68020 | CPU_68030)))
+ return error(unsupport);
+
+ return m_fpbr(inst, siz);
+}
+
+
+//
+// fbcc(6808X, 68040, 68060)
+//
+int m_fbcc(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return m_fpbr(inst, siz);
+}
+
+
+//
+// pbcc(68851 but let's assume 68020 only)
+//
+int m_pbcc(WORD inst, WORD siz)
+{
+ CHECKNO20;
+ return m_fpbr(inst, siz);
+}
+
+
//
// cpdbcc(68020, 68030)
//
}
return OK;
+
}
if (flg & 16)
{
- // OR-in register number
+ // OR-in register number
if (flg & 8)
inst |= reg_9[a1reg]; // ea1reg in bits 9..11
else
D_word(inst);
- // Generate ea0 if requested
+ // Generate ea0 if requested
if (flg & 2)
ea0gen(siz);
return error("Wasn't this suppose to call m_move16a???");
else
{
- //move16 (ax)+,(xxx).L
+ // move16 (ax)+,(xxx).L
inst |= 0 << 3;
v = (int)a1exval;
}
{
if (am1 == AIND)
{
- //move16 (xxx).L,(ax)+
+ // move16 (xxx).L,(ax)+
inst |= 1 << 3;
v = (int)a0exval;
}
- else //APOSTINC
+ else // APOSTINC
{
- //move16 (xxx).L,(ax)
+ // move16 (xxx).L,(ax)
inst |= 3 << 3;
v = (int)a0exval;
}
}
else if (am0 == AIND)
{
- //move16 (ax),(xxx).L
+ // move16 (ax),(xxx).L
inst |= 2 << 3;
v = (int)a1exval;
}
//
-// cinvl/p/a (68040)
+// cinvl/p/a (68040/68060)
//
int m_cinv(WORD inst, WORD siz)
{
//
-// movec (68010, 68020, 68030, 68040, CPU32)
+// movec (68010, 68020, 68030, 68040, 68060, CPU32)
//
int m_movec(WORD inst, WORD siz)
{
}
-//
-// PBcc (MC68851)
-//
-int m_pbcc(WORD inst, WORD siz)
-{
- CHECKNO20;
- return error("Not implemented yet.");
-}
-
-
//
// pflusha (68030, 68040)
//
if ((a0exattr & DEFINED) == 0)
return error("function code immediate should be defined");
- if (a0exval > 7 && a0exval < 0)
+ if (a0exval > 7)
return error("function code out of range (0-7)");
fc = (uint16_t)a0exval;
if ((a0exattr & DEFINED) == 0)
return error("mask immediate value should be defined");
- if (a0exval > 7 && a0exval < 0)
+ if (a0exval > 7)
return error("function code out of range (0-7)");
mask = (uint16_t)a0exval << 5;
}
+//
+// pflushan (68040, 68060)
+//
+int m_pflushan(WORD inst, WORD siz)
+{
+ if (activecpu == CPU_68040 || activecpu == CPU_68060)
+ D_word(inst);
+
+ return OK;
+}
+
+
//
// pflushr (68851)
//
inst = 1;
else
return error("illegal control register specified");
-
break;
case DREG:
inst = (1 << 3) | a0reg;
if ((a0exattr & DEFINED) == 0)
return error("constant value must be defined");
+ if (a0exval>7)
+ return error("constant value must be between 0 and 7");
+
inst = (2 << 3) | (uint16_t)a0exval;
break;
}
// The instruction is a quad-word (8 byte) operation
// for the CPU root pointer and the supervisor root pointer.
- // It is a long - word operation for the translation control register
+ // It is a long-word operation for the translation control register
// and the transparent translation registers(TT0 and TT1).
// It is a word operation for the MMU status register.
}
else if (am1 == CREG)
{
- inst |= am0 | a0reg;
+ inst |= am0 | a0reg;
D_word(inst);
}
//
int m_ptrapcc(WORD inst, WORD siz)
{
- CHECKNO20;
+ CHECKNO20;
// We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4),
// so we need to extract them first and fill in the clobbered bits.
WORD opcode = inst & 0x1F;
//
-// ptestr, ptestw (68030)
+// ptestr, ptestw (68030, 68040)
+// TODO See comment on m_pmove about 68851 support
+// TODO quite a good chunk of the 030 code is copied from m_pload, perhaps merge these somehow?
//
-int m_ptest(WORD inst, WORD siz)
+int m_ptest(WORD inst, WORD siz, WORD extension)
{
- CHECKNO30;
+ uint64_t eval;
+
+ if (activecpu != CPU_68030 && activecpu != CPU_68040)
+ return error(unsupport);
if (activecpu == CPU_68030)
- return error("Not implemented yet.");
- else if (activecpu == CPU_68040)
+ {
+ inst |= am1;
+ D_word(inst);
+
+ switch (am0)
+ {
+ case CREG:
+ if (a0reg == KW_SFC - KW_SFC)
+ extension |= 0;
+ else if (a0reg == KW_DFC - KW_SFC)
+ extension |= 1;
+ else
+ return error("illegal control register specified");
+ break;
+ case DREG:
+ extension |= (1 << 3) | a0reg;
+ break;
+ case IMMED:
+ if ((a0exattr & DEFINED) == 0)
+ return error("constant value must be defined");
+
+ if (a0exval > 7)
+ return error("constant value must be between 0 and 7");
+
+ extension |= (2 << 3) | (uint16_t)a0exval;
+ break;
+ }
+
+ // Operand 3 must be an immediate
+ CHECK_COMMA
+
+ if (*tok++ != '#')
+ return error("ptest level must be immediate");
+
+ // Let's be a bit inflexible here and demand that this
+ // is fully defined at this stage. Otherwise we'd have
+ // to arrange for a bitfield fixup, which would mean
+ // polluting the bitfields and codebase with special
+ // cases that might most likely never be used.
+ // So if anyone gets bit by this: sorry for being a butt!
+ if (abs_expr(&eval) != OK)
+ return OK; // We're returning OK because error() has already been called and error count has been increased
+
+ if (eval > 7)
+ return error("ptest level must be between 0 and 7");
+
+ extension |= eval << 10;
+
+ // Operand 4 is optional and must be an address register
+
+ if (*tok != EOL)
+ {
+ CHECK_COMMA
+
+ if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ {
+ extension |= (1 << 8) | ((*tok++ & 7) << 4);
+ }
+ else
+ {
+ return error("fourth parameter must be an address register");
+ }
+ }
+
+ ErrorIfNotAtEOL();
+
+ D_word(extension);
+ return OK;
+ }
+ else
return error("Not implemented yet.");
return ERROR;
}
+int m_ptestr(WORD inst, WORD siz)
+{
+ return m_ptest(inst, siz, (1 << 15) | (0 << 9));
+}
+
+int m_ptestw(WORD inst, WORD siz)
+{
+ return m_ptest(inst, siz, (1 << 15) | (1 << 9));
+}
+
//////////////////////////////////////////////////////////////////////////////
//
// 68020/30/40/60 instructions
if (activefpu == FPU_68040)
warn("Instruction is emulated in 68040");
-
+
return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN);
}
//
-// flognp1 (68040FPSP, 68060FPSP)
+// flognp1 (6888X, 68040FPSP, 68060FPSP)
//
int m_flognp1(WORD inst, WORD siz)
{
- if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(00000110), FPU_FPSP);
-
- return error("Unsupported in current FPU");
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00000110), FPU_FPSP);
}
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return error("Not implemented yet.");
-
-#if 0
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
-#endif
+ return gen_fpu(inst, siz, B8(01100100), FPU_FPSP);
}
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return error("Not implemented yet.");
-
-#if 0
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
-#endif
+ return gen_fpu(inst, siz, B8(01100100), FPU_FPSP);
}
{
if (activefpu & (FPU_68040 | FPU_68060))
return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN);
-
+
return error("Unsupported in current FPU");
}
a1reg = a0reg;
return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
}
-
+
return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
}
a1reg = a0reg;
return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
}
-
+
return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
}
{
if (activefpu & (FPU_68040 | FPU_68060))
return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN);
-
+
return error("Unsupported in current FPU");
}
return gen_fpu(inst, siz, B8(00010001), FPU_FPSP);
}
+
+/////////////////////////////////
+// //
+// 68060 specific instructions //
+// //
+/////////////////////////////////
+
+
+//
+// lpstop (68060)
+//
+int m_lpstop(WORD inst, WORD siz)
+{
+ CHECKNO60;
+ D_word(B16(00000001, 11000000));
+
+ if (a0exattr & DEFINED)
+ {
+ D_word(a0exval);
+ }
+ else
+ {
+ AddFixup(FU_WORD, sloc, a0expr);
+ D_word(0);
+ }
+
+ return OK;
+}
+
+
+//
+// plpa (68060)
+//
+int m_plpa(WORD inst, WORD siz)
+{
+ CHECKNO60;
+ inst |= a0reg; // Install register
+ D_word(inst);
+
+ return OK;
+}
+