#include "sect.h"
#include "math.h"
-#define DEF_KW
-#include "kwtab.h"
#define DEF_MN
#include "mntab.h"
+#define DEF_REG56
+#include "56kregs.h"
// Address-mode information
int dsp_am0; // Addressing mode
//
static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnEXVAL, WORD * AnEXATTR, SYM ** AnESYM, LONG *memspace, LONG *perspace, const int operand)
{
- if (*tok == KW_A || *tok == KW_B)
+ if (*tok == REG56_A || *tok == REG56_B)
{
*am = M_ACC56;
*areg = *tok++;
return OK;
}
- else if (*tok >= KW_X0 && *tok <= KW_Y1)
+ else if (*tok >= REG56_X0 && *tok <= REG56_Y1)
{
*am = M_ALU24;
*areg = *tok++;
return OK;
}
- else if (*tok == KW_X && *(tok + 1) == ':')
+ else if (*tok == REG56_X && *(tok + 1) == ':')
{
tok = tok + 2;
else
return ERROR;
}
- else if (*tok == KW_Y && *(tok + 1) == ':')
+ else if (*tok == REG56_Y && *(tok + 1) == ':')
{
tok = tok + 2;
return ERROR;
// TODO: add absolute address checks
}
- else if ((*tok >= KW_X) && (*tok <= KW_Y))
+ else if ((*tok >= REG56_X) && (*tok <= REG56_Y))
{
*am = M_INP48;
*areg = *tok++;
return OK;
}
- else if ((*tok >= KW_M0) && (*tok <= KW_M7))
+ else if ((*tok >= REG56_M0) && (*tok <= REG56_M7))
{
*am = M_DSPM;
*areg = (*tok++) & 7;
return OK;
}
- else if ((*tok >= KW_R0) && (*tok <= KW_R7))
+ else if ((*tok >= REG56_R0) && (*tok <= REG56_R7))
{
*am = M_DSPR;
- *areg = (*tok++) - KW_R0;
+ *areg = (*tok++) - REG56_R0;
return OK;
}
- else if ((*tok >= KW_N0) && (*tok <= KW_N7))
+ else if ((*tok >= REG56_N0) && (*tok <= REG56_N7))
{
*am = M_DSPN;
*areg = (*tok++) & 7;
return OK;
}
- else if ((*tok == KW_A0) || (*tok == KW_A1) || (*tok == KW_B0)
- || (*tok == KW_B1))
+ else if ((*tok == REG56_A0) || (*tok == REG56_A1) || (*tok == REG56_B0)
+ || (*tok == REG56_B1))
{
*am = M_ACC24;
*areg = *tok++;
return OK;
}
- else if ((*tok == KW_A2) || (*tok == KW_B2))
+ else if ((*tok == REG56_A2) || (*tok == REG56_B2))
{
*am = M_ACC8;
*areg = *tok++;
return OK;
}
- else if ((*tok == '-') && (*(tok + 1) == KW_X0 || *(tok + 1) == KW_X1 || *(tok + 1) == KW_Y0 || *(tok + 1) == KW_Y1))
+ else if ((*tok == '-') && (*(tok + 1) == REG56_X0 || *(tok + 1) == REG56_X1 || *(tok + 1) == REG56_Y0 || *(tok + 1) == REG56_Y1))
{
// '-X0', '-Y0', '-X1' or '-Y1', used in multiplications
tok++;
dsp_k = 1 << 2;
return OK;
}
- else if (*tok == '+' && (*(tok + 1) == KW_X0 || *(tok + 1) == KW_X1 || *(tok + 1) == KW_Y0 || *(tok + 1) == KW_Y1))
+ else if (*tok == '+' && (*(tok + 1) == REG56_X0 || *(tok + 1) == REG56_X1 || *(tok + 1) == REG56_Y0 || *(tok + 1) == REG56_Y1))
{
// '+X0', '+Y0', '+X1' or '+Y1', used in multiplications
tok++;
// TODO: add absolute address checks
return error("internal assembler error: parmode checking for '(' and '-' does not have absolute address checks yet!");
}
- else if (*tok == KW_P && *(tok + 1) == ':')
+ else if (*tok == REG56_P && *(tok + 1) == ':')
{
tok = tok + 2;
*areg = DSP_EA_ABS;
return OK;
}
- else if (*tok == KW_PC || *tok == KW_CCR || *tok == KW_SR || *tok == KW_SP || (*tok >= KW_MR&&*tok <= KW_SS))
+ else if (*tok == REG56_PC || *tok == REG56_CCR || *tok == REG56_SR || *tok == REG56_SP || (*tok >= REG56_MR&&*tok <= REG56_SS))
{
*areg = *tok++;
*am = M_DSPPCU;
//
static inline int SDreg(int reg)
{
- if (reg >= KW_X0 && reg <= KW_N7)
+ if (reg >= REG56_X0 && reg <= REG56_N7)
return reg & 0xFF;
- else if (reg >= KW_A0&® <= KW_A2)
+ else if (reg >= REG56_A0&® <= REG56_A2)
return (8 >> (reg & 7)) | 8;
- else //if (reg>=KW_R0&®<=KW_R7)
- return reg - KW_R0 + 16;
+ else //if (reg>=REG56_R0&®<=REG56_R7)
+ return reg - REG56_R0 + 16;
// Handy map for the above:
// (values are of course taken from keytab)
// Register | Value | Return value
// Check for D1
switch (K_D1 = *tok++)
{
- case KW_X0: D1 = 0 << 10; break;
- case KW_X1: D1 = 1 << 10; break;
- case KW_A: D1 = 2 << 10; break;
- case KW_B: D1 = 3 << 10; break;
+ case REG56_X0: D1 = 0 << 10; break;
+ case REG56_X1: D1 = 1 << 10; break;
+ case REG56_A: D1 = 2 << 10; break;
+ case REG56_B: D1 = 3 << 10; break;
default: return error("unrecognised X:Y: parallel move syntax: expected x0, x1, a or b after 'X:eax,'");
}
}
}
}
- if (*tok == KW_Y)
+ if (*tok == REG56_Y)
{
tok++;
// 'X:eax,D1 Y:eay,D2' 'S1,X:eax Y:eay,D2'
if (*tok++ == '(')
{
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
- ea2 = (*tok++ - KW_R0);
+ ea2 = (*tok++ - REG56_R0);
if (((ea1 & 7) < 4 && ea2 < 4) || ((ea1 & 7) >= 4 && ea2 > 4))
return error("unrecognised X:Y: parallel move syntax: eax and eay register banks must be different in 'X:ea,D1/S1,X:ea Y:eay,D2'");
ea2 = 3 << 12;
tok++;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea2)
switch (K_D2 = *tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
- case KW_A: D2 = 2 << 8; break;
- case KW_B: D2 = 3 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
+ case REG56_A: D2 = 2 << 8; break;
+ case REG56_B: D2 = 3 << 8; break;
default: return error("unrecognised X:Y: parallel move syntax: expected y0, y1, a or b after 'X:ea,D1/S1,X:ea Y:eay,'");
}
else
return error("unrecognised X:Y: parallel move syntax: expected '(Rn)', '(Rn)+', '(Rn)-', '(Rn)+Nn' after 'X:ea,D1/S1,X:ea Y:'");
}
- else if (*tok == KW_Y0 || *tok == KW_Y1 || *tok == KW_A || *tok == KW_B)
+ else if (*tok == REG56_Y0 || *tok == REG56_Y1 || *tok == REG56_A || *tok == REG56_B)
{
// 'X:eax,D1 S2,Y:eay' 'S1,X:eax1 S2,Y:eay'
switch (*tok++)
{
- case KW_Y0: S2 = 0 << 8; break;
- case KW_Y1: S2 = 1 << 8; break;
- case KW_A: S2 = 2 << 8; break;
- case KW_B: S2 = 3 << 8; break;
+ case REG56_Y0: S2 = 0 << 8; break;
+ case REG56_Y1: S2 = 1 << 8; break;
+ case REG56_A: S2 = 2 << 8; break;
+ case REG56_B: S2 = 3 << 8; break;
default: return error("unrecognised X:Y: parallel move syntax: expected y0, y1, a or b after 'X:ea,D1/S1,X:ea Y:eay,'");
}
if (*tok++ != ',')
return error("unrecognised X:Y: parallel move syntax: expected ',' after 'X:ea,D1/S1,X:ea S2'");
- if (*tok++ == KW_Y)
+ if (*tok++ == REG56_Y)
{
// 'X:eax,D1 Y:eay,D2' 'S1,X:eax Y:eay,D2'
if (*tok++ != ':')
if (*tok++ == '(')
{
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
- ea2 = (*tok++ - KW_R0);
+ ea2 = (*tok++ - REG56_R0);
if (((ea1 & 7) < 4 && ea2 < 4) || ((ea1 & 7) >= 4 && ea2 > 4))
return error("unrecognised X:Y: parallel move syntax: eax and eay register banks must be different in 'X:ea,D1/S1,X:ea S2,Y:eay'");
if (*tok == EOL)
// (Rn)+
ea2 = 3 << 12;
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea2)
{
x_checkea_right:
// 'S1,X:ea S2,D2', 'A,X:ea X0,A', 'B,X:ea X0,B', 'S1,X:eax Y:eay,D2', 'S1,X:eax S2,Y:eay'
- if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_A)
+ if (*tok == REG56_X0 && tok[1] == ',' && tok[2] == REG56_A)
{
// 'A,X:ea X0,A'
if (ea1 == DSP_EA_ABS)
inst = 0b0000100000000000 | ea1 | (0 << 8);
return inst;
}
- else if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_B)
+ else if (*tok == REG56_X0 && tok[1] == ',' && tok[2] == REG56_B)
{
// 'B,X:ea X0,B'
if (ea1 == DSP_EA_ABS)
inst = 0b0000100100000000 | ea1 | (1 << 8);
return inst;
}
- else if (*tok == KW_A || *tok == KW_B)
+ else if (*tok == REG56_A || *tok == REG56_B)
{
// 'S1,X:ea S2,D2', 'S1,X:eax S2,Y:eay'
switch (S1)
default: return error("unrecognised X:R parallel move syntax: S1 can only be x0, x1, a or b in 'S1,X:ea S2,D2'");
}
- if (tok[1] == ',' && tok[2] == KW_Y)
+ if (tok[1] == ',' && tok[2] == REG56_Y)
{
// 'S1,X:eax S2,Y:eay'
return check_x_y(ea1, S1);
switch (*tok++)
{
- case KW_A: S2 = 0 << 9; break;
- case KW_B: S2 = 1 << 9; break;
+ case REG56_A: S2 = 0 << 9; break;
+ case REG56_B: S2 = 1 << 9; break;
default: return error("unrecognised X:R parallel move syntax: expected a or b after 'S1,X:eax'");
}
if (*tok++ != ',')
return error("unrecognised X:R parallel move syntax: expected ',' after 'S1,X:eax S2'");
- if (*tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
- if (*tok++ == KW_Y0)
+ if (*tok++ == REG56_Y0)
D2 = 0 << 8;
else
D2 = 1 << 8;
else
return error("unrecognised X:R parallel move syntax: expected y0 or y1 after 'X:eax,D1 S2,'");
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
// 'S1,X:eax Y:eay,D2'
return check_x_y(ea1, S1);
}
- else if (*tok == KW_Y0 || *tok == KW_Y1)
+ else if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
// 'S1,X:eax S2,Y:eay'
return check_x_y(ea1, S1);
// It might be X:aa but we're not 100% sure yet.
// If it is, the only possible syntax here is 'X:aa,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (*tok == ',' && ((*(tok + 1) >= KW_X0 && *(tok + 1) <= KW_N7) || (*(tok + 1) >= KW_R0 && *(tok + 1) <= KW_R7) || (*(tok + 1) >= KW_A0 && *(tok + 1) <= KW_A2)) && *(tok + 2) == EOL)
+ if (*tok == ',' && ((*(tok + 1) >= REG56_X0 && *(tok + 1) <= REG56_N7) || (*(tok + 1) >= REG56_R0 && *(tok + 1) <= REG56_R7) || (*(tok + 1) >= REG56_A0 && *(tok + 1) <= REG56_A2)) && *(tok + 2) == EOL)
{
// Yup, we're good to go - 'X:aa,D' it is
tok++;
if (*tok++ != ',')
return error("unrecognised X: parallel move syntax: expected ',' after 'X:ea'");
- if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))
+ if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2))
{
D1 = SDreg(*tok++);
else
{
// 'X:ea,D1 S2,D2'
- if (*tok == KW_A || *tok == KW_B)
+ if (*tok == REG56_A || *tok == REG56_B)
{
S2 = SDreg(*tok++);
if (*tok++ != ',')
return error("unrecognised X:R parallel move syntax: expected comma after X:ea,D1 S2");
- if (*tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
D2 = SDreg(*tok++);
// It might be 'X:(Rn..)..,D' but we're not 100% sure yet.
// If it is, the only possible syntax here is 'X:ea,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) && *(tok + 1) == EOL)
+ if (((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) && *(tok + 1) == EOL)
{
//'X:ea,D'
D1 = SDreg(*tok++);
// 'X:eax,D1 Y:eay,D2', 'X:eax,D1 S2,Y:eay' or 'X:ea,D1 S2,D2'
// Check ahead for S2,D2 - if that's true then we have 'X:ea,D1 S2,D2'
- if ((*tok == KW_X0 || *tok == KW_X1 || *tok == KW_A || *tok == KW_B) && (*(tok + 1) == KW_A || *(tok + 1) == KW_B) && (*(tok + 2) == ',') && (*(tok + 3) == KW_Y0 || (*(tok + 3) == KW_Y1)))
+ if ((*tok == REG56_X0 || *tok == REG56_X1 || *tok == REG56_A || *tok == REG56_B) && (*(tok + 1) == REG56_A || *(tok + 1) == REG56_B) && (*(tok + 2) == ',') && (*(tok + 3) == REG56_Y0 || (*(tok + 3) == REG56_Y1)))
{
// 'X:ea,D1 S2,D2'
// Check if D1 is x0, x1, a or b
switch (*tok++)
{
- case KW_X0: D1 = 0 << 10; break;
- case KW_X1: D1 = 1 << 10; break;
- case KW_A: D1 = 2 << 10; break;
- case KW_B: D1 = 3 << 10; break;
+ case REG56_X0: D1 = 0 << 10; break;
+ case REG56_X1: D1 = 1 << 10; break;
+ case REG56_A: D1 = 2 << 10; break;
+ case REG56_B: D1 = 3 << 10; break;
default: return error("unrecognised X:R parallel move syntax: expected x0, x1, a or b after 'X:eax,'");
}
switch (*tok++)
{
- case KW_A: S2 = 0 << 9; break;
- case KW_B: S2 = 1 << 9; break;
+ case REG56_A: S2 = 0 << 9; break;
+ case REG56_B: S2 = 1 << 9; break;
default: return error("unrecognised X:R parallel move syntax: expected a or b after 'X:eax,D1 '");
}
if (*tok++ != ',')
return error("unrecognised X:R parallel move syntax: expected ',' after 'X:eax,D1 S2'");
- if (*tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
- if (*tok++ == KW_Y0)
+ if (*tok++ == REG56_Y0)
D2 = 0 << 8;
else
D2 = 1 << 8;
return inst;
}
- if (*tok == ',' && ((*(tok + 1) >= KW_X0 && *(tok + 1) <= KW_N7) || (*(tok + 1) >= KW_R0 && *(tok + 1) <= KW_R7) || (*(tok + 1) >= KW_A0 && *(tok + 1) <= KW_A2)) && *(tok + 2) == EOL)
+ if (*tok == ',' && ((*(tok + 1) >= REG56_X0 && *(tok + 1) <= REG56_N7) || (*(tok + 1) >= REG56_R0 && *(tok + 1) <= REG56_R7) || (*(tok + 1) >= REG56_A0 && *(tok + 1) <= REG56_A2)) && *(tok + 2) == EOL)
{
// Yup, we're good to go - 'Y:aa,D' it is
tok++;
if (D1 == 0 && S1 == 0)
{
// 'Y:ea,D'
- if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))
+ if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2))
{
D1 = SDreg(*tok++);
else
{
// 'S1,D1 Y:ea,D2'
- if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_A || *tok == REG56_B || *tok == REG56_Y0 || *tok == REG56_Y1)
{
D2 = SDreg(*tok++);
inst |= ea1;
switch (*tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
- case KW_A: D2 = 2 << 8; break;
- case KW_B: D2 = 3 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
+ case REG56_A: D2 = 2 << 8; break;
+ case REG56_B: D2 = 3 << 8; break;
default: return error("unrecognised R:Y parallel move syntax: D2 can only be y0, y1, a or b after 'S1,D1 Y:ea'");
}
// It might be 'Y:(Rn..)..,D' but we're not 100% sure yet.
// If it is, the only possible syntax here is 'Y:ea,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) && *(tok + 1) == EOL)
+ if (((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) && *(tok + 1) == EOL)
{
//'Y:ea,D'
D1 = SDreg(*tok++);
if (dspImmedEXVAL < 0x40 && force_imm != NUM_FORCE_LONG)
{
// 'S,L:aa'
- if (S1 == KW_A)
+ if (S1 == REG56_A)
S1 = 4;
- else if (S1 == KW_B)
+ else if (S1 == REG56_B)
S1 = 5;
else
S1 &= 7;
else
{
// 'S,L:ea'
- if (S1 == KW_A)
+ if (S1 == REG56_A)
S1 = 4;
- else if (S1 == KW_B)
+ else if (S1 == REG56_B)
S1 = 5;
else
S1 &= 7;
return error("unrecognised L: parallel move syntax: expected ',' after 'L:ea/L:aa'");
// Check for allowed registers for D (a0, b0, x, y, a, b, ab or ba)
- if (!((*tok >= KW_A10 && *(tok + 1) <= KW_BA) || (*tok >= KW_A && *tok <= KW_B)))
+ if (!((*tok >= REG56_A10 && *(tok + 1) <= REG56_BA) || (*tok >= REG56_A && *tok <= REG56_B)))
return error("unrecognised L: parallel move syntax: expected a0, b0, x, y, a, b, ab or ba after 'L:ea/L:aa'");
if (dspImmedEXVAL < (1 << 6) && (dspImmedEXATTR&DEFINED))
l_aa:
immreg = *tok++;
- if (immreg == KW_A)
+ if (immreg == REG56_A)
immreg = 4;
- else if (immreg == KW_B)
+ else if (immreg == REG56_B)
immreg = 5;
else
immreg &= 7;
// 'L:ea,D'
D1 = *tok++;
- if (D1 == KW_A)
+ if (D1 == REG56_A)
D1 = 4;
- else if (D1 == KW_B)
+ else if (D1 == REG56_B)
D1 = 5;
else
D1 &= 7;
// 'S,L:ea'
inst = 0b0100000001000000;
- if (S1 == KW_A)
+ if (S1 == REG56_A)
S1 = 4;
- else if (S1 == KW_B)
+ else if (S1 == REG56_B)
S1 = 5;
else
S1 &= 7;
// It might be 'L:(Rn..)..,D' but we're not 100% sure yet.
// If it is, the only possible syntax here is 'L:ea,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (((*tok >= KW_A10 && *tok <= KW_BA) || (*tok >= KW_A && *tok <= KW_B)) && *(tok + 1) == EOL)
+ if (((*tok >= REG56_A10 && *tok <= REG56_BA) || (*tok >= REG56_A && *tok <= REG56_B)) && *(tok + 1) == EOL)
{
//'L:ea,D'
D1 = *tok++;
- if (D1 == KW_A)
+ if (D1 == REG56_A)
D1 = 4;
- else if (D1 == KW_B)
+ else if (D1 == REG56_B)
D1 = 5;
else
D1 &= 7;
if (*tok++ != '(')
return error(ea_errors[strings][0]);
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
// We got '-(Rn' so mark it down
- ea = DSP_EA_PREDEC1 | (*tok++ - KW_R0);
+ ea = DSP_EA_PREDEC1 | (*tok++ - REG56_R0);
if (*tok++ != ')')
return error(ea_errors[strings][1]);
// Checking for ea of type (Rn)
tok++;
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
// We're in 'X:(Rn..)..,D', 'X:(Rn..)..,D1 Y:eay,D2', 'X:(Rn..)..,D1 S2,Y:eay'
- ea = *tok++ - KW_R0;
+ ea = *tok++ - REG56_R0;
if (*tok == '+')
{
// '(Rn+Nn)'
tok++;
- if (*tok < KW_N0 || *tok > KW_N7)
+ if (*tok < REG56_N0 || *tok > REG56_N7)
return error(ea_errors[strings][3]);
if ((*tok++ & 7) != ea)
ea |= DSP_EA_POSTINC1;
return ea;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea)
}
else
{
- if (*tok >= KW_N0 && *tok <= KW_N7)
+ if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea)
ea |= DSP_EA_POSTDEC1;
return ea;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)-Nn
if ((*tok++ & 7) != ea)
}
else
{
- if (*tok >= KW_N0 && *tok <= KW_N7)
+ if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)-Nn
if ((*tok++ & 7) != ea)
if (*tok++ != ',')
return error("expected comma");
- if (!((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)))
+ if (!((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)))
return error("expected x0,x1,y0,y1,a0,b0,a2,b2,a1,b1,a,b,r0-r7,n0-n7 after immediate");
immreg = SDreg(*tok++);
switch (*tok++)
{
- case KW_A: S2 = 0 << 9; break;
- case KW_B: S2 = 1 << 9; break;
+ case REG56_A: S2 = 0 << 9; break;
+ case REG56_B: S2 = 1 << 9; break;
default: return error("unrecognised X:R parallel move syntax: S2 can only be A or B in '#xxxxxx,D1 S2,D2'"); break;
}
switch (*tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
default: return error("unrecognised X:R parallel move syntax: D2 can only be Y0 or Y1 in '#xxxxxx,D1 S2,D2'"); break;
}
return inst;
}
}
- else if (*tok == KW_X)
+ else if (*tok == REG56_X)
{
if (tok[1] == ',')
// Hey look, it's just the register X and not the addressing mode - fall through to general case
// 'X:ea,D' or 'X:aa,D' or 'X:ea,D1 S2,D2' or 'X:eax,D1 Y:eay,D2' or 'X:eax,D1 S2,Y:eay'
return parse_x(1, 0b0100000000000000, 0, 1);
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
if (tok[1] == ',')
// Hey look, it's just the register y and not the addressing mode - fall through to general case
// 'Y:ea,D' or 'Y:aa,D'
return parse_y(0b0100100010000000, 0, 0, 0);
}
- else if (*tok == KW_L)
+ else if (*tok == REG56_L)
{
// 'L:ea,D' or 'L:aa,D'
tok++;
return parse_l(1, 0b0100000011000000, 0);
}
- else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2) || (*tok >= KW_A10 && *tok <= KW_BA))
+ else if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2) || (*tok >= REG56_A10 && *tok <= REG56_BA))
{
// Everything else - brace for impact!
// R: 'S,D'
if (*tok++ != ',')
return error("Comma expected after 'S')");
- if (*tok == KW_X)
+ if (*tok == REG56_X)
{
// 'S,X:ea' 'S,X:aa' 'S,X:ea S2,D2' 'S1,X:eax Y:eay,D2' 'S1,X:eax S2,Y:eay'
// 'A,X:ea X0,A' 'B,X:ea X0,B'
return parse_x(0, 0b0100000000000000, S1, 1);
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
// 'S,Y:ea' 'S,Y:aa'
tok++;
return parse_y(0b000000000000000, S1, 0, 0);
}
- else if (*tok == KW_L)
+ else if (*tok == REG56_L)
{
// 'S,L:ea' 'S,L:aa'
tok++;
return parse_l(1, 0b0000000000000000, L_S1);
}
- else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))
+ else if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2))
{
// 'S,D'
// 'S1,D1 Y:ea,D2' 'S1,D1 S2,Y:ea' 'S1,D1 #xxxxxx,D2'
inst |= (S1 << 5) | (D1);
return inst;
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
// 'S1,D1 Y:ea,D2'
tok++;
return parse_y(0b0001000001000000, S1, D1, 0);
}
- else if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1)
+ else if (*tok == REG56_A || *tok == REG56_B || *tok == REG56_Y0 || *tok == REG56_Y1)
{
// 'Y0,A A,Y:ea' 'Y0,B B,Y:ea' 'S1,D1 S2,Y:ea'
S2 = SDreg(*tok++);
if (*tok++ != ',')
return error("unrecognised Y: parallel move syntax: expected ',' after Y0,A A");
- if (*tok++ != KW_Y)
+ if (*tok++ != REG56_Y)
return error("unrecognised Y: parallel move syntax: expected 'Y' after Y0,A A,");
if (*tok++ != ':')
if (*tok++ != ',')
return error("unrecognised Y: parallel move syntax: expected ',' after Y0,B B");
- if (*tok++ != KW_Y)
+ if (*tok++ != REG56_Y)
return error("unrecognised Y: parallel move syntax: expected 'Y' after Y0,B B,");
if (*tok++ != ':')
if (*tok++ != ',')
return error("unrecognised Y: parallel move syntax: expected ',' after S1,D1 S2");
- if (*tok++ != KW_Y)
+ if (*tok++ != REG56_Y)
return error("unrecognised Y: parallel move syntax: expected 'Y' after S1,D1 S2,");
if (*tok++ != ':')
// S1 is a or b, D1 is x0 or x1 and d2 is y0, y1, a or b
switch (*tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
- case KW_A: D2 = 2 << 8; break;
- case KW_B: D2 = 3 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
+ case REG56_A: D2 = 2 << 8; break;
+ case REG56_B: D2 = 3 << 8; break;
default: return error("unrecognised R:Y: parallel move syntax: D2 must be y0, y1, a or b in 'S1,D1 #xxxxxx,D2'");
}
// U 'ea' can only be '(Rn)-Nn', '(Rn)+Nn', '(Rn)-' or '(Rn)+'
tok++;
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
- ea1 = (*tok++ - KW_R0);
+ ea1 = (*tok++ - REG56_R0);
}
else
return error("unrecognised U parallel move syntax: expected 'Rn' after '('");
if (*tok == EOL)
// (Rn)+
ea1 |= 3 << 3;
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea1)
ea1 |= 2 << 3;
tok++;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)-Nn
if ((*tok++ & 7) != ea1)