-static void Op3B(void) // RTI
-{
- regs.cc = regs.RdMem(regs.s++);
- if (regs.cc&0x80) // If E flag set, pull all regs
- {
- regs.a = regs.RdMem(regs.s++); regs.b = regs.RdMem(regs.s++); regs.dp = regs.RdMem(regs.s++);
- regs.x = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.y = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.u = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
- regs.clock += 15;
- }
- else
- {
- regs.clock += 6;
- }
- regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
-}
-static void Op3C(void) // CWAI
-{
- regs.cc &= regs.RdMem(regs.pc++); regs.cc |= 0x80;
- regs.clock += 1000000; // Force interrupt
-}
-static void Op3D(void) // MUL
-{
- addr = regs.a * regs.b; regs.a = addr>>8; regs.b = addr&0xFF;
- (addr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
- (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
- regs.clock += 11;
-}
-static void Op3E(void) // RESET
-{
-}
-static void Op3F(void) // SWI
-{
-}
-static void Op40(void) // NEGA
-{
- regs.a = 256 - regs.a;
- (regs.a > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op43(void) // COMA
-{
- regs.a ^= 0xFF;
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op44(void) // LSRA
-{
- (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- regs.a >>= 1;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op46(void) // RORA
-{
- tmp = regs.a; regs.a = (tmp>>1) + (regs.cc&0x01)*128;
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op47(void) // ASRA
-{
- (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- regs.a >>= 1; // Do the shift
- if (regs.a&0x40) regs.a |= 0x80; // Set neg if it was set
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op48(void) // LSLA [Keep checking from here...]
-{
- (regs.a&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- regs.a <<= 1;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op49(void) // ROLA
-{
- tmp = regs.a; regs.a = (tmp<<1) + (regs.cc&0x01);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op4A(void) // DECA
-{
- regs.a--;
- (regs.a == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op4C(void) // INCA
- {
- regs.a++;
- (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op4D(void) // TSTA
- {
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op4F(void) // CLRA
-{
- regs.a = 0;
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 2;
-}
-static void Op50(void) // NEGB
- {
- regs.b = 256 - regs.b;
-// ((regs.b^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
- (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- regs.clock += 2;
- }
-static void Op53(void) // COMB
- {
- regs.b ^= 0xFF;
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op54(void) // LSRB
- {
- (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- regs.b >>= 1;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op56(void) // RORB
- {
- tmp = regs.b; regs.b = (regs.b >> 1) + (regs.cc&0x01)*128;
- (tmp&0x01 ? regs.cc |=0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op57(void) // ASRB
- {
- (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- regs.b >>= 1; // Do the shift
- if (regs.b&0x40) regs.b |= 0x80; // Set neg if it was set
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op58(void) // LSLB
- {
- (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- regs.b <<= 1;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op59(void) // ROLB
-{
- tmp = regs.b;
- regs.b = (tmp<<1) + (regs.cc&0x01);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op5A(void) // DECB
- {
- regs.b--;
- (regs.b == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op5C(void) // INCB
- {
- regs.b++;
- (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op5D(void) // TSTB
- {
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op5F(void) // CLRB
- {
- regs.b = 0;
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 2;
- }
-static void Op60(void) // NEG IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
- regs.WrMem(addr, res);
-// ((res^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
- (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- regs.clock += 6;
- }
-static void Op63(void) // COM IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr) ^ 0xFF;
- regs.WrMem(addr, tmp);
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op64(void) // LSR IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- tmp >>= 1; regs.WrMem(addr, tmp);
- regs.cc &= 0xF7; // CLN
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 6;
- }
-static void Op66(void) // ROR IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
- tmp = (tmp >> 1) + (regs.cc&0x01)*128;
- regs.WrMem(addr, tmp);
- (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op67(void) // ASR IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- tmp >>= 1;
- if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op68(void) // LSL IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- tmp <<= 1;
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op69(void) // ROL IDX
-{
- uint8 tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- tmp = (tmp2<<1) + (regs.cc&0x01);
- regs.WrMem(addr, tmp);
- (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
-}
-static void Op6A(void) // DEC IDX
- {
- uint8 tmp; uint16 addr;
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr) - 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op6C(void) // INC IDX
- {
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- tmp = regs.RdMem(addr) + 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op6D(void) // TST IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void Op6E(void) // JMP IDX
-{
- regs.pc = DecodeIDX(regs.RdMem(regs.pc++));
- regs.clock += 3;
-}
-static void Op6F(void) // CLR IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, 0);
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 6;
-}
-static void Op70(void) // NEG ABS
- {
- addr = FetchW();
- tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
- regs.WrMem(addr, res);
- (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
- regs.clock += 7;
- }
-static void Op73(void) // COM ABS
- {
- addr = FetchW();
- tmp = regs.RdMem(addr) ^ 0xFF;
- regs.WrMem(addr, tmp);
- regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op74(void) // LSR ABS
- {
- addr = FetchW();
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
- tmp >>= 1; regs.WrMem(addr, tmp);
- regs.cc &= 0xF7; // CLN
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- regs.clock += 7;
- }
-static void Op76(void) // ROR ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
- tmp = (tmp >> 1) + (regs.cc&0x01)*128;
- regs.WrMem(addr, tmp);
- (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op77(void) // ASR ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr);
- (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
- tmp >>= 1;
- if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op78(void) // LSL ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr);
- (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- tmp <<= 1;
- regs.WrMem(addr, tmp);
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op79(void) // ROL ABS
-{
- uint8 tmp2 = regs.RdMem(FetchW());
- tmp = (tmp2<<1) + (regs.cc&0x01);
- regs.WrMem(addr, tmp);
- (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
-}
-static void Op7A(void) // DEC ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr) - 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-static void Op7C(void) // INC ABS
- {
- uint8 tmp; uint16 addr;
- addr = FetchW();
- tmp = regs.RdMem(addr) + 1;
- regs.WrMem(addr, tmp);
- (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 7;
- }
-
-static void Op7D(void) // TST ABS
-{
- uint8 tmp = regs.RdMem(FetchW());
-
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 7;
-}
-
-static void Op7E(void) // JMP ABS
-{
- regs.pc = FetchW();
- regs.clock += 3;
-}
-static void Op7F(void) // CLR ABS
- {
- regs.WrMem(FetchW(), 0);
- regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
- regs.clock += 7;
- }
-static void Op80(void) // SUBA #
-{
- uint8 tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
- regs.a -= tmp;
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op81(void) // CMPA #
-{
- tmp = regs.RdMem(regs.pc++);
- uint8 db = regs.a - tmp;
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op82(void) // SBCA #
-{
- tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void Op83(void) // SUBD #
-{
- addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- dr -= addr;
- (ds < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 4;
-}
-static void Op84(void) // ANDA #
- {
- regs.a &= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op85(void) // BITA #
- {
- tmp = regs.a & regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op86(void) // LDA #
- {
- regs.a = regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op88(void) // EORA #
- {
- regs.a ^= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op89(void) // ADCA #
-{
- tmp = regs.RdMem(regs.pc++);
- addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
- regs.clock += 2;
-}
-static void Op8A(void) // ORA #
- {
- regs.a |= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void Op8B(void) // ADDA #
-{
- tmp = regs.RdMem(regs.pc++); addr = regs.a + tmp;
- (addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 2;
-}
-static void Op8C(void) // CMPX #
-{
- addr = FetchW();
- uint16 dw = regs.x - addr;
- (regs.x < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-
-static void Op8D(void) // Bregs.s
-{
- uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
- regs.WrMem(--regs.s, regs.pc & 0xFF);
- regs.WrMem(--regs.s, regs.pc >> 8);
- regs.pc += word;
-
- regs.clock += 7;
-}
-
-static void Op8E(void) // LDX #
- {
- regs.x = FetchW();
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 3;
- }
-static void Op90(void) // SUBA DP
- {
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
- regs.a -= tmp;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void Op91(void) // CMPA DP
- {
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- uint8 db = regs.a - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void Op92(void) // SBCA DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void Op93(void) // SUBD DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- dr -= adr2;
- (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 6;
-}
-static void Op94(void) // ANDA DP
-{
- regs.a &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 4;
-}
-static void Op95(void) // BITA DP
- {
- tmp = regs.a & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op96(void) // LDA DP
-{
- regs.a = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xF1; // CLN CLZ CLV
- if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 4;
-}
-static void Op97(void) // STA DP
- {
- regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.a);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op98(void) // EORA DP
- {
- regs.a ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op99(void) // ADCA DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
- regs.clock += 4;
-}
-static void Op9A(void) // ORA DP
- {
- regs.a |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void Op9B(void) // ADDA DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (uint16)regs.a + (uint16)tmp;
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 4;
-}
-static void Op9C(void) // CMPX DP
- {
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.x - adr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.x < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^adr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.clock += 6;
- }
-static void Op9D(void) // JSR DP
- {
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // JSR to DP location...
- regs.clock += 7;
- }
-static void Op9E(void) // LDX DP
- {
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void Op9F(void) // STX DP
- {
- addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpA0(void) // SUBA IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
- regs.a -= tmp;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void OpA1(void) // CMPA IDX
- {
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- uint8 db = regs.a - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
- }
-static void OpA2(void) // SBCA IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpA3(void) // SUBD IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++)); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- dr -= adr2;
- (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 6;
-}
-static void OpA4(void) // ANDA IDX
- {
- regs.a &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpA5(void) // BITA IDX
- {
- tmp = regs.a & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpA6(void) // LDA IDX
-{
- regs.a = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 4;
-}
-static void OpA7(void) // STA IDX
-{
- regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.a);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 4;
-}
-static void OpA8(void) // EORA IDX
- {
- regs.a ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpA9(void) // ADCA IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 4;
-}
-static void OpAA(void) // ORA IDX
-{
- regs.a |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpAB(void) // ADDA IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (uint16)regs.a + (uint16)tmp;
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 4;
-}
-static void OpAC(void) // CMPX IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.x - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 6;
-}
-static void OpAD(void) // JSR IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // Jregs.s directly to IDX ptr
- regs.clock += 7;
-}
-static void OpAE(void) // LDX IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpAF(void) // STX IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.x == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.x&0x8000) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 5;
-}
-static void OpB0(void) // SUBA ABS
- {
- tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
- regs.a -= tmp;
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
- }
-static void OpB1(void) // CMPA ABS
- {
- tmp = regs.RdMem(FetchW());
- uint8 db = regs.a - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
- }
-static void OpB2(void) // SBCA ABS
-{
- tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
- regs.a = regs.a - tmp - (regs.cc&0x01);
- (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB3(void) // SUBD ABS
-{
- addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- dr -= adr2;
- (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 7;
-}
-static void OpB4(void) // ANDA ABS
-{
- regs.a &= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB5(void) // BITA ABS
-{
- tmp = regs.a & regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB6(void) // LDA ABS
-{
- regs.a = regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB7(void) // STA ABS
-{
- regs.WrMem(FetchW(), regs.a);
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB8(void) // EORA ABS
-{
- regs.a ^= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpB9(void) // ADCA ABS
-{
- tmp = regs.RdMem(FetchW());
- addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = addr; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 5;
-}
-static void OpBA(void) // ORA ABS
-{
- regs.a |= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpBB(void) // ADDA ABS
-{
- tmp = regs.RdMem(FetchW());
- addr = (uint16)regs.a + (uint16)tmp;
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.a = addr & 0xFF; // Set accumulator
- (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 5;
-}
-static void OpBC(void) // CMPX ABS
-{
- addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
- uint16 dw = regs.x - addr2;
- (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 7;
-}
-static void OpBD(void) // JSR ABS
-{
- addr = FetchW();
- regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
- regs.pc = addr; // Go to absolute address (Not indir)
- regs.clock += 8;
-}
-
-static void OpBE(void) // LDX ABS
-{
-// addr = FetchW();
-// regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.x = RdMemW(FetchW());
-
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 6;
-}
-
-static void OpBF(void) // STX ABS
-{
-// addr = FetchW();
-// regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
- WrMemW(FetchW(), regs.x);
-
- regs.cc &= 0xFD; // CLV
- (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
-
- regs.clock += 6;
-}
-
-static void OpC0(void) // SUBB #
- {
- tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 2;
- }
-static void OpC1(void) // CMPB #
- {
- tmp = regs.RdMem(regs.pc++);
- uint8 db = regs.b - tmp;
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpC2(void) // SBCB #
-{
- tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
-}
-static void OpC3(void) // ADDD #
-{
- addr = FetchW(); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
- dr += addr;
- (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- dr &= 0xFFFF;
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 4;
-}
-static void OpC4(void) // ANDB #
- {
- regs.b &= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpC5(void) // BITB #
-{
- tmp = regs.b & regs.RdMem(regs.pc++);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (tmp == 0) regs.cc |= 0x04; // Set Zero flag
- if (tmp&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 2;
-}
-static void OpC6(void) // LDB #
-{
- regs.b = regs.RdMem(regs.pc++);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.b == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.b&0x80) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 2;
-}
-static void OpC8(void) // EORB #
- {
- regs.b ^= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpC9(void) // ADCB #
-{
- tmp = regs.RdMem(regs.pc++);
- addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.b = addr & 0xFF; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 2;
-}
-static void OpCA(void) // ORB #
- {
- regs.b |= regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 2;
- }
-static void OpCB(void) // ADDB #
-{
- tmp = regs.RdMem(regs.pc++); addr = regs.b + tmp;
- (addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.b = addr & 0xFF; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 2;
-}
-static void OpCC(void) // LDD #
-{
- regs.a = regs.RdMem(regs.pc++); regs.b = regs.RdMem(regs.pc++);
- regs.cc &= 0xFD; // CLV
- ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 3;
-}
-static void OpCE(void) // LDU #
-{
- regs.u = FetchW();
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 3;
-}
-static void OpD0(void) // SUBB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpD1(void) // CMPB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- uint8 db = regs.b - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpD2(void) // SBCB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpD3(void) // ADDD DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
- dr += adr2;
- (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- dr &= 0xFFFF;
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 6;
-}
-static void OpD4(void) // ANDB DP
- {
- regs.b &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpD5(void) // BITB DP
- {
- tmp = regs.b & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpD6(void) // LDB DP
-{
- regs.b = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpD7(void) // STB DP
- {
- regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.b);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpD8(void) // EORB DP
- {
- regs.b ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpD9(void) // ADCB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.b = addr; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 4;
-}
-static void OpDA(void) // ORB DP
- {
- regs.b |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpDB(void) // ADDB DP
-{
- tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
- addr = (uint16)regs.b + (uint16)tmp;
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.b = addr & 0xFF; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 4;
-}
-static void OpDC(void) // LDD DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpDD(void) // STD DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
- regs.cc &= 0xFD; // CLV
- ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpDE(void) // LDU DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpDF(void) // STU DP
-{
- addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
- regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpE0(void) // SUBB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpE1(void) // CMPB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- uint8 db = regs.b - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 4;
-}
-static void OpE2(void) // SBCB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpE3(void) // ADDD IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++)); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
- dr += adr2;
- (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- dr &= 0xFFFF;
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 6;
-}
-static void OpE4(void) // ANDB IDX
- {
- regs.b &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpE5(void) // BITB IDX
- {
- tmp = regs.b & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpE6(void) // LDB IDX
- {
- regs.b = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpE7(void) // STB IDX
-{
- regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.b);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.b == 0) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.b&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 4;
-}
-static void OpE8(void) // EORB IDX
- {
- regs.b ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpE9(void) // ADCB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.b = addr; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 4;
-}
-static void OpEA(void) // ORB IDX
- {
- regs.b |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 4;
- }
-static void OpEB(void) // ADDB IDX
-{
- tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
- addr = (uint16)regs.b + (uint16)tmp;
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.b = addr; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 4;
-}
-static void OpEC(void) // LDD IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpED(void) // STD IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
- regs.cc &= 0xF1; // CLV CLZ CLZ
- if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag
- if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
- regs.clock += 5;
-}
-static void OpEE(void) // LDU IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 5;
-}
-static void OpEF(void) // STU IDX
-{
- addr = DecodeIDX(regs.RdMem(regs.pc++));
- regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
- regs.cc &= 0xF1; // CLV CLZ CLN
- if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag
- if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag
- regs.clock += 5;
-}
-static void OpF0(void) // SUBB ABS
- {
- tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
- regs.b -= tmp;
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- }
-static void OpF1(void) // CMPB ABS
- {
- tmp = regs.RdMem(FetchW());
- uint8 db = regs.b - tmp;
- (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
- }
-static void OpF2(void) // SBCB ABS
-{
- tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
- regs.b = regs.b - tmp - (regs.cc&0x01);
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
- regs.clock += 5;
-}
-static void OpF3(void) // ADDD ABS
-{
- addr = FetchW(); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
- uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
- dr += adr2;
- (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
- dr &= 0xFFFF;
- (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
- regs.a = dr>>8; regs.b = dr&0xFF;
- regs.clock += 7;
-}
-static void OpF4(void) // ANDB ABS
- {
- regs.b &= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF5(void) // BITB ABS
- {
- tmp = regs.b & regs.RdMem(FetchW());
- regs.cc &= 0xFD; // Clear oVerflow flag
- (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF6(void) // LDB ABS
- {
- regs.b = regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF7(void) // STB ABS
- {
- regs.WrMem(FetchW(), regs.b);
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF8(void) // EORB ABS
- {
- regs.b ^= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpF9(void) // ADCB ABS
-{
- tmp = regs.RdMem(FetchW());
- addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.b = addr & 0xFF; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 5;
-}
-static void OpFA(void) // ORB ABS
- {
- regs.b |= regs.RdMem(FetchW());
- regs.cc &= 0xFD; // CLV
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 5;
- }
-static void OpFB(void) // ADDB ABS
-{
- tmp = regs.RdMem(FetchW());
- addr = (uint16)regs.b + (uint16)tmp;
- (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
- ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
- ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
- regs.b = addr & 0xFF; // Set accumulator
- (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
- (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
- regs.clock += 5;
-}
-static void OpFC(void) // LDD ABS
- {
- addr = FetchW();
- regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void OpFD(void) // STD ABS
- {
- addr = FetchW();
- regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
- regs.cc &= 0xFD; // CLV
- ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void OpFE(void) // LDU ABS
- {
- addr = FetchW();
- regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-static void OpFF(void) // STU ABS
- {
- addr = FetchW();
- regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
- regs.cc &= 0xFD; // CLV
- (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
- (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
- regs.clock += 6;
- }
-
-//
-// Page one opcodes' execute code
-//