+// M68K_show_context();
+// log_done();
+// exit(0);
+//}
+ if (start)
+ {
+ m68k_disassemble(buffer, m68kPC, M68K_CPU_TYPE_68000);
+ WriteLog("%08X: %s \t\tD0=%08X, A0=%08X, D1=%08X, A1=%08X\n", m68kPC, buffer, m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_A1));
+ }//*/
+
+/* if (m68kPC == 0x803F16)
+ {
+ WriteLog("M68K: Registers found at $803F16:\n");
+ WriteLog("\t68K PC=%06X\n", m68k_get_reg(NULL, M68K_REG_PC));
+ for(int i=M68K_REG_D0; i<=M68K_REG_D7; i++)
+ WriteLog("\tD%i = %08X\n", i-M68K_REG_D0, m68k_get_reg(NULL, (m68k_register_t)i));
+ WriteLog("\n");
+ for(int i=M68K_REG_A0; i<=M68K_REG_A7; i++)
+ WriteLog("\tA%i = %08X\n", i-M68K_REG_A0, m68k_get_reg(NULL, (m68k_register_t)i));
+ }*/
+//Looks like the DSP is supposed to return $12345678 when it finishes its validation routine...
+// !!! Investigate !!!
+/*extern bool doDSPDis;
+ static bool disgo = false;
+ if (m68kPC == 0x50222)
+ {
+ // CD BIOS hacking
+// WriteLog("M68K: About to stuff $12345678 into $F1B000 (=%08X)...\n", DSPReadLong(0xF1B000, M68K));
+// DSPWriteLong(0xF1B000, 0x12345678, M68K);
+// disgo = true;
+ }
+ if (m68kPC == 0x5000)
+// doDSPDis = true;
+ disgo = true;
+ if (disgo)
+ {
+ static char buffer[2048];
+ m68k_disassemble(buffer, m68kPC, M68K_CPU_TYPE_68000);
+ WriteLog("%08X: %s", m68kPC, buffer);
+ WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X, D1=%08X, D2=%08X\n",
+ m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1),
+ m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2));
+ }//*/
+/* if (m68kPC == 0x82E1A)
+ {
+ static char buffer[2048];
+ m68k_disassemble(buffer, m68kPC, 0);//M68K_CPU_TYPE_68000);
+ WriteLog("--> [Routine start] %08X: %s", m68kPC, buffer);
+ WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X(cmd), D1=%08X(# bytes), D2=%08X\n",
+ m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1),
+ m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2));
+ }//*/
+/* if (m68kPC == 0x82E58)
+ WriteLog("--> [Routine end]\n");
+ if (m68kPC == 0x80004)
+ {
+ WriteLog("--> [Calling BusWrite2] D2: %08X\n", m68k_get_reg(NULL, M68K_REG_D2));
+// m68k_set_reg(M68K_REG_D2, 0x12345678);
+ }//*/
+
+#ifdef LOG_CD_BIOS_CALLS
+/*
+CD_init:: -> $3000
+BIOS_VER:: -> $3004
+CD_mode:: -> $3006
+CD_ack:: -> $300C
+CD_jeri:: -> $3012
+CD_spin:: -> $3018
+CD_stop:: -> $301E
+CD_mute:: -> $3024
+CD_umute:: -> $302A
+CD_paus:: -> $3030
+CD_upaus:: -> $3036
+CD_read:: -> $303C
+CD_uread:: -> $3042
+CD_setup:: -> $3048
+CD_ptr:: -> $304E
+CD_osamp:: -> $3054
+CD_getoc:: -> $305A
+CD_initm:: -> $3060
+CD_initf:: -> $3066
+CD_switch:: -> $306C
+*/
+ if (m68kPC == 0x3000)
+ WriteLog("M68K: CD_init\n");
+ else if (m68kPC == 0x3006 + (6 * 0))
+ WriteLog("M68K: CD_mode\n");
+ else if (m68kPC == 0x3006 + (6 * 1))
+ WriteLog("M68K: CD_ack\n");
+ else if (m68kPC == 0x3006 + (6 * 2))
+ WriteLog("M68K: CD_jeri\n");
+ else if (m68kPC == 0x3006 + (6 * 3))
+ WriteLog("M68K: CD_spin\n");
+ else if (m68kPC == 0x3006 + (6 * 4))
+ WriteLog("M68K: CD_stop\n");
+ else if (m68kPC == 0x3006 + (6 * 5))
+ WriteLog("M68K: CD_mute\n");
+ else if (m68kPC == 0x3006 + (6 * 6))
+ WriteLog("M68K: CD_umute\n");
+ else if (m68kPC == 0x3006 + (6 * 7))
+ WriteLog("M68K: CD_paus\n");
+ else if (m68kPC == 0x3006 + (6 * 8))
+ WriteLog("M68K: CD_upaus\n");
+ else if (m68kPC == 0x3006 + (6 * 9))
+ WriteLog("M68K: CD_read\n");
+ else if (m68kPC == 0x3006 + (6 * 10))
+ WriteLog("M68K: CD_uread\n");
+ else if (m68kPC == 0x3006 + (6 * 11))
+ WriteLog("M68K: CD_setup\n");
+ else if (m68kPC == 0x3006 + (6 * 12))
+ WriteLog("M68K: CD_ptr\n");
+ else if (m68kPC == 0x3006 + (6 * 13))
+ WriteLog("M68K: CD_osamp\n");
+ else if (m68kPC == 0x3006 + (6 * 14))
+ WriteLog("M68K: CD_getoc\n");
+ else if (m68kPC == 0x3006 + (6 * 15))
+ WriteLog("M68K: CD_initm\n");
+ else if (m68kPC == 0x3006 + (6 * 16))
+ WriteLog("M68K: CD_initf\n");
+ else if (m68kPC == 0x3006 + (6 * 17))
+ WriteLog("M68K: CD_switch\n");
+
+ if (m68kPC >= 0x3000 && m68kPC <= 0x306C)
+ WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X, D1=%08X, D2=%08X\n",
+ m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1),
+ m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2));
+#endif
+
+#ifdef ABORT_ON_ILLEGAL_INSTRUCTIONS
+ if (!m68k_is_valid_instruction(m68k_read_memory_16(m68kPC), 0))//M68K_CPU_TYPE_68000))
+ {
+#ifndef ABORT_ON_OFFICIAL_ILLEGAL_INSTRUCTION
+ if (m68k_read_memory_16(m68kPC) == 0x4AFC)
+ {
+ // This is a kludge to let homebrew programs work properly (i.e., let the other processors
+ // keep going even when the 68K dumped back to the debugger or what have you).
+//dis no wok right!
+// m68k_set_reg(M68K_REG_PC, m68kPC - 2);
+// Try setting the vector to the illegal instruction...
+//This doesn't work right either! Do something else! Quick!
+// SET32(jaguar_mainRam, 0x10, m68kPC);
+
+ return;
+ }
+#endif
+
+ WriteLog("\nM68K encountered an illegal instruction at %08X!!!\n\nAborting!\n", m68kPC);
+ uint32 topOfStack = m68k_get_reg(NULL, M68K_REG_A7);
+ WriteLog("M68K: Top of stack: %08X. Stack trace:\n", JaguarReadLong(topOfStack));
+ uint32 address = topOfStack - (4 * 4 * 3);
+
+ for(int i=0; i<10; i++)
+ {
+ WriteLog("%06X:", address);
+
+ for(int j=0; j<4; j++)
+ {
+ WriteLog(" %08X", JaguarReadLong(address));
+ address += 4;
+ }
+
+ WriteLog("\n");
+ }
+
+ WriteLog("Jaguar: VBL interrupt is %s\n", ((TOMIRQEnabled(IRQ_VIDEO)) && (JaguarInterruptHandlerIsValid(64))) ? "enabled" : "disabled");
+ M68K_show_context();
+
+//temp
+// WriteLog("\n\n68K disasm\n\n");
+// jaguar_dasm(0x802000, 0x50C);
+// WriteLog("\n\n");
+//endoftemp
+
+ LogDone();
+ exit(0);
+ }//*/
+#endif
+}
+
+#if 0
+Now here be dragons...
+Here is how memory ranges are defined in the CoJag driver.
+Note that we only have to be concerned with 3 entities read/writing anything:
+The main CPU, the GPU, and the DSP. Everything else is unnecessary. So we can keep our main memory
+checking in jaguar.cpp, gpu.cpp and dsp.cpp. There should be NO checking in TOM, JERRY, etc. other than
+things that are entirely internal to those modules. This way we should be able to get a handle on all
+this crap which is currently scattered over Hell's Half Acre(tm).
+
+Also: We need to distinguish whether or not we need .b, .w, and .dw versions of everything, or if there
+is a good way to collapse that shit (look below for inspiration). Current method works, but is error prone.
+
+/*************************************
+ *
+ * Main CPU memory handlers
+ *
+ *************************************/
+
+static ADDRESS_MAP_START( m68020_map, ADDRESS_SPACE_PROGRAM, 32 )
+ AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_BASE(&jaguar_shared_ram) AM_SHARE(1)
+ AM_RANGE(0x800000, 0x9fffff) AM_ROM AM_REGION(REGION_USER1, 0) AM_BASE(&rom_base)
+ AM_RANGE(0xa00000, 0xa1ffff) AM_RAM
+ AM_RANGE(0xa20000, 0xa21fff) AM_READWRITE(eeprom_data_r, eeprom_data_w) AM_BASE(&generic_nvram32) AM_SIZE(&generic_nvram_size)
+ AM_RANGE(0xa30000, 0xa30003) AM_WRITE(watchdog_reset32_w)
+ AM_RANGE(0xa40000, 0xa40003) AM_WRITE(eeprom_enable_w)
+ AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w)
+ AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK(2)
+ AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", ide_controller32_r, ide_controller32_w)
+ AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE(jaguar_tom_regs32_r, jaguar_tom_regs32_w)
+ AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_BASE(&jaguar_gpu_clut) AM_SHARE(2)
+ AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
+ AM_RANGE(0xf02200, 0xf022ff) AM_READWRITE(jaguar_blitter_r, jaguar_blitter_w)
+ AM_RANGE(0xf03000, 0xf03fff) AM_MIRROR(0x008000) AM_RAM AM_BASE(&jaguar_gpu_ram) AM_SHARE(3)
+ AM_RANGE(0xf10000, 0xf103ff) AM_READWRITE(jaguar_jerry_regs32_r, jaguar_jerry_regs32_w)
+ AM_RANGE(0xf16000, 0xf1600b) AM_READ(cojag_gun_input_r) // GPI02
+ AM_RANGE(0xf17000, 0xf17003) AM_READ(status_r) // GPI03
+// AM_RANGE(0xf17800, 0xf17803) AM_WRITE(latch_w) // GPI04
+ AM_RANGE(0xf17c00, 0xf17c03) AM_READ(jamma_r) // GPI05
+ AM_RANGE(0xf1a100, 0xf1a13f) AM_READWRITE(dspctrl_r, dspctrl_w)
+ AM_RANGE(0xf1a140, 0xf1a17f) AM_READWRITE(jaguar_serial_r, jaguar_serial_w)
+ AM_RANGE(0xf1b000, 0xf1cfff) AM_RAM AM_BASE(&jaguar_dsp_ram) AM_SHARE(4)
+ADDRESS_MAP_END
+
+/*************************************
+ *
+ * GPU memory handlers
+ *
+ *************************************/
+
+static ADDRESS_MAP_START( gpu_map, ADDRESS_SPACE_PROGRAM, 32 )
+ AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE(1)
+ AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK(8)
+ AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK(9)
+ AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", ide_controller32_r, ide_controller32_w)
+ AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE(jaguar_tom_regs32_r, jaguar_tom_regs32_w)
+ AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE(2)
+ AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
+ AM_RANGE(0xf02200, 0xf022ff) AM_READWRITE(jaguar_blitter_r, jaguar_blitter_w)
+ AM_RANGE(0xf03000, 0xf03fff) AM_RAM AM_SHARE(3)
+ AM_RANGE(0xf10000, 0xf103ff) AM_READWRITE(jaguar_jerry_regs32_r, jaguar_jerry_regs32_w)
+ADDRESS_MAP_END
+
+/*************************************
+ *
+ * DSP memory handlers
+ *
+ *************************************/
+
+static ADDRESS_MAP_START( dsp_map, ADDRESS_SPACE_PROGRAM, 32 )
+ AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE(1)
+ AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK(8)
+ AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK(9)
+ AM_RANGE(0xf10000, 0xf103ff) AM_READWRITE(jaguar_jerry_regs32_r, jaguar_jerry_regs32_w)
+ AM_RANGE(0xf1a100, 0xf1a13f) AM_READWRITE(dspctrl_r, dspctrl_w)
+ AM_RANGE(0xf1a140, 0xf1a17f) AM_READWRITE(jaguar_serial_r, jaguar_serial_w)
+ AM_RANGE(0xf1b000, 0xf1cfff) AM_RAM AM_SHARE(4)
+ AM_RANGE(0xf1d000, 0xf1dfff) AM_READ(jaguar_wave_rom_r) AM_BASE(&jaguar_wave_rom)
+ADDRESS_MAP_END
+*/
+#endif
+
+//#define EXPERIMENTAL_MEMORY_HANDLING
+// Experimental memory mappage...
+// Dunno if this is a good approach or not, but it seems to make better
+// sense to have all this crap in one spot intstead of scattered all over
+// the place the way it is now.
+#ifdef EXPERIMENTAL_MEMORY_HANDLING
+// Needed defines...
+#define NEW_TIMER_SYSTEM
+
+/*
+uint8 jaguarMainRAM[0x400000]; // 68K CPU RAM
+uint8 jaguarMainROM[0x600000]; // 68K CPU ROM
+uint8 jaguarBootROM[0x040000]; // 68K CPU BIOS ROM--uses only half of this!
+uint8 jaguarCDBootROM[0x040000]; // 68K CPU CD BIOS ROM
+bool BIOSLoaded = false;
+bool CDBIOSLoaded = false;
+
+uint8 cdRAM[0x100];
+uint8 tomRAM[0x4000];
+uint8 jerryRAM[0x10000];
+static uint16 eeprom_ram[64];
+
+// NOTE: CD BIOS ROM is read from cartridge space @ $802000 (it's a cartridge, after all)
+*/
+
+enum MemType { MM_NOP = 0, MM_RAM, MM_ROM, MM_IO };
+
+// M68K Memory map/handlers
+uint32 {
+ { 0x000000, 0x3FFFFF, MM_RAM, jaguarMainRAM },
+ { 0x800000, 0xDFFEFF, MM_ROM, jaguarMainROM },
+// Note that this is really memory mapped I/O region...
+// { 0xDFFF00, 0xDFFFFF, MM_RAM, cdRAM },
+ { 0xDFFF00, 0xDFFF03, MM_IO, cdBUTCH }, // base of Butch == interrupt control register, R/W
+ { 0xDFFF04, 0xDFFF07, MM_IO, cdDSCNTRL }, // DSA control register, R/W
+ { 0xDFFF0A, 0xDFFF0B, MM_IO, cdDS_DATA }, // DSA TX/RX data, R/W
+ { 0xDFFF10, 0xDFFF13, MM_IO, cdI2CNTRL }, // i2s bus control register, R/W
+ { 0xDFFF14, 0xDFFF17, MM_IO, cdSBCNTRL }, // CD subcode control register, R/W
+ { 0xDFFF18, 0xDFFF1B, MM_IO, cdSUBDATA }, // Subcode data register A
+ { 0xDFFF1C, 0xDFFF1F, MM_IO, cdSUBDATB }, // Subcode data register B
+ { 0xDFFF20, 0xDFFF23, MM_IO, cdSB_TIME }, // Subcode time and compare enable (D24)
+ { 0xDFFF24, 0xDFFF27, MM_IO, cdFIFO_DATA }, // i2s FIFO data
+ { 0xDFFF28, 0xDFFF2B, MM_IO, cdI2SDAT2 }, // i2s FIFO data (old)
+ { 0xDFFF2C, 0xDFFF2F, MM_IO, cdUNKNOWN }, // Seems to be some sort of I2S interface
+
+ { 0xE00000, 0xE3FFFF, MM_ROM, jaguarBootROM },
+
+// { 0xF00000, 0xF0FFFF, MM_IO, TOM_REGS_RW },
+ { 0xF00050, 0xF00051, MM_IO, tomTimerPrescaler },
+ { 0xF00052, 0xF00053, MM_IO, tomTimerDivider },
+ { 0xF00400, 0xF005FF, MM_RAM, tomRAM }, // CLUT A&B: How to link these? Write to one writes to the other...
+ { 0xF00600, 0xF007FF, MM_RAM, tomRAM }, // Actually, this is a good approach--just make the reads the same as well
+ //What about LBUF writes???
+ { 0xF02100, 0xF0211F, MM_IO, GPUWriteByte }, // GPU CONTROL
+ { 0xF02200, 0xF0229F, MM_IO, BlitterWriteByte }, // BLITTER
+ { 0xF03000, 0xF03FFF, MM_RAM, GPUWriteByte }, // GPU RAM
+
+ { 0xF10000, 0xF1FFFF, MM_IO, JERRY_REGS_RW },
+
+/*
+ EEPROM:
+ { 0xF14001, 0xF14001, MM_IO_RO, eepromFOO }
+ { 0xF14801, 0xF14801, MM_IO_WO, eepromBAR }
+ { 0xF15001, 0xF15001, MM_IO_RW, eepromBAZ }
+
+ JOYSTICK:
+ { 0xF14000, 0xF14003, MM_IO, joystickFoo }
+ 0 = pad0/1 button values (4 bits each), RO(?)
+ 1 = pad0/1 index value (4 bits each), WO
+ 2 = unused, RO
+ 3 = NTSC/PAL, certain button states, RO
+
+JOYSTICK $F14000 Read/Write
+ 15.....8 7......0
+Read fedcba98 7654321q f-1 Signals J15 to J1
+ q Cartridge EEPROM output data
+Write exxxxxxm 76543210 e 1 = enable J7-J0 outputs
+ 0 = disable J7-J0 outputs
+ x don't care
+ m Audio mute
+ 0 = Audio muted (reset state)
+ 1 = Audio enabled
+ 7-4 J7-J4 outputs (port 2)
+ 3-0 J3-J0 outputs (port 1)
+JOYBUTS $F14002 Read Only
+ 15.....8 7......0
+Read xxxxxxxx rrdv3210 x don't care
+ r Reserved
+ d Reserved
+ v 1 = NTSC Video hardware
+ 0 = PAL Video hardware
+ 3-2 Button inputs B3 & B2 (port 2)
+ 1-0 Button inputs B1 & B0 (port 1)
+
+J4 J5 J6 J7 Port 2 B2 B3 J12 J13 J14 J15
+J3 J2 J1 J0 Port 1 B0 B1 J8 J9 J10 J11
+ 0 0 0 0
+ 0 0 0 1
+ 0 0 1 0
+ 0 0 1 1
+ 0 1 0 0
+ 0 1 0 1
+ 0 1 1 0
+ 0 1 1 1 Row 3 C3 Option # 9 6 3
+ 1 0 0 0
+ 1 0 0 1
+ 1 0 1 0
+ 1 0 1 1 Row 2 C2 C 0 8 5 2
+ 1 1 0 0
+ 1 1 0 1 Row 1 C1 B * 7 4 1
+ 1 1 1 0 Row 0 Pause A Up Down Left Right
+ 1 1 1 1
+
+0 bit read in any position means that button is pressed.
+C3 = C2 = 1 means std. Jag. cntrlr. or nothing attached.
+*/
+};
+
+void WriteByte(uint32 address, uint8 byte, uint32 who/*=UNKNOWN*/)
+{
+ // Not sure, but I think the system only has 24 address bits...
+ address &= 0x00FFFFFF;
+
+ // RAM ($000000 - $3FFFFF) 4M
+ if (address <= 0x3FFFFF)
+ jaguarMainRAM[address] = byte;
+ // hole ($400000 - $7FFFFF) 4M
+ else if (address <= 0x7FFFFF)
+ ; // Do nothing
+ // GAME ROM ($800000 - $DFFEFF) 6M - 256 bytes
+ else if (address <= 0xDFFEFF)
+ ; // Do nothing
+ // CDROM ($DFFF00 - $DFFFFF) 256 bytes
+ else if (address <= 0xDFFFFF)
+ {
+ cdRAM[address & 0xFF] = byte;
+#ifdef CDROM_LOG
+ if ((address & 0xFF) < 12 * 4)
+ WriteLog("[%s] ", BReg[(address & 0xFF) / 4]);
+ WriteLog("CDROM: %s writing byte $%02X at $%08X [68K PC=$%08X]\n", whoName[who], data, offset, m68k_get_reg(NULL, M68K_REG_PC));
+#endif
+ }
+ // BIOS ROM ($E00000 - $E3FFFF) 256K
+ else if (address <= 0xE3FFFF)
+ ; // Do nothing
+ // hole ($E40000 - $EFFFFF) 768K
+ else if (address <= 0xEFFFFF)
+ ; // Do nothing
+ // TOM ($F00000 - $F0FFFF) 64K
+ else if (address <= 0xF0FFFF)
+// ; // Do nothing
+ {
+ if (address == 0xF00050)
+ {
+ tomTimerPrescaler = (tomTimerPrescaler & 0x00FF) | ((uint16)byte << 8);
+ TOMResetPIT();
+ return;
+ }
+ else if (address == 0xF00051)
+ {
+ tomTimerPrescaler = (tomTimerPrescaler & 0xFF00) | byte;
+ TOMResetPIT();
+ return;
+ }
+ else if (address == 0xF00052)
+ {
+ tomTimerDivider = (tomTimerDivider & 0x00FF) | ((uint16)byte << 8);
+ TOMResetPIT();
+ return;
+ }
+ else if (address == 0xF00053)
+ {
+ tomTimerDivider = (tomTimerDivider & 0xFF00) | byte;
+ TOMResetPIT();
+ return;
+ }
+ else if (address >= 0xF00400 && address <= 0xF007FF) // CLUT (A & B)
+ {
+ // Writing to one CLUT writes to the other
+ address &= 0x5FF; // Mask out $F00600 (restrict to $F00400-5FF)
+ tomRAM[address] = tomRAM[address + 0x200] = byte;
+ return;
+ }
+ //What about LBUF writes???
+ else if ((address >= 0xF02100) && (address <= 0xF0211F)) // GPU CONTROL
+ {
+ GPUWriteByte(address, byte, who);
+ return;
+ }
+ else if ((address >= 0xF02200) && (address <= 0xF0229F)) // BLITTER
+ {
+ BlitterWriteByte(address, byte, who);
+ return;
+ }
+ else if ((address >= 0xF03000) && (address <= 0xF03FFF)) // GPU RAM
+ {
+ GPUWriteByte(address, byte, who);
+ return;
+ }
+
+ tomRAM[address & 0x3FFF] = byte;
+ }
+ // JERRY ($F10000 - $F1FFFF) 64K
+ else if (address <= 0xF1FFFF)
+// ; // Do nothing
+ {
+#ifdef JERRY_DEBUG
+ WriteLog("jerry: writing byte %.2x at 0x%.6x\n", byte, address);
+#endif
+ if ((address >= DSP_CONTROL_RAM_BASE) && (address < DSP_CONTROL_RAM_BASE+0x20))
+ {
+ DSPWriteByte(address, byte, who);
+ return;
+ }
+ else if ((address >= DSP_WORK_RAM_BASE) && (address < DSP_WORK_RAM_BASE+0x2000))
+ {
+ DSPWriteByte(address, byte, who);
+ return;
+ }
+ // SCLK ($F1A150--8 bits wide)
+//NOTE: This should be taken care of in DAC...
+ else if ((address >= 0xF1A152) && (address <= 0xF1A153))
+ {
+// WriteLog("JERRY: Writing %02X to SCLK...\n", data);
+ if ((address & 0x03) == 2)
+ JERRYI2SInterruptDivide = (JERRYI2SInterruptDivide & 0x00FF) | ((uint32)byte << 8);
+ else
+ JERRYI2SInterruptDivide = (JERRYI2SInterruptDivide & 0xFF00) | (uint32)byte;
+
+ JERRYI2SInterruptTimer = -1;
+#ifndef NEW_TIMER_SYSTEM
+ jerry_i2s_exec(0);
+#else
+ RemoveCallback(JERRYI2SCallback);
+ JERRYI2SCallback();
+#endif
+// return;
+ }
+ // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
+ else if (address >= 0xF1A148 && address <= 0xF1A157)
+ {
+ DACWriteByte(address, byte, who);
+ return;
+ }
+ else if (address >= 0xF10000 && address <= 0xF10007)
+ {
+#ifndef NEW_TIMER_SYSTEM
+ switch (address & 0x07)
+ {
+ case 0:
+ JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0x00FF) | (byte << 8);
+ JERRYResetPIT1();
+ break;
+ case 1:
+ JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0xFF00) | byte;
+ JERRYResetPIT1();
+ break;
+ case 2:
+ JERRYPIT1Divider = (JERRYPIT1Divider & 0x00FF) | (byte << 8);
+ JERRYResetPIT1();
+ break;
+ case 3:
+ JERRYPIT1Divider = (JERRYPIT1Divider & 0xFF00) | byte;
+ JERRYResetPIT1();
+ break;
+ case 4:
+ JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0x00FF) | (byte << 8);
+ JERRYResetPIT2();
+ break;
+ case 5:
+ JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0xFF00) | byte;
+ JERRYResetPIT2();
+ break;
+ case 6:
+ JERRYPIT2Divider = (JERRYPIT2Divider & 0x00FF) | (byte << 8);
+ JERRYResetPIT2();
+ break;
+ case 7:
+ JERRYPIT2Divider = (JERRYPIT2Divider & 0xFF00) | byte;
+ JERRYResetPIT2();
+ }
+#else
+WriteLog("JERRY: Unhandled timer write (BYTE) at %08X...\n", address);
+#endif
+ return;
+ }
+/* else if ((offset >= 0xF10010) && (offset <= 0xF10015))
+ {
+ clock_byte_write(offset, byte);
+ return;
+ }//*/
+ // JERRY -> 68K interrupt enables/latches (need to be handled!)
+ else if (address >= 0xF10020 && address <= 0xF10023)
+ {
+WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%02X to $%08X!\n", byte, address);
+ }
+/* else if ((offset >= 0xF17C00) && (offset <= 0xF17C01))
+ {
+ anajoy_byte_write(offset, byte);
+ return;
+ }*/
+ else if ((address >= 0xF14000) && (address <= 0xF14003))
+ {
+ JoystickWriteByte(address, byte);
+ EepromWriteByte(address, byte);
+ return;
+ }
+ else if ((address >= 0xF14004) && (address <= 0xF1A0FF))
+ {
+ EepromWriteByte(address, byte);
+ return;
+ }
+//Need to protect write attempts to Wavetable ROM (F1D000-FFF)
+ else if (address >= 0xF1D000 && address <= 0xF1DFFF)
+ return;
+
+ jerryRAM[address & 0xFFFF] = byte;
+ }
+ // hole ($F20000 - $FFFFFF) 1M - 128K
+ else
+ ; // Do nothing
+}
+
+void WriteWord(uint32 adddress, uint16 word)
+{
+}
+
+void WriteDWord(uint32 adddress, uint32 dword)
+{
+}
+
+uint8 ReadByte(uint32 adddress)
+{
+}
+
+uint16 ReadWord(uint32 adddress)
+{
+}
+
+uint32 ReadDWord(uint32 adddress)
+{
+}
+#endif