+ sprintf(string, "GPU PC: %06X FLAGS: %04X SR: %04X<br><br>", GPUReadLong(0xF02110, DEBUG), GPUReadLong(0xF02100, DEBUG), GPUReadLong(0xF02114, DEBUG));
+ s += QString(string);
+/*
+GPU Flags:
+0 - Zero flag
+1 - Carry flag
+2 - Negative flag
+3 - IMASK (writing 0 clears, 1 has no effect)
+4-8 - IRQ enable 0 - 4
+9-13 - IRQ latch clear 0 - 4
+14 - REGPAGE
+15 - DMAEN
+
+GPU Control:
+0 - GPU Go
+1 - CPUINT
+2 - GPUINT0
+3 - Single Step
+4 - Single step go
+5 - Unused
+6-10 - IRQ Latch 0 - 4
+11 - Bus Hog
+12-15 - Version
+*/
+
+ sprintf(string, "Bank 0:<br>"
+ "R00: %08X R01: %08X R02: %08X R03: %08X<br>"
+ "R04: %08X R05: %08X R06: %08X R07: %08X<br>"
+ "R08: %08X R09: %08X R10: %08X R11: %08X<br>"
+ "R12: %08X R13: %08X R14: %08X R15: %08X<br>"
+ "R16: %08X R17: %08X R18: %08X R19: %08X<br>"
+ "R20: %08X R21: %08X R22: %08X R23: %08X<br>"
+ "R24: %08X R25: %08X R26: %08X R27: %08X<br>"
+ "R28: %08X R29: %08X R30: %08X R31: %08X<br><br>",
+ gpu_reg_bank_0[0], gpu_reg_bank_0[1], gpu_reg_bank_0[2], gpu_reg_bank_0[3],
+ gpu_reg_bank_0[4], gpu_reg_bank_0[5], gpu_reg_bank_0[6], gpu_reg_bank_0[7],
+ gpu_reg_bank_0[8], gpu_reg_bank_0[9], gpu_reg_bank_0[10], gpu_reg_bank_0[11],
+ gpu_reg_bank_0[12], gpu_reg_bank_0[13], gpu_reg_bank_0[14], gpu_reg_bank_0[15],
+ gpu_reg_bank_0[16], gpu_reg_bank_0[17], gpu_reg_bank_0[18], gpu_reg_bank_0[19],
+ gpu_reg_bank_0[20], gpu_reg_bank_0[21], gpu_reg_bank_0[22], gpu_reg_bank_0[23],
+ gpu_reg_bank_0[24], gpu_reg_bank_0[25], gpu_reg_bank_0[26], gpu_reg_bank_0[27],
+ gpu_reg_bank_0[28], gpu_reg_bank_0[29], gpu_reg_bank_0[30], gpu_reg_bank_0[31]);
+ s += QString(string);
+
+ sprintf(string, "Bank 1:<br>"
+ "R00: %08X R01: %08X R02: %08X R03: %08X<br>"
+ "R04: %08X R05: %08X R06: %08X R07: %08X<br>"
+ "R08: %08X R09: %08X R10: %08X R11: %08X<br>"
+ "R12: %08X R13: %08X R14: %08X R15: %08X<br>"
+ "R16: %08X R17: %08X R18: %08X R19: %08X<br>"
+ "R20: %08X R21: %08X R22: %08X R23: %08X<br>"
+ "R24: %08X R25: %08X R26: %08X R27: %08X<br>"
+ "R28: %08X R29: %08X R30: %08X R31: %08X<br><br>",
+ gpu_reg_bank_1[0], gpu_reg_bank_1[1], gpu_reg_bank_1[2], gpu_reg_bank_1[3],
+ gpu_reg_bank_1[4], gpu_reg_bank_1[5], gpu_reg_bank_1[6], gpu_reg_bank_1[7],
+ gpu_reg_bank_1[8], gpu_reg_bank_1[9], gpu_reg_bank_1[10], gpu_reg_bank_1[11],
+ gpu_reg_bank_1[12], gpu_reg_bank_1[13], gpu_reg_bank_1[14], gpu_reg_bank_1[15],
+ gpu_reg_bank_1[16], gpu_reg_bank_1[17], gpu_reg_bank_1[18], gpu_reg_bank_1[19],
+ gpu_reg_bank_1[20], gpu_reg_bank_1[21], gpu_reg_bank_1[22], gpu_reg_bank_1[23],
+ gpu_reg_bank_1[24], gpu_reg_bank_1[25], gpu_reg_bank_1[26], gpu_reg_bank_1[27],
+ gpu_reg_bank_1[28], gpu_reg_bank_1[29], gpu_reg_bank_1[30], gpu_reg_bank_1[31]);