+
+// NB: This is just a wild hairy-assed guess as to what the playback frequency is.
+// It can be timed to anything really, anything that writes to L/RTXD at a regular
+// interval. Most things seem to use either the I2S interrupt or the TIMER 0
+// interrupt, so that's what we check for here. Just know that this approach
+// can be easily fooled!
+// Note also that if both interrupts are enabled, the I2S freq will win. :-P
+
+// Further Note:
+// The impetus for this "fix" was Cybermorph, which sets the SCLK to 7 which is an
+// audio frequency > 48 KHz. However, it stuffs the L/RTXD registers using TIMER0.
+// So, while this works, it's a by-product of the lame way in which audio is currently
+// handled. Hopefully, once we run the DSP in the host audio IRQ, this problem will
+// go away of its own accord. :-P
+// Or does it? It seems the I2S interrupt isn't on with Cybermorph, so something
+// weird is going on here...
+// Maybe it works like this: It acknowledges the 1st interrupt, but never clears it.
+// So subsequent interrupts come into the chip, but they're never serviced but the
+// I2S subsystem keeps going.
+
+ if (data & INT_ENA1) // I2S interrupt
+ {
+ int freq = GetCalculatedFrequency();
+//This happens too often to be useful...
+// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq);
+ DACSetNewFrequency(freq);
+ }
+ else if (data & INT_ENA2) // TIMER 0 interrupt
+ {
+ int freq = JERRYGetPIT1Frequency();
+//This happens too often to be useful...
+// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq);
+ DACSetNewFrequency(freq);
+ }
+