-static uint16 *mirror_table;
-static uint8 *dsp_ram_8;
-
-static uint32 dsp_pc;
-static uint32 dsp_acc;
-static uint32 dsp_remain;
-static uint32 dsp_modulo;
-static uint32 dsp_flags;
-static uint32 dsp_matrix_control;
-static uint32 dsp_pointer_to_matrix;
-static uint32 dsp_data_organization;
-static uint32 dsp_control;
-static uint32 dsp_div_control;
-static uint8 dsp_flag_z;
-static uint8 dsp_flag_n;
-static uint8 dsp_flag_c;
-static uint8 dsp_alternate_flag_z;
-static uint8 dsp_alternate_flag_n;
-static uint8 dsp_alternate_flag_c;
-static uint32 *dsp_reg;
-static uint32 *dsp_alternate_reg;
-static uint32 *dsp_reg_bank_0;
-static uint32 *dsp_reg_bank_1;
-
-static uint32 dsp_opcode_first_parameter;
-static uint32 dsp_opcode_second_parameter;
-
-#define dsp_running (dsp_control&0x01)
-
-#define Rm dsp_reg[dsp_opcode_first_parameter]
-#define Rn dsp_reg[dsp_opcode_second_parameter]
-#define alternate_Rm dsp_alternate_reg[dsp_opcode_first_parameter]
-#define alternate_Rn dsp_alternate_reg[dsp_opcode_second_parameter]
-#define imm_1 dsp_opcode_first_parameter
-#define imm_2 dsp_opcode_second_parameter
-
-#define set_flag_z(r) dsp_flag_z=(r==0);
-#define set_flag_n(r) dsp_flag_n=(r&0x80000000);
-
-#define reset_flag_z() dsp_flag_z=0;
-#define reset_flag_n() dsp_flag_n=0;
-#define reset_flag_c() dsp_flag_c=0;
+uint32 dsp_pc;
+static uint64 dsp_acc; // 40 bit register, NOT 32!
+static uint32 dsp_remain;
+static uint32 dsp_modulo;
+static uint32 dsp_flags;
+static uint32 dsp_matrix_control;
+static uint32 dsp_pointer_to_matrix;
+static uint32 dsp_data_organization;
+uint32 dsp_control;
+static uint32 dsp_div_control;
+static uint8 dsp_flag_z, dsp_flag_n, dsp_flag_c;
+static uint32 * dsp_reg, * dsp_alternate_reg;
+static uint32 * dsp_reg_bank_0, * dsp_reg_bank_1;
+
+static uint32 dsp_opcode_first_parameter;
+static uint32 dsp_opcode_second_parameter;
+
+#define DSP_RUNNING (dsp_control & 0x01)
+
+#define RM dsp_reg[dsp_opcode_first_parameter]
+#define RN dsp_reg[dsp_opcode_second_parameter]
+#define ALTERNATE_RM dsp_alternate_reg[dsp_opcode_first_parameter]
+#define ALTERNATE_RN dsp_alternate_reg[dsp_opcode_second_parameter]
+#define IMM_1 dsp_opcode_first_parameter
+#define IMM_2 dsp_opcode_second_parameter
+
+#define CLR_Z (dsp_flag_z = 0)
+#define CLR_ZN (dsp_flag_z = dsp_flag_n = 0)
+#define CLR_ZNC (dsp_flag_z = dsp_flag_n = dsp_flag_c = 0)
+#define SET_Z(r) (dsp_flag_z = ((r) == 0))
+#define SET_N(r) (dsp_flag_n = (((UINT32)(r) >> 31) & 0x01))
+#define SET_C_ADD(a,b) (dsp_flag_c = ((UINT32)(b) > (UINT32)(~(a))))
+#define SET_C_SUB(a,b) (dsp_flag_c = ((UINT32)(b) > (UINT32)(a)))
+#define SET_ZN(r) SET_N(r); SET_Z(r)
+#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
+#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b)