// Seems alignment in loads & stores was off...
#define DSP_CORRECT_ALIGNMENT
//#define DSP_CORRECT_ALIGNMENT_STORE
// Seems alignment in loads & stores was off...
#define DSP_CORRECT_ALIGNMENT
//#define DSP_CORRECT_ALIGNMENT_STORE
// IRQs on J_INT ($F10020), you don't have to run an I2S interrupt on the DSP. Also,
// It seems that it's only stable for values of SCLK <= 9.
// IRQs on J_INT ($F10020), you don't have to run an I2S interrupt on the DSP. Also,
// It seems that it's only stable for values of SCLK <= 9.
// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq);
DACSetNewFrequency(freq);
}
// WriteLog("DSP: Setting audio freqency to %u Hz...\n", freq);
DACSetNewFrequency(freq);
}
// Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents
for(uint32 i=0; i<8192; i+=4)
{
// Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents
for(uint32 i=0; i<8192; i+=4)
{