+ <li>
+ <dfn>Power Management, CPU DMA latency: </dfn> modern processors try
+ to aggressively transition to power saving when idle, even for a few
+ microseconds, hurting realtime performance by needing to wake to a
+ more active state. This setting counters this behaviour by setting
+ a maximum response time while low latency operation is desired.
+ <kbd class="menu">0</em> is the fastest response time.
+ </li>