const char reg_err[] = "missing register R0...R31";
-// Jaguar Jump Condition Names
+// Jaguar jump condition names
const char condname[MAXINTERNCC][5] = {
"NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
"N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
"PL", "MI", "F"
};
-// Jaguar Jump Condition Numbers
+// Jaguar jump condition numbers
const char condnumber[] = {
1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
{ MR_NORMI, RI_TWO, 56 },
{ MR_NOP, RI_NONE, 57 },
{ MR_SAT24, RI_ONE, 62 },
- { MR_UNPACK, RI_ONE, 63 + GPUONLY },
- { MR_PACK, RI_ONE, 63 + GPUONLY },
+ { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
+ { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
{ MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
{ MR_MOVE, RI_MOVE, 0 },
{ MR_LOAD, RI_LOAD, 0 },
// Check for absolute address setting
if (!orgwarning && !orgactive)
{
-// warn("GPU/DSP code outside of absolute section");
warn("RISC code generated with no origin defined");
orgwarning = 1;
}
int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
D_word(value);
+//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
}
break;
// Single operand instructions (Rd)
- // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK
+ // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
+ // UNPACK
case RI_ONE:
reg2 = GetRegister(FU_REGTWO);
at_eol();
break;
// Two operand instructions (Rs,Rd)
- // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT,
- // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
+ // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
+ // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
case RI_TWO:
if (parm == 37)
altbankok = 1; // MOVEFA
case RI_NUM_31:
// Numeric operand (n,Rd) where n = 1..32
- // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ
+ // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
+ // RORQ
case RI_NUM_32:
switch (type)
{
{
if (eattr & TDB)
//{
-//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
+//printf("RISCASM: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
//}
}