2 // mmu.cpp: Memory management
5 // (C) 2013 Underground Software
7 // JLH = James Hammons <jlhamm@acm.org>
10 // --- ---------- ------------------------------------------------------------
11 // JLH 09/27/2013 Created this file
16 #include "applevideo.h"
25 // Address Map enumeration
26 enum { AM_RAM, AM_ROM, AM_BANKED, AM_READ, AM_WRITE, AM_READ_WRITE, AM_END_OF_LIST };
28 // Macros for function pointers
29 // The typedef would be something like:
30 //typedef ReadFunc (uint8_t (*)(uint16_t));
31 //typedef WriteFunc (void (*)(uint16_t, uint8_t));
32 #define READFUNC(x) uint8_t (* x)(uint16_t)
33 #define WRITEFUNC(x) void (* x)(uint16_t, uint8_t)
36 uint8_t ** addrPtrRead[0x10000];
37 uint8_t ** addrPtrWrite[0x10000];
38 uint16_t addrOffset[0x10000];
40 READFUNC(funcMapRead[0x10000]);
41 WRITEFUNC(funcMapWrite[0x10000]);
43 // Language card state (ROM read, no write)
44 uint8_t lcState = 0x02;
58 // Dunno if I like this approach or not...
60 // AM_RANGE(0x0000, 0xBFFF) AM_RAM AM_BASE(ram) AM_SHARE(1)
61 // AM_RANGE(0xC000, 0xC001) AM_READWRITE(readFunc, writeFunc)
64 // Would need a pointer for 80STORE as well...
66 uint8_t * pageZeroMemory = &ram[0x0000]; // $0000 - $01FF
67 uint8_t * mainMemoryR = &ram[0x0200]; // $0200 - $BFFF (read)
68 uint8_t * mainMemoryW = &ram[0x0200]; // $0200 - $BFFF (write)
70 uint8_t * mainMemoryTextR = &ram[0x0400]; // $0400 - $07FF (read)
71 uint8_t * mainMemoryTextW = &ram[0x0400]; // $0400 - $07FF (write)
72 uint8_t * mainMemoryHGRR = &ram[0x2000]; // $2000 - $3FFF (read)
73 uint8_t * mainMemoryHGRW = &ram[0x2000]; // $2000 - $3FFF (write)
75 uint8_t * slotMemory = &rom[0xC100]; // $C100 - $CFFF
76 uint8_t * slot3Memory = &rom[0xC300]; // $C300 - $C3FF
77 uint8_t * slot6Memory = &diskROM[0]; // $C600 - $C6FF
78 uint8_t * lcBankMemoryR = &ram[0xD000]; // $D000 - $DFFF (read)
79 uint8_t * lcBankMemoryW = &ram[0xD000]; // $D000 - $DFFF (write)
80 uint8_t * upperMemoryR = &ram[0xE000]; // $E000 - $FFFF (read)
81 uint8_t * upperMemoryW = &ram[0xE000]; // $E000 - $FFFF (write)
84 // Function prototypes
85 uint8_t ReadNOP(uint16_t);
86 void WriteNOP(uint16_t, uint8_t);
87 uint8_t ReadMemory(uint16_t);
88 void WriteMemory(uint16_t, uint8_t);
89 uint8_t ReadKeyboard(uint16_t);
90 void Switch80STORE(uint16_t, uint8_t);
91 void SwitchRAMRD(uint16_t, uint8_t);
92 void SwitchRAMWRT(uint16_t, uint8_t);
93 void SwitchSLOTCXROM(uint16_t, uint8_t);
94 void SwitchALTZP(uint16_t, uint8_t);
95 void SwitchSLOTC3ROM(uint16_t, uint8_t);
96 void Switch80COL(uint16_t, uint8_t);
97 void SwitchALTCHARSET(uint16_t, uint8_t);
98 uint8_t ReadKeyStrobe(uint16_t);
99 uint8_t ReadBANK2(uint16_t);
100 uint8_t ReadLCRAM(uint16_t);
101 uint8_t ReadRAMRD(uint16_t);
102 uint8_t ReadRAMWRT(uint16_t);
103 uint8_t ReadSLOTCXROM(uint16_t);
104 uint8_t ReadALTZP(uint16_t);
105 uint8_t ReadSLOTC3ROM(uint16_t);
106 uint8_t Read80STORE(uint16_t);
107 uint8_t ReadVBL(uint16_t);
108 uint8_t ReadTEXT(uint16_t);
109 uint8_t ReadMIXED(uint16_t);
110 uint8_t ReadPAGE2(uint16_t);
111 uint8_t ReadHIRES(uint16_t);
112 uint8_t ReadALTCHARSET(uint16_t);
113 uint8_t Read80COL(uint16_t);
114 void WriteKeyStrobe(uint16_t, uint8_t);
115 uint8_t ReadSpeaker(uint16_t);
116 void WriteSpeaker(uint16_t, uint8_t);
117 uint8_t SwitchLCR(uint16_t);
118 void SwitchLCW(uint16_t, uint8_t);
120 uint8_t SwitchTEXTR(uint16_t);
121 void SwitchTEXTW(uint16_t, uint8_t);
122 uint8_t SwitchMIXEDR(uint16_t);
123 void SwitchMIXEDW(uint16_t, uint8_t);
124 uint8_t SwitchPAGE2R(uint16_t);
125 void SwitchPAGE2W(uint16_t, uint8_t);
126 uint8_t SwitchHIRESR(uint16_t);
127 void SwitchHIRESW(uint16_t, uint8_t);
128 uint8_t SwitchDHIRESR(uint16_t);
129 void SwitchDHIRESW(uint16_t, uint8_t);
130 void SwitchIOUDIS(uint16_t, uint8_t);
131 uint8_t Slot6R(uint16_t);
132 void Slot6W(uint16_t, uint8_t);
133 void HandleSlot6(uint16_t, uint8_t);
134 uint8_t ReadButton0(uint16_t);
135 uint8_t ReadButton1(uint16_t);
136 uint8_t ReadPaddle0(uint16_t);
137 uint8_t ReadIOUDIS(uint16_t);
138 uint8_t ReadDHIRES(uint16_t);
139 //uint8_t SwitchR(uint16_t);
140 //void SwitchW(uint16_t, uint8_t);
143 // The main Apple //e memory map
144 AddressMap memoryMap[] = {
145 { 0x0000, 0x01FF, AM_RAM, &pageZeroMemory, 0, 0, 0 },
146 { 0x0200, 0xBFFF, AM_BANKED, &mainMemoryR, &mainMemoryW, 0, 0 },
148 // These will overlay over the previously written memory accessors
149 { 0x0400, 0x07FF, AM_BANKED, &mainMemoryTextR, &mainMemoryTextW, 0, 0 },
150 { 0x2000, 0x3FFF, AM_BANKED, &mainMemoryHGRR, &mainMemoryHGRW, 0, 0 },
152 { 0xC000, 0xC001, AM_READ_WRITE, 0, 0, ReadKeyboard, Switch80STORE },
153 { 0xC002, 0xC003, AM_READ_WRITE, 0, 0, ReadKeyboard, SwitchRAMRD },
154 { 0xC004, 0xC005, AM_READ_WRITE, 0, 0, ReadKeyboard, SwitchRAMWRT },
155 { 0xC006, 0xC007, AM_READ_WRITE, 0, 0, ReadKeyboard, SwitchSLOTCXROM },
156 { 0xC008, 0xC009, AM_READ_WRITE, 0, 0, ReadKeyboard, SwitchALTZP },
157 { 0xC00A, 0xC00B, AM_READ_WRITE, 0, 0, ReadKeyboard, SwitchSLOTC3ROM },
158 { 0xC00C, 0xC00D, AM_READ_WRITE, 0, 0, ReadKeyboard, Switch80COL },
159 { 0xC00E, 0xC00F, AM_READ_WRITE, 0, 0, ReadKeyboard, SwitchALTCHARSET },
160 { 0xC010, 0xC010, AM_READ_WRITE, 0, 0, ReadKeyStrobe, WriteKeyStrobe },
161 { 0xC011, 0xC011, AM_READ_WRITE, 0, 0, ReadBANK2, WriteKeyStrobe },
162 { 0xC012, 0xC012, AM_READ_WRITE, 0, 0, ReadLCRAM, WriteKeyStrobe },
163 { 0xC013, 0xC013, AM_READ_WRITE, 0, 0, ReadRAMRD, WriteKeyStrobe },
164 { 0xC014, 0xC014, AM_READ_WRITE, 0, 0, ReadRAMWRT, WriteKeyStrobe },
165 { 0xC015, 0xC015, AM_READ_WRITE, 0, 0, ReadSLOTCXROM, WriteKeyStrobe },
166 { 0xC016, 0xC016, AM_READ_WRITE, 0, 0, ReadALTZP, WriteKeyStrobe },
167 { 0xC017, 0xC017, AM_READ_WRITE, 0, 0, ReadSLOTC3ROM, WriteKeyStrobe },
168 { 0xC018, 0xC018, AM_READ_WRITE, 0, 0, Read80STORE, WriteKeyStrobe },
169 { 0xC019, 0xC019, AM_READ_WRITE, 0, 0, ReadVBL, WriteKeyStrobe },
170 { 0xC01A, 0xC01A, AM_READ_WRITE, 0, 0, ReadTEXT, WriteKeyStrobe },
171 { 0xC01B, 0xC01B, AM_READ_WRITE, 0, 0, ReadMIXED, WriteKeyStrobe },
172 { 0xC01C, 0xC01C, AM_READ_WRITE, 0, 0, ReadPAGE2, WriteKeyStrobe },
173 { 0xC01D, 0xC01D, AM_READ_WRITE, 0, 0, ReadHIRES, WriteKeyStrobe },
174 { 0xC01E, 0xC01E, AM_READ_WRITE, 0, 0, ReadALTCHARSET, WriteKeyStrobe },
175 { 0xC01F, 0xC01F, AM_READ_WRITE, 0, 0, Read80COL, WriteKeyStrobe },
176 { 0xC030, 0xC03F, AM_READ_WRITE, 0, 0, ReadSpeaker, WriteSpeaker },
177 { 0xC050, 0xC051, AM_READ_WRITE, 0, 0, SwitchTEXTR, SwitchTEXTW },
178 { 0xC052, 0xC053, AM_READ_WRITE, 0, 0, SwitchMIXEDR, SwitchMIXEDW },
179 { 0xC054, 0xC055, AM_READ_WRITE, 0, 0, SwitchPAGE2R, SwitchPAGE2W },
180 { 0xC056, 0xC057, AM_READ_WRITE, 0, 0, SwitchHIRESR, SwitchHIRESW },
181 { 0xC05E, 0xC05F, AM_READ_WRITE, 0, 0, SwitchDHIRESR, SwitchDHIRESW },
182 { 0xC061, 0xC061, AM_READ, 0, 0, ReadButton0, 0 },
183 { 0xC062, 0xC062, AM_READ, 0, 0, ReadButton1, 0 },
184 { 0xC064, 0xC067, AM_READ, 0, 0, ReadPaddle0, 0 },
185 // { 0xC07E, 0xC07F, AM_READ_WRITE, 0, 0, SwitchIOUDISR, SwitchIOUDISW },
186 { 0xC07E, 0xC07E, AM_READ_WRITE, 0, 0, ReadIOUDIS, SwitchIOUDIS },
187 { 0xC07F, 0xC07F, AM_READ_WRITE, 0, 0, ReadDHIRES, SwitchIOUDIS },
188 { 0xC080, 0xC08F, AM_READ_WRITE, 0, 0, SwitchLCR, SwitchLCW },
189 { 0xC0E0, 0xC0EF, AM_READ_WRITE, 0, 0, Slot6R, Slot6W },
190 { 0xC100, 0xCFFF, AM_ROM, &slotMemory, 0, 0, 0 },
192 // This will overlay the slotMemory accessors for slot 6 ROM
193 { 0xC300, 0xC3FF, AM_ROM, &slot3Memory, 0, 0, 0 },
194 { 0xC600, 0xC6FF, AM_ROM, &slot6Memory, 0, 0, 0 },
196 { 0xD000, 0xDFFF, AM_BANKED, &lcBankMemoryR, &lcBankMemoryW, 0, 0 },
197 { 0xE000, 0xFFFF, AM_BANKED, &upperMemoryR, &upperMemoryW, 0, 0 },
198 { 0x0000, 0x0000, AM_END_OF_LIST, 0, 0, 0, 0 }
202 void SetupAddressMap(void)
204 for(uint32_t i=0; i<0x10000; i++)
206 funcMapRead[i] = ReadNOP;
207 funcMapWrite[i] = WriteNOP;
215 while (memoryMap[i].type != AM_END_OF_LIST)
217 switch (memoryMap[i].type)
220 for(uint32_t j=memoryMap[i].start; j<=memoryMap[i].end; j++)
222 funcMapRead[j] = ReadMemory;
223 funcMapWrite[j] = WriteMemory;
224 addrPtrRead[j] = memoryMap[i].memory;
225 addrPtrWrite[j] = memoryMap[i].memory;
226 addrOffset[j] = j - memoryMap[i].start;
227 //WriteLog("SetupAddressMap: j=$%04X, addrOffset[j]=$%04X\n", j, addrOffset[j]);
232 for(uint32_t j=memoryMap[i].start; j<=memoryMap[i].end; j++)
234 funcMapRead[j] = ReadMemory;
235 addrPtrRead[j] = memoryMap[i].memory;
236 addrOffset[j] = j - memoryMap[i].start;
241 for(uint32_t j=memoryMap[i].start; j<=memoryMap[i].end; j++)
243 funcMapRead[j] = ReadMemory;
244 funcMapWrite[j] = WriteMemory;
245 addrPtrRead[j] = memoryMap[i].memory;
246 addrPtrWrite[j] = memoryMap[i].altMemory;
247 addrOffset[j] = j - memoryMap[i].start;
252 for(uint32_t j=memoryMap[i].start; j<=memoryMap[i].end; j++)
253 funcMapRead[j] = memoryMap[i].read;
257 for(uint32_t j=memoryMap[i].start; j<=memoryMap[i].end; j++)
258 funcMapWrite[j] = memoryMap[i].write;
262 for(uint32_t j=memoryMap[i].start; j<=memoryMap[i].end; j++)
264 funcMapRead[j] = memoryMap[i].read;
265 funcMapWrite[j] = memoryMap[i].write;
274 // This should correctly set up the LC pointers, but it doesn't
275 // for some reason... :-/
276 // It's because we were storing pointers directly, instead of pointers
277 // to the pointer... It's complicated. :-)
283 // Built-in functions
285 uint8_t ReadNOP(uint16_t)
291 void WriteNOP(uint16_t, uint8_t)
296 uint8_t ReadMemory(uint16_t address)
298 //WriteLog("ReadMemory: addr=$%04X, addrPtrRead[addr]=$%X, addrOffset[addr]=$%X, val=$%02X\n", address, addrPtrRead[address], addrOffset[address], addrPtrRead[address][addrOffset[address]]);
299 // We are guaranteed a valid address here by the setup function, so there's
300 // no need to do any checking here.
301 return (*addrPtrRead[address])[addrOffset[address]];
305 void WriteMemory(uint16_t address, uint8_t byte)
307 // We can write protect memory this way, but it adds a branch to the mix. :-/
308 // (this can be avoided by setting up another bank of memory which we
310 if ((*addrPtrWrite[address]) == 0)
313 (*addrPtrWrite[address])[addrOffset[address]] = byte;
318 // The main memory access functions used by V65C02
320 uint8_t AppleReadMem(uint16_t address)
322 return (*(funcMapRead[address]))(address);
326 void AppleWriteMem(uint16_t address, uint8_t byte)
328 (*(funcMapWrite[address]))(address, byte);
333 // Actual emulated I/O functions follow
335 uint8_t ReadKeyboard(uint16_t /*addr*/)
337 return lastKeyPressed | ((uint8_t)keyDown << 7);
341 void Switch80STORE(uint16_t address, uint8_t)
343 store80Mode = (bool)(address & 0x01);
344 WriteLog("Setting 80STORE to %s...\n", (store80Mode ? "ON" : "off"));
348 mainMemoryTextR = (displayPage2 ? &ram2[0x0400] : &ram[0x0400]);
349 mainMemoryTextW = (displayPage2 ? &ram2[0x0400] : &ram[0x0400]);
350 // mainMemoryHGRR = (displayPage2 ? &ram2[0x2000] : &ram[0x2000]);
351 // mainMemoryHGRW = (displayPage2 ? &ram2[0x2000] : &ram[0x2000]);
355 mainMemoryTextR = (ramwrt ? &ram2[0x0400] : &ram[0x0400]);
356 mainMemoryTextW = (ramwrt ? &ram2[0x0400] : &ram[0x0400]);
357 // mainMemoryHGRR = (ramwrt ? &ram2[0x2000] : &ram[0x2000]);
358 // mainMemoryHGRW = (ramwrt ? &ram2[0x2000] : &ram[0x2000]);
363 void SwitchRAMRD(uint16_t address, uint8_t)
365 ramrd = (bool)(address & 0x01);
366 mainMemoryR = (ramrd ? &ram2[0x0200] : &ram[0x0200]);
367 mainMemoryHGRR = (ramrd ? &ram2[0x2000] : &ram[0x2000]);
372 mainMemoryTextR = (ramrd ? &ram2[0x0400] : &ram[0x0400]);
376 void SwitchRAMWRT(uint16_t address, uint8_t)
378 ramwrt = (bool)(address & 0x01);
379 mainMemoryW = (ramwrt ? &ram2[0x0200] : &ram[0x0200]);
380 mainMemoryHGRW = (ramwrt ? &ram2[0x2000] : &ram[0x2000]);
385 mainMemoryTextW = (ramwrt ? &ram2[0x0400] : &ram[0x0400]);
389 void SwitchSLOTCXROM(uint16_t address, uint8_t)
391 //WriteLog("Setting SLOTCXROM to %s...\n", ((address & 0x01) ^ 0x01 ? "ON" : "off"));
392 // This is the only soft switch that breaks the usual convention.
393 slotCXROM = !((bool)(address & 0x01));
394 // slot3Memory = (slotCXROM ? &rom[0] : &rom[0xC300]);
395 slot6Memory = (slotCXROM ? &diskROM[0] : &rom[0xC600]);
399 void SwitchALTZP(uint16_t address, uint8_t)
401 altzp = (bool)(address & 0x01);
402 pageZeroMemory = (altzp ? &ram2[0x0000] : &ram[0x0000]);
406 //extern bool dumpDis;
408 void SwitchSLOTC3ROM(uint16_t address, uint8_t)
411 //WriteLog("Setting SLOTC3ROM to %s...\n", (address & 0x01 ? "ON" : "off"));
412 slotC3ROM = (bool)(address & 0x01);
413 // slotC3ROM = false;
414 // Seems the h/w forces this with an 80 column card in slot 3...
415 slot3Memory = (slotC3ROM ? &rom[0] : &rom[0xC300]);
416 // slot3Memory = &rom[0xC300];
420 void Switch80COL(uint16_t address, uint8_t)
422 col80Mode = (bool)(address & 0x01);
426 void SwitchALTCHARSET(uint16_t address, uint8_t)
428 alternateCharset = (bool)(address & 0x01);
432 uint8_t ReadKeyStrobe(uint16_t)
434 uint8_t byte = lastKeyPressed | ((uint8_t)keyDown << 7);
440 uint8_t ReadBANK2(uint16_t)
442 return (lcState < 0x04 ? 0x80 : 0x00);
446 uint8_t ReadLCRAM(uint16_t)
448 // If bits 0 & 1 are set, but not at the same time, then it's ROM
449 uint8_t lcROM = (lcState & 0x1) ^ ((lcState & 0x02) >> 1);
450 return (lcROM ? 0x00 : 0x80);
454 uint8_t ReadRAMRD(uint16_t)
456 return (uint8_t)ramrd << 7;
460 uint8_t ReadRAMWRT(uint16_t)
462 return (uint8_t)ramwrt << 7;
466 uint8_t ReadSLOTCXROM(uint16_t)
468 return (uint8_t)slotCXROM << 7;
472 uint8_t ReadALTZP(uint16_t)
474 return (uint8_t)altzp << 7;
478 uint8_t ReadSLOTC3ROM(uint16_t)
481 return (uint8_t)slotC3ROM << 7;
485 uint8_t Read80STORE(uint16_t)
487 return (uint8_t)store80Mode << 7;
491 uint8_t ReadVBL(uint16_t)
493 return (uint8_t)vbl << 7;
497 uint8_t ReadTEXT(uint16_t)
499 return (uint8_t)textMode << 7;
503 uint8_t ReadMIXED(uint16_t)
505 return (uint8_t)mixedMode << 7;
509 uint8_t ReadPAGE2(uint16_t)
511 return (uint8_t)displayPage2 << 7;
515 uint8_t ReadHIRES(uint16_t)
517 return (uint8_t)hiRes << 7;
521 uint8_t ReadALTCHARSET(uint16_t)
523 return (uint8_t)alternateCharset << 7;
527 uint8_t Read80COL(uint16_t)
529 return (uint8_t)col80Mode << 7;
533 void WriteKeyStrobe(uint16_t, uint8_t)
539 uint8_t ReadSpeaker(uint16_t)
546 void WriteSpeaker(uint16_t, uint8_t)
552 uint8_t SwitchLCR(uint16_t address)
554 lcState = address & 0x0B;
560 void SwitchLCW(uint16_t address, uint8_t)
562 lcState = address & 0x0B;
573 WriteLog("SwitchLC: Read RAM bank 2, no write\n");
575 // [R ] Read RAM bank 2; no write
576 lcBankMemoryR = (altzp ? &ram2[0xD000] : &ram[0xD000]);
578 upperMemoryR = (altzp ? &ram2[0xE000] : &ram[0xE000]);
583 WriteLog("SwitchLC: Read ROM, write bank 2\n");
585 // [RR] Read ROM; write RAM bank 2
586 lcBankMemoryR = &rom[0xD000];
587 lcBankMemoryW = (altzp ? &ram2[0xD000] : &ram[0xD000]);
588 upperMemoryR = &rom[0xE000];
589 upperMemoryW = (altzp ? &ram2[0xE000] : &ram[0xE000]);
593 WriteLog("SwitchLC: Read ROM, no write\n");
595 // [R ] Read ROM; no write
596 lcBankMemoryR = &rom[0xD000];
598 upperMemoryR = &rom[0xE000];
603 WriteLog("SwitchLC: Read/write bank 2\n");
605 // [RR] Read RAM bank 2; write RAM bank 2
606 lcBankMemoryR = (altzp ? &ram2[0xD000] : &ram[0xD000]);
607 lcBankMemoryW = (altzp ? &ram2[0xD000] : &ram[0xD000]);
608 upperMemoryR = (altzp ? &ram2[0xE000] : &ram[0xE000]);
609 upperMemoryW = (altzp ? &ram2[0xE000] : &ram[0xE000]);
612 // [R ] Read RAM bank 1; no write
613 lcBankMemoryR = (altzp ? &ram2[0xC000] : &ram[0xC000]);
615 upperMemoryR = (altzp ? &ram2[0xE000] : &ram[0xE000]);
619 // [RR] Read ROM; write RAM bank 1
620 lcBankMemoryR = &rom[0xD000];
621 lcBankMemoryW = (altzp ? &ram2[0xC000] : &ram[0xC000]);
622 upperMemoryR = &rom[0xE000];
623 upperMemoryW = (altzp ? &ram2[0xE000] : &ram[0xE000]);
626 // [R ] Read ROM; no write
627 lcBankMemoryR = &rom[0xD000];
629 upperMemoryR = &rom[0xE000];
633 // [RR] Read RAM bank 1; write RAM bank 1
634 lcBankMemoryR = (altzp ? &ram2[0xC000] : &ram[0xC000]);
635 lcBankMemoryW = (altzp ? &ram2[0xC000] : &ram[0xC000]);
636 upperMemoryR = (altzp ? &ram2[0xE000] : &ram[0xE000]);
637 upperMemoryW = (altzp ? &ram2[0xE000] : &ram[0xE000]);
643 uint8_t SwitchTEXTR(uint16_t address)
645 WriteLog("Setting TEXT to %s...\n", (address & 0x01 ? "ON" : "off"));
646 textMode = (bool)(address & 0x01);
651 void SwitchTEXTW(uint16_t address, uint8_t)
653 WriteLog("Setting TEXT to %s...\n", (address & 0x01 ? "ON" : "off"));
654 textMode = (bool)(address & 0x01);
658 uint8_t SwitchMIXEDR(uint16_t address)
660 WriteLog("Setting MIXED to %s...\n", (address & 0x01 ? "ON" : "off"));
661 mixedMode = (bool)(address & 0x01);
666 void SwitchMIXEDW(uint16_t address, uint8_t)
668 WriteLog("Setting MIXED to %s...\n", (address & 0x01 ? "ON" : "off"));
669 mixedMode = (bool)(address & 0x01);
673 uint8_t SwitchPAGE2R(uint16_t address)
675 WriteLog("Setting PAGE2 to %s...\n", (address & 0x01 ? "ON" : "off"));
676 displayPage2 = (bool)(address & 0x01);
680 mainMemoryTextR = (displayPage2 ? &ram2[0x0400] : &ram[0x0400]);
681 mainMemoryTextW = (displayPage2 ? &ram2[0x0400] : &ram[0x0400]);
682 // mainMemoryHGRR = (displayPage2 ? &ram2[0x2000] : &ram[0x2000]);
683 // mainMemoryHGRW = (displayPage2 ? &ram2[0x2000] : &ram[0x2000]);
690 void SwitchPAGE2W(uint16_t address, uint8_t)
692 WriteLog("Setting PAGE2 to %s...\n", (address & 0x01 ? "ON" : "off"));
693 displayPage2 = (bool)(address & 0x01);
697 mainMemoryTextR = (displayPage2 ? &ram2[0x0400] : &ram[0x0400]);
698 mainMemoryTextW = (displayPage2 ? &ram2[0x0400] : &ram[0x0400]);
699 // mainMemoryHGRR = (displayPage2 ? &ram2[0x2000] : &ram[0x2000]);
700 // mainMemoryHGRW = (displayPage2 ? &ram2[0x2000] : &ram[0x2000]);
705 uint8_t SwitchHIRESR(uint16_t address)
707 WriteLog("Setting HIRES to %s...\n", (address & 0x01 ? "ON" : "off"));
708 hiRes = (bool)(address & 0x01);
713 void SwitchHIRESW(uint16_t address, uint8_t)
715 WriteLog("Setting HIRES to %s...\n", (address & 0x01 ? "ON" : "off"));
716 hiRes = (bool)(address & 0x01);
720 uint8_t SwitchDHIRESR(uint16_t address)
722 WriteLog("Setting DHIRES to %s (ioudis = %s)...\n", ((address & 0x01) ^ 0x01 ? "ON" : "off"), (ioudis ? "ON" : "off"));
723 // Hmm, this breaks convention too, like SLOTCXROM
725 dhires = !((bool)(address & 0x01));
731 void SwitchDHIRESW(uint16_t address, uint8_t)
733 WriteLog("Setting DHIRES to %s (ioudis = %s)...\n", ((address & 0x01) ^ 0x01 ? "ON" : "off"), (ioudis ? "ON" : "off"));
735 dhires = !((bool)(address & 0x01));
739 void SwitchIOUDIS(uint16_t address, uint8_t)
741 ioudis = !((bool)(address & 0x01));
745 uint8_t Slot6R(uint16_t address)
747 //WriteLog("Slot6R: address = %X\n", address & 0x0F);
748 // HandleSlot6(address, 0);
750 uint8_t state = address & 0x0F;
762 floppyDrive.ControlStepper(state);
766 floppyDrive.ControlMotor(state & 0x01);
770 floppyDrive.DriveEnable(state & 0x01);
773 return floppyDrive.ReadWrite();
776 return floppyDrive.GetLatchValue();
779 floppyDrive.SetReadMode();
782 floppyDrive.SetWriteMode();
790 void Slot6W(uint16_t address, uint8_t byte)
792 //WriteLog("Slot6W: address = %X, byte= %X\n", address & 0x0F, byte);
793 // HandleSlot6(address, byte);
794 uint8_t state = address & 0x0F;
806 floppyDrive.ControlStepper(state);
810 floppyDrive.ControlMotor(state & 0x01);
814 floppyDrive.DriveEnable(state & 0x01);
817 floppyDrive.ReadWrite();
820 floppyDrive.SetLatchValue(byte);
823 floppyDrive.SetReadMode();
826 floppyDrive.SetWriteMode();
832 void HandleSlot6(uint16_t address, uint8_t byte)
837 uint8_t ReadButton0(uint16_t)
839 return (uint8_t)openAppleDown << 7;
843 uint8_t ReadButton1(uint16_t)
845 return (uint8_t)closedAppleDown << 7;
849 // The way the paddles work is that a strobe is written (or read) to $C070,
850 // then software counts down the time that it takes for the paddle outputs
851 // to have bit 7 return to 0. If there are no paddles connected, bit 7
853 // NB: This is really paddles 0-3, not just 0 :-P
854 uint8_t ReadPaddle0(uint16_t)
860 uint8_t ReadIOUDIS(uint16_t)
862 return (uint8_t)ioudis << 7;
866 uint8_t ReadDHIRES(uint16_t)
868 return (uint8_t)dhires << 7;