Shamusworld >> Repos - virtualjaguar/blob - src/mmu.cpp

   1 //
   2 // mmu.cpp
   3 //
   4 // Jaguar Memory Manager Unit
   5 //
   6 // by James L. Hammons
   7 //
   8 // JLH = James L. Hammons
   9 //
  10 // WHO  WHEN        WHAT
  11 // ---  ----------  -----------------------------------------------------------
  12 // JLH  11/25/2009  Created this file. :-)
  13 //
  14
  15 #include "mmu.h"
  16
  17 /*
  18 Addresses to be handled:
  19
  20 SYSTEM SETUP REGISTERS
  21
  22 *MEMCON1        Memory Control Register 1                       F00000          RW
  23 *MEMCON2        Memory Control Register 2                       F00002          RW
  24 HC                      Horizontal Count                                        F00004          RW
  25 VC                      Vertical Count                                          F00006          RW
  26 LPH                     Light Pen Horizontal                            F00008          RO
  27 LPV                     Light Pen Vertical                                      F0000A          RO
  28 OB[0-3]         Object Data Field                                       F00010-16       RO
  29 OLP                     Object List Pointer                                     F00020-23       WO
  30 OBF                     Object Flag                                                     F00026          WO
  31 VMODE           Video Mode                                                      F00028          WO
  32 BORD1           Border Colour (Red & Green)                     F0002A          WO
  33 BORD2           Border Colour (Blue)                            F0002C          WO
  34 *HP                     Horizontal Period                                       F0002E          WO
  35 *HBB            Horizontal Blank Begin                          F00030          WO
  36 *HBE            Horizontal Blank End                            F00032          WO
  37 *HS                     Horizontal Sync                                         F00034          WO
  38 *HVS            Horizontal Vertical Sync                        F00036          WO
  39 HDB1            Horizontal Display Begin 1                      F00038          WO
  40 HDB2            Horizontal Display Begin 2                      F0003A          WO
  41 HDE                     Horizontal Display End                          F0003C          WO
  42 *VP                     Vertical Period                                         F0003E          WO
  43 *VBB            Vertical Blank Begin                            F00040          WO
  44 *VBE            Vertical Blank End                                      F00042          WO
  45 *VS                     Vertical Sync                                           F00044          WO
  46 VDB                     Vertical Display Begin                          F00046          WO
  47 VDE                     Vertical Display End                            F00048          WO
  48 *VEB            Vertical Equalization Begin                     F0004A          WO
  49 *VEE            Vertical Equalization End                       F0004C          WO
  50 VI                      Vertical Interrupt                                      F0004E          WO
  51 PIT[0-1]        Programmable Interrupt Timer            F00050-52       WO
  52 *HEQ            Horizontal Equalization End                     F00054          WO
  53 BG                      Background Colour                                       F00058          WO
  54 INT1            CPU Interrupt Control Register          F000E0          RW
  55 INT2            CPU Interrupt Resume Register           F000E2          WO
  56 CLUT            Colour Look-Up Table                            F00400-7FE      RW
  57 LBUF            Line Buffer                                                     F00800-1D9E     RW
  58
  59 GPU REGISTERS
  60
  61 G_FLAGS         GPU Flags Register                                      F02100          RW
  62 G_MTXC          Matrix Control Register                         F02104          WO
  63 G_MTXA          Matrix Address Register                         F02108          WO
  64 G_END           Data Organization Register                      F0210C          WO
  65 G_PC            GPU Program Counter                                     F02110          RW
  66 G_CTRL          GPU Control/Status Register                     F02114          RW
  67 G_HIDATA        High Data Register                                      F02118          RW
  68 G_REMAIN        Divide Unit Remainder                           F0211C          RO
  69 G_DIVCTRL       Divide Unit Control                                     F0211C          WO
  70
  71 BLITTER REGISTERS
  72
  73 A1_BASE         A1 Base Register                                        F02200          WO
  74 A1_FLAGS        Flags Register                                          F02204          WO
  75 A1_CLIP         A1 Clipping Size                                        F02208          WO
  76 A1_PIXEL        A1 Pixel Pointer                                        F0220C          WO
  77                                                                                                 F02204          RO
  78 A1_STEP         A1 Step Value                                           F02210          WO
  79 A1_FSTEP        A1 Step Fraction Value                          F02214          WO
  80 A1_FPIXEL       A1 Pixel Pointer Fraction                       F02218          RW
  81 A1_INC          A1 Increment                                            F0221C          WO
  82 A1_FINC         A1 Increment Fraction                           F02220          WO
  83 A2_BASE         A2 Base Register                                        F02224          WO
  84 A2_FLAGS        A2 Flags Register                                       F02228          WO
  85 A2_MASK         A2 Window Mask                                          F0222C          WO
  86 A2_PIXEL        A2 Pixel Pointer                                        F02230          WO
  87                                                                                                 F0222C          RO
  88 A2_STEP         A2 Step Value                                           F02234          WO
  89 B_CMD           Command/Status Register                         F02238          RW
  90 B_COUNT         Counters Register                                       F0223C          WO
  91 B_SRCD          Source Data Register                            F02240          WO
  92 B_DSTD          Destination Data Register                       F02248          WO
  93 B_DSTZ          Destination Z Register                          F02250          WO
  94 B_SRCZ1         Source Z Register 1                                     F02258          WO
  95 B_SRCZ2         Source Z Register 2                                     F02260          WO
  96 B_PATD          Pattern Data Register                           F02268          WO
  97 B_IINC          Intensity Increment                                     F02270          WO
  98 B_ZINC          Z Increment                                                     F02274          WO
  99 B_STOP          Collision Control                                       F02278          WO
 100 B_I3            Intensity 3                                                     F0227C          WO
 101 B_I2            Intensity 2                                                     F02280          WO
 102 B_I1            Intensity 1                                                     F02284          WO
 103 B_I0            Intensity 0                                                     F02288          WO
 104 B_Z3            Z 3                                                                     F0228C          WO
 105 B_Z2            Z 2                                                                     F02290          WO
 106 B_Z1            Z 1                                                                     F02294          WO
 107 B_Z0            Z 0                                                                     F02298          WO
 108
 109 JERRY REGISTERS
 110
 111 *CLK1           Processor Clock Divider                         F10010          WO
 112 *CLK2           Video Clock Divider                                     F10012          WO
 113 *CLK3           Chroma Clock Divider                            F10014          WO
 114 JPIT1           Timer 1 Pre-scaler                                      F10000          WO
 115 JPIT3           Timer 2 Pre-scaler                                      F10004          WO
 116 JPIT2           Timer 1 Divider                                         F10002          WO
 117 JPIT4           Timer 2 Divider                                         F10006          WO
 118 J_INT           Interrup Control Register                       F10020          RW
 119 SCLK            Serial Clock Frequency                          F1A150          WO
 120 SMODE           Serial Mode                                                     F1A154          WO
 121 LTXD            Left Transmit Data                                      F1A148          WO
 122 RTXD            Right Transmit Data                                     F1A14C          WO
 123 LRXD            Left Receive Data                                       F1A148          RO
 124 RRXD            Right Receive Data                                      F1A14C          RO
 125 L_I2S           Left I2S Serial Interface                       F1A148          RW
 126 R_I2S           Right I2S Serial Interface                      F1A14C          RW
 127 SSTAT           Serial Status                                           F1A150          RO
 128 ASICLK          Asynchronous Serial Interface Clock     F10034          RW
 129 ASICTRL         Asynchronous Serial Control                     F10032          WO
 130 ASISTAT         Asynchronous Serial Status                      F10032          RO
 131 ASIDATA         Asynchronous Serial Data                        F10030          RW
 132
 133 JOYSTICK REGISTERS
 134
 135 JOYSTICK        Joystick Register                                       F14000          RW
 136 JOYBUTS         Button Register                                         F14002          RW
 137
 138 DSP REGISTERS
 139
 140 D_FLAGS         DSP Flags Register                                      F1A100          RW
 141 D_MTXC          DSP Matrix Control Register                     F1A104          WO
 142 D_MTXA          DSP Matrix Address Register                     F1A108          WO
 143 D_END           DSP Data Organization Register          F1A10C          WO
 144 D_PC            DSP Program Counter                                     F1A110          RW
 145 D_CTRL          DSP Control/Status Register                     F1A114          RW
 146 D_MOD           Modulo Instruction Mask                         F1A118          WO
 147 D_REMAIN        Divide Unit Remainder                           F1A11C          RO
 148 D_DIVCTRL       Divide Unit Control                                     F1A11C          WO
 149 D_MACHI         MAC High Result Bits                            F1A120          RO
 150 */
 151
 152 /*
 153 The approach here is to have a list of addresses and who handles them. Could be
 154 a one-to-one memory location up to a range for each function. Will look
 155 something like this:
 156
 157         { 0xF14000, 0xF14001, MM_IO, JoystickReadHanlder, JoystickWriteHandler },
 158
 159 Would be nice to have a way of either calling a handler function or reading/writing
 160 directly to/from a variable or array...
 161 */
 162
 163 enum MemType { MM_NOP = 0, MM_RAM, MM_ROM, MM_IO };
 164
 165 #if 0
 166 // Jaguar Memory map/handlers
 167 uint32 memoryMap[] = {
 168         { 0x000000, 0x3FFFFF, MM_RAM, jaguarMainRAM },
 169         { 0x800000, 0xDFFEFF, MM_ROM, jaguarMainROM },
 170 // Note that this is really memory mapped I/O region...
 171 //      { 0xDFFF00, 0xDFFFFF, MM_RAM, cdRAM },
 172         { 0xDFFF00, 0xDFFF03, MM_IO,  cdBUTCH }, // base of Butch == interrupt control register, R/W
 173         { 0xDFFF04, 0xDFFF07, MM_IO,  cdDSCNTRL }, // DSA control register, R/W
 174         { 0xDFFF0A, 0xDFFF0B, MM_IO,  cdDS_DATA }, // DSA TX/RX data, R/W
 175         { 0xDFFF10, 0xDFFF13, MM_IO,  cdI2CNTRL }, // i2s bus control register, R/W
 176         { 0xDFFF14, 0xDFFF17, MM_IO,  cdSBCNTRL }, // CD subcode control register, R/W
 177         { 0xDFFF18, 0xDFFF1B, MM_IO,  cdSUBDATA }, // Subcode data register A
 178         { 0xDFFF1C, 0xDFFF1F, MM_IO,  cdSUBDATB }, // Subcode data register B
 179         { 0xDFFF20, 0xDFFF23, MM_IO,  cdSB_TIME }, // Subcode time and compare enable (D24)
 180         { 0xDFFF24, 0xDFFF27, MM_IO,  cdFIFO_DATA }, // i2s FIFO data
 181         { 0xDFFF28, 0xDFFF2B, MM_IO,  cdI2SDAT2 }, // i2s FIFO data (old)
 182         { 0xDFFF2C, 0xDFFF2F, MM_IO,  cdUNKNOWN }, // Seems to be some sort of I2S interface
 183
 184         { 0xE00000, 0xE3FFFF, MM_ROM, jaguarBootROM },
 185
 186 //      { 0xF00000, 0xF0FFFF, MM_IO,  TOM_REGS_RW },
 187         { 0xF00050, 0xF00051, MM_IO,  tomTimerPrescaler },
 188         { 0xF00052, 0xF00053, MM_IO,  tomTimerDivider },
 189         { 0xF00400, 0xF005FF, MM_RAM, tomRAM }, // CLUT A&B: How to link these? Write to one writes to the other...
 190         { 0xF00600, 0xF007FF, MM_RAM, tomRAM }, // Actually, this is a good approach--just make the reads the same as well
 191         //What about LBUF writes???
 192         { 0xF02100, 0xF0211F, MM_IO,  GPUWriteByte }, // GPU CONTROL
 193         { 0xF02200, 0xF0229F, MM_IO,  BlitterWriteByte }, // BLITTER
 194         { 0xF03000, 0xF03FFF, MM_RAM, GPUWriteByte }, // GPU RAM
 195
 196         { 0xF10000, 0xF1FFFF, MM_IO,  JERRY_REGS_RW },
 197
 198 /*
 199         EEPROM:
 200         { 0xF14001, 0xF14001, MM_IO_RO, eepromFOO }
 201         { 0xF14801, 0xF14801, MM_IO_WO, eepromBAR }
 202         { 0xF15001, 0xF15001, MM_IO_RW, eepromBAZ }
 203
 204         JOYSTICK:
 205         { 0xF14000, 0xF14003, MM_IO,  joystickFoo }
 206         0 = pad0/1 button values (4 bits each), RO(?)
 207         1 = pad0/1 index value (4 bits each), WO
 208         2 = unused, RO
 209         3 = NTSC/PAL, certain button states, RO
 210
 211 JOYSTICK    $F14000               Read/Write
 212             15.....8  7......0
 213 Read        fedcba98  7654321q    f-1    Signals J15 to J1
 214                                   q      Cartridge EEPROM  output data
 215 Write       exxxxxxm  76543210    e      1 = enable  J7-J0 outputs
 216                                          0 = disable J7-J0 outputs
 217                                   x      don't care
 218                                   m      Audio mute
 219                                          0 = Audio muted (reset state)
 220                                          1 = Audio enabled
 221                                   7-4    J7-J4 outputs (port 2)
 222                                   3-0    J3-J0 outputs (port 1)
 223 JOYBUTS     $F14002               Read Only
 224             15.....8  7......0
 225 Read        xxxxxxxx  rrdv3210    x      don't care
 226                                   r      Reserved
 227                                   d      Reserved
 228                                   v      1 = NTSC Video hardware
 229                                          0 = PAL  Video hardware
 230                                   3-2    Button inputs B3 & B2 (port 2)
 231                                   1-0    Button inputs B1 & B0 (port 1)
 232
 233 J4 J5 J6 J7  Port 2    B2     B3    J12  J13   J14  J15
 234 J3 J2 J1 J0  Port 1    B0     B1    J8   J9    J10  J11
 235  0  0  0  0
 236  0  0  0  1
 237  0  0  1  0
 238  0  0  1  1
 239  0  1  0  0
 240  0  1  0  1
 241  0  1  1  0
 242  0  1  1  1  Row 3     C3   Option  #     9     6     3
 243  1  0  0  0
 244  1  0  0  1
 245  1  0  1  0
 246  1  0  1  1  Row 2     C2      C    0     8     5     2
 247  1  1  0  0
 248  1  1  0  1  Row 1     C1      B    *     7     4     1
 249  1  1  1  0  Row 0   Pause     A    Up  Down  Left  Right
 250  1  1  1  1
 251
 252 0 bit read in any position means that button is pressed.
 253 C3 = C2 = 1 means std. Jag. cntrlr. or nothing attached.
 254 */
 255 };
 256 #endif
 257
 258 void MMUWrite8(uint32 address, uint8 data, uint32 who/*= UNKNOWN*/)
 259 {
 260 }
 261
 262 void MMUWrite16(uint32 address, uint16 data, uint32 who/*= UNKNOWN*/)
 263 {
 264 }
 265
 266 void MMUWrite32(uint32 address, uint32 data, uint32 who/*= UNKNOWN*/)
 267 {
 268 }
 269
 270 void MMUWrite64(uint32 address, uint64 data, uint32 who/*= UNKNOWN*/)
 271 {
 272 }
 273
 274 uint8 MMURead8(uint32 address, uint32 who/*= UNKNOWN*/)
 275 {
 276         return 0;
 277 }
 278
 279 uint16 MMURead16(uint32 address, uint32 who/*= UNKNOWN*/)
 280 {
 281         return 0;
 282 }
 283
 284 uint32 MMURead32(uint32 address, uint32 who/*= UNKNOWN*/)
 285 {
 286         return 0;
 287 }
 288
 289 uint64 MMURead64(uint32 address, uint32 who/*= UNKNOWN*/)
 290 {
 291         return 0;
 292 }
 293