Shamusworld >> Repos - virtualjaguar/blob - src/jerry.cpp

   1 //
   2 // JERRY Core
   3 //
   4 // Originally by David Raingeard
   5 // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS)
   6 // Cleanups/rewrites/fixes by James L. Hammons
   7 //
   8 //      ------------------------------------------------------------
   9 //      JERRY REGISTERS (Mapped by Aaron Giles)
  10 //      ------------------------------------------------------------
  11 //      F10000-F13FFF   R/W   xxxxxxxx xxxxxxxx   Jerry
  12 //      F10000            W   xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
  13 //      F10002            W   xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
  14 //      F10004            W   xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
  15 //      F10008            W   xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
  16 //      F10010            W   ------xx xxxxxxxx   CLK1 - processor clock divider
  17 //      F10012            W   ------xx xxxxxxxx   CLK2 - video clock divider
  18 //      F10014            W   -------- --xxxxxx   CLK3 - chroma clock divider
  19 //      F10020          R/W   ---xxxxx ---xxxxx   JINTCTRL - interrupt control register
  20 //                        W   ---x---- --------      (J_SYNCLR - clear synchronous serial intf ints)
  21 //                        W   ----x--- --------      (J_ASYNCLR - clear asynchronous serial intf ints)
  22 //                        W   -----x-- --------      (J_TIM2CLR - clear timer 2 [tempo] interrupts)
  23 //                        W   ------x- --------      (J_TIM1CLR - clear timer 1 [sample] interrupts)
  24 //                        W   -------x --------      (J_EXTCLR - clear external interrupts)
  25 //                      R/W   -------- ---x----      (J_SYNENA - enable synchronous serial intf ints)
  26 //                      R/W   -------- ----x---      (J_ASYNENA - enable asynchronous serial intf ints)
  27 //                      R/W   -------- -----x--      (J_TIM2ENA - enable timer 2 [tempo] interrupts)
  28 //                      R/W   -------- ------x-      (J_TIM1ENA - enable timer 1 [sample] interrupts)
  29 //                      R/W   -------- -------x      (J_EXTENA - enable external interrupts)
  30 //      F10030          R/W   -------- xxxxxxxx   ASIDATA - asynchronous serial data
  31 //      F10032            W   -x------ -xxxxxxx   ASICTRL - asynchronous serial control
  32 //                        W   -x------ --------      (TXBRK - transmit break)
  33 //                        W   -------- -x------      (CLRERR - clear error)
  34 //                        W   -------- --x-----      (RINTEN - enable receiver interrupts)
  35 //                        W   -------- ---x----      (TINTEN - enable transmitter interrupts)
  36 //                        W   -------- ----x---      (RXIPOL - receiver input polarity)
  37 //                        W   -------- -----x--      (TXOPOL - transmitter output polarity)
  38 //                        W   -------- ------x-      (PAREN - parity enable)
  39 //                        W   -------- -------x      (ODD - odd parity select)
  40 //      F10032          R     xxx-xxxx x-xxxxxx   ASISTAT - asynchronous serial status
  41 //                      R     x------- --------      (ERROR - OR of PE,FE,OE)
  42 //                      R     -x------ --------      (TXBRK - transmit break)
  43 //                      R     --x----- --------      (SERIN - serial input)
  44 //                      R     ----x--- --------      (OE - overrun error)
  45 //                      R     -----x-- --------      (FE - framing error)
  46 //                      R     ------x- --------      (PE - parity error)
  47 //                      R     -------x --------      (TBE - transmit buffer empty)
  48 //                      R     -------- x-------      (RBF - receive buffer full)
  49 //                      R     -------- ---x----      (TINTEN - enable transmitter interrupts)
  50 //                      R     -------- ----x---      (RXIPOL - receiver input polarity)
  51 //                      R     -------- -----x--      (TXOPOL - transmitter output polarity)
  52 //                      R     -------- ------x-      (PAREN - parity enable)
  53 //                      R     -------- -------x      (ODD - odd parity)
  54 //      F10034          R/W   xxxxxxxx xxxxxxxx   ASICLK - asynchronous serial interface clock
  55 //      F10036          R     xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
  56 //      F10038          R     xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
  57 //      F1003A          R     xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
  58 //      F1003C          R     xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
  59 //      ------------------------------------------------------------
  60 //      F14000-F17FFF   R/W   xxxxxxxx xxxxxxxx   Joysticks and GPIO0-5
  61 //      F14000          R     xxxxxxxx xxxxxxxx   JOYSTICK - read joystick state
  62 //      F14000            W   x------- xxxxxxxx   JOYSTICK - latch joystick output
  63 //                        W   x------- --------      (enable joystick outputs)
  64 //                        W   -------- xxxxxxxx      (joystick output data)
  65 //      F14002          R     xxxxxxxx xxxxxxxx   JOYBUTS - button register
  66 //      F14800-F14FFF   R/W   xxxxxxxx xxxxxxxx   GPI00 - reserved (CD-ROM?)
  67 //      F15000-F15FFF   R/W   xxxxxxxx xxxxxxxx   GPI01 - reserved
  68 //      F16000-F16FFF   R/W   xxxxxxxx xxxxxxxx   GPI02 - reserved
  69 //      F17000-F177FF   R/W   xxxxxxxx xxxxxxxx   GPI03 - reserved
  70 //      F17800-F17BFF   R/W   xxxxxxxx xxxxxxxx   GPI04 - reserved
  71 //      F17C00-F17FFF   R/W   xxxxxxxx xxxxxxxx   GPI05 - reserved
  72 //      ------------------------------------------------------------
  73 //      F18000-F1FFFF   R/W   xxxxxxxx xxxxxxxx   Jerry DSP
  74 //      F1A100          R/W   xxxxxxxx xxxxxxxx   D_FLAGS - DSP flags register
  75 //                      R/W   x------- --------      (DMAEN - DMA enable)
  76 //                      R/W   -x------ --------      (REGPAGE - register page)
  77 //                        W   --x----- --------      (D_EXT0CLR - clear external interrupt 0)
  78 //                        W   ---x---- --------      (D_TIM2CLR - clear timer 2 interrupt)
  79 //                        W   ----x--- --------      (D_TIM1CLR - clear timer 1 interrupt)
  80 //                        W   -----x-- --------      (D_I2SCLR - clear I2S interrupt)
  81 //                        W   ------x- --------      (D_CPUCLR - clear CPU interrupt)
  82 //                      R/W   -------x --------      (D_EXT0ENA - enable external interrupt 0)
  83 //                      R/W   -------- x-------      (D_TIM2ENA - enable timer 2 interrupt)
  84 //                      R/W   -------- -x------      (D_TIM1ENA - enable timer 1 interrupt)
  85 //                      R/W   -------- --x-----      (D_I2SENA - enable I2S interrupt)
  86 //                      R/W   -------- ---x----      (D_CPUENA - enable CPU interrupt)
  87 //                      R/W   -------- ----x---      (IMASK - interrupt mask)
  88 //                      R/W   -------- -----x--      (NEGA_FLAG - ALU negative)
  89 //                      R/W   -------- ------x-      (CARRY_FLAG - ALU carry)
  90 //                      R/W   -------- -------x      (ZERO_FLAG - ALU zero)
  91 //      F1A102          R/W   -------- ------xx   D_FLAGS - upper DSP flags
  92 //                      R/W   -------- ------x-      (D_EXT1ENA - enable external interrupt 1)
  93 //                      R/W   -------- -------x      (D_EXT1CLR - clear external interrupt 1)
  94 //      F1A104            W   -------- ----xxxx   D_MTXC - matrix control register
  95 //                        W   -------- ----x---      (MATCOL - column/row major)
  96 //                        W   -------- -----xxx      (MATRIX3-15 - matrix width)
  97 //      F1A108            W   ----xxxx xxxxxx--   D_MTXA - matrix address register
  98 //      F1A10C            W   -------- -----x-x   D_END - data organization register
  99 //                        W   -------- -----x--      (BIG_INST - big endian instruction fetch)
 100 //                        W   -------- -------x      (BIG_IO - big endian I/O)
 101 //      F1A110          R/W   xxxxxxxx xxxxxxxx   D_PC - DSP program counter
 102 //      F1A114          R/W   xxxxxxxx xx-xxxxx   D_CTRL - DSP control/status register
 103 //                      R     xxxx---- --------      (VERSION - DSP version code)
 104 //                      R/W   ----x--- --------      (BUS_HOG - hog the bus!)
 105 //                      R/W   -----x-- --------      (D_EXT0LAT - external interrupt 0 latch)
 106 //                      R/W   ------x- --------      (D_TIM2LAT - timer 2 interrupt latch)
 107 //                      R/W   -------x --------      (D_TIM1LAT - timer 1 interrupt latch)
 108 //                      R/W   -------- x-------      (D_I2SLAT - I2S interrupt latch)
 109 //                      R/W   -------- -x------      (D_CPULAT - CPU interrupt latch)
 110 //                      R/W   -------- ---x----      (SINGLE_GO - single step one instruction)
 111 //                      R/W   -------- ----x---      (SINGLE_STEP - single step mode)
 112 //                      R/W   -------- -----x--      (FORCEINT0 - cause interrupt 0 on GPU)
 113 //                      R/W   -------- ------x-      (CPUINT - send GPU interrupt to CPU)
 114 //                      R/W   -------- -------x      (DSPGO - enable DSP execution)
 115 //      F1A116          R/W   -------- -------x   D_CTRL - upper DSP control/status register
 116 //                      R/W   -------- -------x      (D_EXT1LAT - external interrupt 1 latch)
 117 //      F1A118-F1A11B     W   xxxxxxxx xxxxxxxx   D_MOD - modulo instruction mask
 118 //      F1A11C-F1A11F   R     xxxxxxxx xxxxxxxx   D_REMAIN - divide unit remainder
 119 //      F1A11C            W   -------- -------x   D_DIVCTRL - divide unit control
 120 //                        W   -------- -------x      (DIV_OFFSET - 1=16.16 divide, 0=32-bit divide)
 121 //      F1A120-F1A123   R     xxxxxxxx xxxxxxxx   D_MACHI - multiply & accumulate high bits
 122 //      F1A148            W   xxxxxxxx xxxxxxxx   R_DAC - right transmit data
 123 //      F1A14C            W   xxxxxxxx xxxxxxxx   L_DAC - left transmit data
 124 //      F1A150            W   -------- xxxxxxxx   SCLK - serial clock frequency
 125 //      F1A150          R     -------- ------xx   SSTAT
 126 //                      R     -------- ------x-      (left - no description)
 127 //                      R     -------- -------x      (WS - word strobe status)
 128 //      F1A154            W   -------- --xxxx-x   SMODE - serial mode
 129 //                        W   -------- --x-----      (EVERYWORD - interrupt on MSB of every word)
 130 //                        W   -------- ---x----      (FALLING - interrupt on falling edge)
 131 //                        W   -------- ----x---      (RISING - interrupt of rising edge)
 132 //                        W   -------- -----x--      (WSEN - enable word strobes)
 133 //                        W   -------- -------x      (INTERNAL - enables serial clock)
 134 //      ------------------------------------------------------------
 135 //      F1B000-F1CFFF   R/W   xxxxxxxx xxxxxxxx   Local DSP RAM
 136 //      ------------------------------------------------------------
 137 //      F1D000          R     xxxxxxxx xxxxxxxx   ROM_TRI - triangle wave
 138 //      F1D200          R     xxxxxxxx xxxxxxxx   ROM_SINE - full sine wave
 139 //      F1D400          R     xxxxxxxx xxxxxxxx   ROM_AMSINE - amplitude modulated sine wave
 140 //      F1D600          R     xxxxxxxx xxxxxxxx   ROM_12W - sine wave and second order harmonic
 141 //      F1D800          R     xxxxxxxx xxxxxxxx   ROM_CHIRP16 - chirp
 142 //      F1DA00          R     xxxxxxxx xxxxxxxx   ROM_NTRI - traingle wave with noise
 143 //      F1DC00          R     xxxxxxxx xxxxxxxx   ROM_DELTA - spike
 144 //      F1DE00          R     xxxxxxxx xxxxxxxx   ROM_NOISE - white noise
 145 //      ------------------------------------------------------------
 146
 147 //#include <math.h>
 148 #include "jaguar.h"
 149 #include "wavetable.h"
 150 #include "jerry.h"
 151 #include "clock.h"
 152
 153 //Note that 44100 Hz requires samples every 22.675737 usec.
 154 #define NEW_TIMER_SYSTEM
 155 //#define JERRY_DEBUG
 156
 157 /*static*/ uint8 * jerry_ram_8;
 158
 159 //#define JERRY_CONFIG  0x4002                                          // ??? What's this ???
 160
 161 uint8 analog_x, analog_y;
 162
 163 static uint32 JERRYPIT1Prescaler;
 164 static uint32 JERRYPIT1Divider;
 165 static uint32 JERRYPIT2Prescaler;
 166 static uint32 JERRYPIT2Divider;
 167 static int32 jerry_timer_1_counter;
 168 static int32 jerry_timer_2_counter;
 169
 170 static uint32 jerry_i2s_interrupt_divide = 8;
 171 static int32 jerry_i2s_interrupt_timer = -1;
 172 uint32 jerryI2SCycles;
 173 uint32 jerryIntPending;
 174
 175 // Private function prototypes
 176
 177 void JERRYResetPIT1(void);
 178 void JERRYResetPIT2(void);
 179 void JERRYResetI2S(void);
 180
 181 void JERRYPIT1Callback(void);
 182 void JERRYPIT2Callback(void);
 183 void JERRYI2SCallback(void);
 184
 185 //This approach is probably wrong, since the timer is continuously counting down, though
 186 //it might only be a problem if the # of interrupts generated is greater than 1--the M68K's
 187 //timeslice should be running during that phase... (The DSP needs to be aware of this!)
 188
 189 //This is only used by the old system, so once the new timer system is working this
 190 //should be safe to nuke.
 191 void jerry_i2s_exec(uint32 cycles)
 192 {
 193 #ifndef NEW_TIMER_SYSTEM
 194         extern uint16 serialMode;                                               // From DAC.CPP
 195         if (serialMode & 0x01)                                                  // INTERNAL flag (JERRY is master)
 196         {
 197
 198         // Why is it called this? Instead of SCLK? Shouldn't this be read from DAC.CPP???
 199 //Yes, it should. !!! FIX !!!
 200                 jerry_i2s_interrupt_divide &= 0xFF;
 201
 202                 if (jerry_i2s_interrupt_timer == -1)
 203                 {
 204                 // We don't have to divide the RISC clock rate by this--the reason is a bit
 205                 // convoluted. Will put explanation here later...
 206 // What's needed here is to find the ratio of the frequency to the number of clock cycles
 207 // in one second. For example, if the sample rate is 44100, we divide the clock rate by
 208 // this: 26590906 / 44100 = 602 cycles.
 209 // Which means, every 602 cycles that go by we have to generate an interrupt.
 210                         jerryI2SCycles = 32 * (2 * (jerry_i2s_interrupt_divide + 1));
 211                 }
 212
 213                 jerry_i2s_interrupt_timer -= cycles;
 214                 if (jerry_i2s_interrupt_timer <= 0)
 215                 {
 216 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!!
 217                         DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
 218                         jerry_i2s_interrupt_timer += jerryI2SCycles;
 219 #ifdef JERRY_DEBUG
 220                         if (jerry_i2s_interrupt_timer < 0)
 221                                 WriteLog("JERRY: Missed generating an interrupt (missed %u)!\n", (-jerry_i2s_interrupt_timer / jerryI2SCycles) + 1);
 222 #endif
 223                 }
 224         }
 225         else                                                                                    // JERRY is slave to external word clock
 226         {
 227                 // This is just a temporary kludge to see if the CD bus mastering works
 228                 // I.e., this is totally faked...!
 229 // The whole interrupt system is pretty much borked and is need of an overhaul.
 230 // What we need is a way of handling these interrupts when they happen instead of
 231 // scanline boundaries the way it is now.
 232                 jerry_i2s_interrupt_timer -= cycles;
 233                 if (jerry_i2s_interrupt_timer <= 0)
 234                 {
 235 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!! [DONE]
 236                         if (ButchIsReadyToSend())//Not sure this is right spot to check...
 237                         {
 238 //      return GetWordFromButchSSI(offset, who);
 239                                 SetSSIWordsXmittedFromButch();
 240                                 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
 241                         }
 242                         jerry_i2s_interrupt_timer += 602;
 243                 }
 244         }
 245 #else
 246         RemoveCallback(JERRYI2SCallback);
 247         JERRYI2SCallback();
 248 #endif
 249 }
 250
 251 //NOTE: This is only used by the old execution core. Safe to nuke once it's stable.
 252 void JERRYExecPIT(uint32 cycles)
 253 {
 254 //This is wrong too: Counters are *always* spinning! !!! FIX !!! [DONE]
 255 //      if (jerry_timer_1_counter)
 256                 jerry_timer_1_counter -= cycles;
 257
 258         if (jerry_timer_1_counter <= 0)
 259         {
 260 //Also, it can generate a CPU interrupt as well... !!! FIX !!! or does it? Maybe it goes Timer->GPU->CPU?
 261                 DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 262 //              JERRYResetPIT1();
 263                 jerry_timer_1_counter += (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 264         }
 265
 266 //This is wrong too: Counters are *always* spinning! !!! FIX !!! [DONE]
 267 //      if (jerry_timer_2_counter)
 268                 jerry_timer_2_counter -= cycles;
 269
 270         if (jerry_timer_2_counter <= 0)
 271         {
 272 //Also, it can generate a CPU interrupt as well... !!! FIX !!! or does it? Maybe it goes Timer->GPU->CPU?
 273                 DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 274 //              JERRYResetPIT2();
 275                 jerry_timer_2_counter += (JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1);
 276         }
 277 }
 278
 279 void JERRYResetI2S(void)
 280 {
 281         //WriteLog("i2s: reseting\n");
 282 //This is really SCLK... !!! FIX !!!
 283         jerry_i2s_interrupt_divide = 8;
 284         jerry_i2s_interrupt_timer = -1;
 285 }
 286
 287 void JERRYResetPIT1(void)
 288 {
 289 #ifndef NEW_TIMER_SYSTEM
 290 /*      if (!JERRYPIT1Prescaler || !JERRYPIT1Divider)
 291                 jerry_timer_1_counter = 0;
 292         else//*/
 293 //Small problem with this approach: Overflow if both are = $FFFF. !!! FIX !!!
 294                 jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 295
 296 //      if (jerry_timer_1_counter)
 297 //              WriteLog("jerry: reseting timer 1 to 0x%.8x (%i)\n",jerry_timer_1_counter,jerry_timer_1_counter);
 298
 299 #else
 300         RemoveCallback(JERRYPIT1Callback);
 301
 302         if (JERRYPIT1Prescaler | JERRYPIT1Divider)
 303         {
 304                 double usecs = (float)(JERRYPIT1Prescaler + 1) * (float)(JERRYPIT1Divider + 1) * RISC_CYCLE_IN_USEC;
 305                 SetCallbackTime(JERRYPIT1Callback, usecs);
 306         }
 307 #endif
 308 }
 309
 310 void JERRYResetPIT2(void)
 311 {
 312 #ifndef NEW_TIMER_SYSTEM
 313 /*      if (!JERRYPIT2Prescaler || !JERRYPIT2Divider)
 314         {
 315                 jerry_timer_2_counter = 0;
 316                 return;
 317         }
 318         else//*/
 319                 jerry_timer_2_counter = (JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1);
 320
 321 //      if (jerry_timer_2_counter)
 322 //              WriteLog("jerry: reseting timer 2 to 0x%.8x (%i)\n",jerry_timer_2_counter,jerry_timer_2_counter);
 323
 324 #else
 325         RemoveCallback(JERRYPIT2Callback);
 326
 327         if (JERRYPIT1Prescaler | JERRYPIT1Divider)
 328         {
 329                 double usecs = (float)(JERRYPIT2Prescaler + 1) * (float)(JERRYPIT2Divider + 1) * RISC_CYCLE_IN_USEC;
 330                 SetCallbackTime(JERRYPIT2Callback, usecs);
 331         }
 332 #endif
 333 }
 334
 335 void JERRYPIT1Callback(void)
 336 {
 337         DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 338         JERRYResetPIT1();
 339 }
 340
 341 void JERRYPIT2Callback(void)
 342 {
 343         DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 344         JERRYResetPIT2();
 345 }
 346
 347 void JERRYI2SCallback(void)
 348 {
 349         // Why is it called this? Instead of SCLK? Shouldn't this be read from DAC.CPP???
 350 //Yes, it should. !!! FIX !!!
 351         jerry_i2s_interrupt_divide &= 0xFF;
 352         // We don't have to divide the RISC clock rate by this--the reason is a bit
 353         // convoluted. Will put explanation here later...
 354 // What's needed here is to find the ratio of the frequency to the number of clock cycles
 355 // in one second. For example, if the sample rate is 44100, we divide the clock rate by
 356 // this: 26590906 / 44100 = 602 cycles.
 357 // Which means, every 602 cycles that go by we have to generate an interrupt.
 358         jerryI2SCycles = 32 * (2 * (jerry_i2s_interrupt_divide + 1));
 359
 360 //This should be in this file with an extern reference in the header file so that
 361 //DAC.CPP can see it... !!! FIX !!!
 362         extern uint16 serialMode;                                               // From DAC.CPP
 363
 364         if (serialMode & 0x01)                                                  // INTERNAL flag (JERRY is master)
 365         {
 366                 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);         // This does the 'IRQ enabled' checking...
 367                 double usecs = (float)jerryI2SCycles * RISC_CYCLE_IN_USEC;
 368                 SetCallbackTime(JERRYI2SCallback, usecs);
 369         }
 370         else                                                                                    // JERRY is slave to external word clock
 371         {
 372 //Note that 44100 Hz requires samples every 22.675737 usec.
 373 //When JERRY is slave to the word clock, we need to do interrupts either at 44.1K
 374 //sample rate or at a 88.2K sample rate (11.332... usec).
 375 /*              // This is just a temporary kludge to see if the CD bus mastering works
 376                 // I.e., this is totally faked...!
 377 // The whole interrupt system is pretty much borked and is need of an overhaul.
 378 // What we need is a way of handling these interrupts when they happen instead of
 379 // scanline boundaries the way it is now.
 380                 jerry_i2s_interrupt_timer -= cycles;
 381                 if (jerry_i2s_interrupt_timer <= 0)
 382                 {
 383 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!! [DONE]
 384                         if (ButchIsReadyToSend())//Not sure this is right spot to check...
 385                         {
 386 //      return GetWordFromButchSSI(offset, who);
 387                                 SetSSIWordsXmittedFromButch();
 388                                 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
 389                         }
 390                         jerry_i2s_interrupt_timer += 602;
 391                 }*/
 392
 393                 if (ButchIsReadyToSend())//Not sure this is right spot to check...
 394                 {
 395 //      return GetWordFromButchSSI(offset, who);
 396                         SetSSIWordsXmittedFromButch();
 397                         DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
 398                 }
 399
 400                 SetCallbackTime(JERRYI2SCallback, 22.675737);
 401         }
 402 }
 403
 404
 405 void jerry_init(void)
 406 {
 407 //      clock_init();
 408 //      anajoy_init();
 409         joystick_init();
 410         DACInit();
 411 //This should be handled with the cart initialization...
 412 //      eeprom_init();
 413         memory_malloc_secure((void **)&jerry_ram_8, 0x10000, "JERRY RAM/ROM");
 414         memcpy(&jerry_ram_8[0xD000], wave_table, 0x1000);
 415
 416         JERRYPIT1Prescaler = 0xFFFF;
 417         JERRYPIT2Prescaler = 0xFFFF;
 418         JERRYPIT1Divider = 0xFFFF;
 419         JERRYPIT2Divider = 0xFFFF;
 420 }
 421
 422 void jerry_reset(void)
 423 {
 424 //      clock_reset();
 425 //      anajoy_reset();
 426         joystick_reset();
 427         eeprom_reset();
 428         JERRYResetI2S();
 429         DACReset();
 430
 431         memset(jerry_ram_8, 0x00, 0xD000);              // Don't clear out the Wavetable ROM...!
 432         JERRYPIT1Prescaler = 0xFFFF;
 433         JERRYPIT2Prescaler = 0xFFFF;
 434         JERRYPIT1Divider = 0xFFFF;
 435         JERRYPIT2Divider = 0xFFFF;
 436         jerry_timer_1_counter = 0;
 437         jerry_timer_2_counter = 0;
 438 }
 439
 440 void jerry_done(void)
 441 {
 442         WriteLog("JERRY: M68K Interrupt control ($F10020) = %04X\n", GET16(jerry_ram_8, 0x20));
 443         memory_free(jerry_ram_8);
 444 //      clock_done();
 445 //      anajoy_done();
 446         joystick_done();
 447         DACDone();
 448         eeprom_done();
 449 }
 450
 451 bool JERRYIRQEnabled(int irq)
 452 {
 453         // Read the word @ $F10020
 454         return jerry_ram_8[0x21] & (1 << irq);
 455 }
 456
 457 void JERRYSetPendingIRQ(int irq)
 458 {
 459         // This is the shadow of INT (it's a split RO/WO register)
 460         jerryIntPending |= (1 << irq);
 461 }
 462
 463 //
 464 // JERRY byte access (read)
 465 //
 466 uint8 JERRYReadByte(uint32 offset, uint32 who/*=UNKNOWN*/)
 467 {
 468 #ifdef JERRY_DEBUG
 469         WriteLog("JERRY: Reading byte at %06X\n", offset);
 470 #endif
 471         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 472                 return DSPReadByte(offset, who);
 473         else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
 474                 return DSPReadByte(offset, who);
 475         // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
 476         else if (offset >= 0xF1A148 && offset <= 0xF1A153)
 477                 return DACReadByte(offset, who);
 478 //      F10036          R     xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
 479 //      F10038          R     xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
 480 //      F1003A          R     xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
 481 //      F1003C          R     xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
 482 //This is WRONG!
 483 //      else if (offset >= 0xF10000 && offset <= 0xF10007)
 484 //This is still wrong. What needs to be returned here are the values being counted down
 485 //in the jerry_timer_n_counter variables... !!! FIX !!! [DONE]
 486
 487 //This is probably the problem with the new timer code... This is invalid
 488 //under the new system... !!! FIX !!!
 489         else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
 490         {
 491 #ifndef NEW_TIMER_SYSTEM
 492 //              jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 493                 uint32 counter1Hi = (jerry_timer_1_counter / (JERRYPIT1Divider + 1)) - 1;
 494                 uint32 counter1Lo = (jerry_timer_1_counter % (JERRYPIT1Divider + 1)) - 1;
 495                 uint32 counter2Hi = (jerry_timer_2_counter / (JERRYPIT2Divider + 1)) - 1;
 496                 uint32 counter2Lo = (jerry_timer_2_counter % (JERRYPIT2Divider + 1)) - 1;
 497
 498                 switch(offset & 0x0F)
 499                 {
 500                 case 6:
 501 //                      return JERRYPIT1Prescaler >> 8;
 502                         return counter1Hi >> 8;
 503                 case 7:
 504 //                      return JERRYPIT1Prescaler & 0xFF;
 505                         return counter1Hi & 0xFF;
 506                 case 8:
 507 //                      return JERRYPIT1Divider >> 8;
 508                         return counter1Lo >> 8;
 509                 case 9:
 510 //                      return JERRYPIT1Divider & 0xFF;
 511                         return counter1Lo & 0xFF;
 512                 case 10:
 513 //                      return JERRYPIT2Prescaler >> 8;
 514                         return counter2Hi >> 8;
 515                 case 11:
 516 //                      return JERRYPIT2Prescaler & 0xFF;
 517                         return counter2Hi & 0xFF;
 518                 case 12:
 519 //                      return JERRYPIT2Divider >> 8;
 520                         return counter2Lo >> 8;
 521                 case 13:
 522 //                      return JERRYPIT2Divider & 0xFF;
 523                         return counter2Lo & 0xFF;
 524                 }
 525 #else
 526 WriteLog("JERRY: Unhandled timer read (BYTE) at %08X...\n", offset);
 527 #endif
 528         }
 529 //      else if (offset >= 0xF10010 && offset <= 0xF10015)
 530 //              return clock_byte_read(offset);
 531 //      else if (offset >= 0xF17C00 && offset <= 0xF17C01)
 532 //              return anajoy_byte_read(offset);
 533         else if (offset >= 0xF14000 && offset <= 0xF14003)
 534                 return joystick_byte_read(offset) | eeprom_byte_read(offset);
 535         else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
 536                 return eeprom_byte_read(offset);
 537
 538         return jerry_ram_8[offset & 0xFFFF];
 539 }
 540
 541 //
 542 // JERRY word access (read)
 543 //
 544 uint16 JERRYReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
 545 {
 546 #ifdef JERRY_DEBUG
 547         WriteLog("JERRY: Reading word at %06X\n", offset);
 548 #endif
 549
 550         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 551                 return DSPReadWord(offset, who);
 552         else if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE + 0x1FFF)
 553                 return DSPReadWord(offset, who);
 554         // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
 555         else if (offset >= 0xF1A148 && offset <= 0xF1A153)
 556                 return DACReadWord(offset, who);
 557 //      F10036          R     xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
 558 //      F10038          R     xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
 559 //      F1003A          R     xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
 560 //      F1003C          R     xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
 561 //This is WRONG!
 562 //      else if ((offset >= 0xF10000) && (offset <= 0xF10007))
 563 //This is still wrong. What needs to be returned here are the values being counted down
 564 //in the jerry_timer_n_counter variables... !!! FIX !!! [DONE]
 565         else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
 566         {
 567 #ifndef NEW_TIMER_SYSTEM
 568 //              jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 569                 uint32 counter1Hi = (jerry_timer_1_counter / (JERRYPIT1Divider + 1)) - 1;
 570                 uint32 counter1Lo = (jerry_timer_1_counter % (JERRYPIT1Divider + 1)) - 1;
 571                 uint32 counter2Hi = (jerry_timer_2_counter / (JERRYPIT2Divider + 1)) - 1;
 572                 uint32 counter2Lo = (jerry_timer_2_counter % (JERRYPIT2Divider + 1)) - 1;
 573
 574                 switch(offset & 0x0F)
 575                 {
 576                 case 6:
 577 //                      return JERRYPIT1Prescaler;
 578                         return counter1Hi;
 579                 case 8:
 580 //                      return JERRYPIT1Divider;
 581                         return counter1Lo;
 582                 case 10:
 583 //                      return JERRYPIT2Prescaler;
 584                         return counter2Hi;
 585                 case 12:
 586 //                      return JERRYPIT2Divider;
 587                         return counter2Lo;
 588                 }
 589                 // Unaligned word reads???
 590 #else
 591 WriteLog("JERRY: Unhandled timer read (WORD) at %08X...\n", offset);
 592 #endif
 593         }
 594 //      else if ((offset >= 0xF10010) && (offset <= 0xF10015))
 595 //              return clock_word_read(offset);
 596         else if (offset == 0xF10020)
 597                 return jerryIntPending;
 598 //      else if ((offset >= 0xF17C00) && (offset <= 0xF17C01))
 599 //              return anajoy_word_read(offset);
 600         else if (offset == 0xF14000)
 601                 return (joystick_word_read(offset) & 0xFFFE) | eeprom_word_read(offset);
 602         else if ((offset >= 0xF14002) && (offset < 0xF14003))
 603                 return joystick_word_read(offset);
 604         else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
 605                 return eeprom_word_read(offset);
 606
 607 /*if (offset >= 0xF1D000)
 608         WriteLog("JERRY: Reading word at %08X [%04X]...\n", offset, ((uint16)jerry_ram_8[(offset+0)&0xFFFF] << 8) | jerry_ram_8[(offset+1)&0xFFFF]);//*/
 609
 610         offset &= 0xFFFF;                               // Prevent crashing...!
 611         return ((uint16)jerry_ram_8[offset+0] << 8) | jerry_ram_8[offset+1];
 612 }
 613
 614 //
 615 // JERRY byte access (write)
 616 //
 617 void JERRYWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
 618 {
 619 #ifdef JERRY_DEBUG
 620         WriteLog("jerry: writing byte %.2x at 0x%.6x\n",data,offset);
 621 #endif
 622         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 623         {
 624                 DSPWriteByte(offset, data, who);
 625                 return;
 626         }
 627         else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
 628         {
 629                 DSPWriteByte(offset, data, who);
 630                 return;
 631         }
 632         // SCLK ($F1A150--8 bits wide)
 633 //NOTE: This should be taken care of in DAC...
 634         else if ((offset >= 0xF1A152) && (offset <= 0xF1A153))
 635         {
 636 //              WriteLog("JERRY: Writing %02X to SCLK...\n", data);
 637                 if ((offset & 0x03) == 2)
 638                         jerry_i2s_interrupt_divide = (jerry_i2s_interrupt_divide & 0x00FF) | ((uint32)data << 8);
 639                 else
 640                         jerry_i2s_interrupt_divide = (jerry_i2s_interrupt_divide & 0xFF00) | (uint32)data;
 641
 642                 jerry_i2s_interrupt_timer = -1;
 643 #ifndef NEW_TIMER_SYSTEM
 644                 jerry_i2s_exec(0);
 645 #else
 646                 RemoveCallback(JERRYI2SCallback);
 647                 JERRYI2SCallback();
 648 #endif
 649 //              return;
 650         }
 651         // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
 652         else if (offset >= 0xF1A148 && offset <= 0xF1A157)
 653         {
 654                 DACWriteByte(offset, data, who);
 655                 return;
 656         }
 657         else if (offset >= 0xF10000 && offset <= 0xF10007)
 658         {
 659 #ifndef NEW_TIMER_SYSTEM
 660                 switch (offset & 0x07)
 661                 {
 662                 case 0:
 663                         JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0x00FF) | (data << 8);
 664                         JERRYResetPIT1();
 665                         break;
 666                 case 1:
 667                         JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0xFF00) | data;
 668                         JERRYResetPIT1();
 669                         break;
 670                 case 2:
 671                         JERRYPIT1Divider = (JERRYPIT1Divider & 0x00FF) | (data << 8);
 672                         JERRYResetPIT1();
 673                         break;
 674                 case 3:
 675                         JERRYPIT1Divider = (JERRYPIT1Divider & 0xFF00) | data;
 676                         JERRYResetPIT1();
 677                         break;
 678                 case 4:
 679                         JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0x00FF) | (data << 8);
 680                         JERRYResetPIT2();
 681                         break;
 682                 case 5:
 683                         JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0xFF00) | data;
 684                         JERRYResetPIT2();
 685                         break;
 686                 case 6:
 687                         JERRYPIT2Divider = (JERRYPIT2Divider & 0x00FF) | (data << 8);
 688                         JERRYResetPIT2();
 689                         break;
 690                 case 7:
 691                         JERRYPIT2Divider = (JERRYPIT2Divider & 0xFF00) | data;
 692                         JERRYResetPIT2();
 693                 }
 694 #else
 695 WriteLog("JERRY: Unhandled timer write (BYTE) at %08X...\n", offset);
 696 #endif
 697                 return;
 698         }
 699 /*      else if ((offset >= 0xF10010) && (offset <= 0xF10015))
 700         {
 701                 clock_byte_write(offset, data);
 702                 return;
 703         }//*/
 704         // JERRY -> 68K interrupt enables/latches (need to be handled!)
 705         else if (offset >= 0xF10020 && offset <= 0xF10023)
 706         {
 707 WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%02X to $%08X!\n", data, offset);
 708         }
 709 /*      else if ((offset >= 0xF17C00) && (offset <= 0xF17C01))
 710         {
 711                 anajoy_byte_write(offset, data);
 712                 return;
 713         }*/
 714         else if ((offset >= 0xF14000) && (offset <= 0xF14003))
 715         {
 716                 joystick_byte_write(offset, data);
 717                 eeprom_byte_write(offset, data);
 718                 return;
 719         }
 720         else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
 721         {
 722                 eeprom_byte_write(offset, data);
 723                 return;
 724         }
 725
 726 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
 727         if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
 728                 return;
 729
 730         jerry_ram_8[offset & 0xFFFF] = data;
 731 }
 732
 733 //
 734 // JERRY word access (write)
 735 //
 736 void JERRYWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
 737 {
 738 #ifdef JERRY_DEBUG
 739         WriteLog( "JERRY: Writing word %04X at %06X\n", data, offset);
 740 #endif
 741
 742         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 743         {
 744                 DSPWriteWord(offset, data, who);
 745                 return;
 746         }
 747         else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
 748         {
 749                 DSPWriteWord(offset, data, who);
 750                 return;
 751         }
 752 //NOTE: This should be taken care of in DAC...
 753         else if (offset == 0xF1A152)                                    // Bottom half of SCLK ($F1A150)
 754         {
 755                 WriteLog("JERRY: Writing %04X to SCLK (by %s)...\n", data, whoName[who]);
 756 //This should *only* be enabled when SMODE has its INTERNAL bit set! !!! FIX !!!
 757                 jerry_i2s_interrupt_divide = (uint8)data;
 758                 jerry_i2s_interrupt_timer = -1;
 759 #ifndef NEW_TIMER_SYSTEM
 760                 jerry_i2s_exec(0);
 761 #else
 762                 RemoveCallback(JERRYI2SCallback);
 763                 JERRYI2SCallback();
 764 #endif
 765
 766                 DACWriteWord(offset, data, who);
 767                 return;
 768         }
 769         // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
 770         else if (offset >= 0xF1A148 && offset <= 0xF1A156)
 771         {
 772                 DACWriteWord(offset, data, who);
 773                 return;
 774         }
 775         else if (offset >= 0xF10000 && offset <= 0xF10007)
 776         {
 777 //#ifndef NEW_TIMER_SYSTEM
 778 #if 1
 779                 switch(offset & 0x07)
 780                 {
 781                 case 0:
 782                         JERRYPIT1Prescaler = data;
 783                         JERRYResetPIT1();
 784                         break;
 785                 case 2:
 786                         JERRYPIT1Divider = data;
 787                         JERRYResetPIT1();
 788                         break;
 789                 case 4:
 790                         JERRYPIT2Prescaler = data;
 791                         JERRYResetPIT2();
 792                         break;
 793                 case 6:
 794                         JERRYPIT2Divider = data;
 795                         JERRYResetPIT2();
 796                 }
 797                 // Need to handle (unaligned) cases???
 798 #else
 799 WriteLog("JERRY: Unhandled timer write %04X (WORD) at %08X by %s...\n", data, offset, whoName[who]);
 800 #endif
 801                 return;
 802         }
 803 /*      else if (offset >= 0xF10010 && offset < 0xF10016)
 804         {
 805                 clock_word_write(offset, data);
 806                 return;
 807         }//*/
 808         // JERRY -> 68K interrupt enables/latches (need to be handled!)
 809         else if (offset >= 0xF10020 && offset <= 0xF10022)
 810         {
 811 WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%04X to $%08X!\n", data, offset);
 812         }
 813 /*      else if (offset >= 0xF17C00 && offset < 0xF17C02)
 814         {
 815 //I think this was removed from the Jaguar. If so, then we don't need this...!
 816                 anajoy_word_write(offset, data);
 817                 return;
 818         }*/
 819         else if (offset >= 0xF14000 && offset < 0xF14003)
 820         {
 821                 joystick_word_write(offset, data);
 822                 eeprom_word_write(offset, data);
 823                 return;
 824         }
 825         else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
 826         {
 827                 eeprom_word_write(offset, data);
 828                 return;
 829         }
 830
 831 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
 832         if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
 833                 return;
 834
 835         jerry_ram_8[(offset+0) & 0xFFFF] = (data >> 8) & 0xFF;
 836         jerry_ram_8[(offset+1) & 0xFFFF] = data & 0xFF;
 837 }