Shamusworld >> Repos - virtualjaguar/blob - src/jerry.cpp

   1 //
   2 // JERRY Core
   3 //
   4 // Originally by David Raingeard
   5 // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS)
   6 // Cleanups/rewrites/fixes by James L. Hammons
   7 //
   8 //      ------------------------------------------------------------
   9 //      JERRY REGISTERS (Mapped by Aaron Giles)
  10 //      ------------------------------------------------------------
  11 //      F10000-F13FFF   R/W   xxxxxxxx xxxxxxxx   Jerry
  12 //      F10000            W   xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
  13 //      F10002            W   xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
  14 //      F10004            W   xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
  15 //      F10008            W   xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
  16 //      F10010            W   ------xx xxxxxxxx   CLK1 - processor clock divider
  17 //      F10012            W   ------xx xxxxxxxx   CLK2 - video clock divider
  18 //      F10014            W   -------- --xxxxxx   CLK3 - chroma clock divider
  19 //      F10020          R/W   ---xxxxx ---xxxxx   JINTCTRL - interrupt control register
  20 //                        W   ---x---- --------      (J_SYNCLR - clear synchronous serial intf ints)
  21 //                        W   ----x--- --------      (J_ASYNCLR - clear asynchronous serial intf ints)
  22 //                        W   -----x-- --------      (J_TIM2CLR - clear timer 2 [tempo] interrupts)
  23 //                        W   ------x- --------      (J_TIM1CLR - clear timer 1 [sample] interrupts)
  24 //                        W   -------x --------      (J_EXTCLR - clear external interrupts)
  25 //                      R/W   -------- ---x----      (J_SYNENA - enable synchronous serial intf ints)
  26 //                      R/W   -------- ----x---      (J_ASYNENA - enable asynchronous serial intf ints)
  27 //                      R/W   -------- -----x--      (J_TIM2ENA - enable timer 2 [tempo] interrupts)
  28 //                      R/W   -------- ------x-      (J_TIM1ENA - enable timer 1 [sample] interrupts)
  29 //                      R/W   -------- -------x      (J_EXTENA - enable external interrupts)
  30 //      F10030          R/W   -------- xxxxxxxx   ASIDATA - asynchronous serial data
  31 //      F10032            W   -x------ -xxxxxxx   ASICTRL - asynchronous serial control
  32 //                        W   -x------ --------      (TXBRK - transmit break)
  33 //                        W   -------- -x------      (CLRERR - clear error)
  34 //                        W   -------- --x-----      (RINTEN - enable receiver interrupts)
  35 //                        W   -------- ---x----      (TINTEN - enable transmitter interrupts)
  36 //                        W   -------- ----x---      (RXIPOL - receiver input polarity)
  37 //                        W   -------- -----x--      (TXOPOL - transmitter output polarity)
  38 //                        W   -------- ------x-      (PAREN - parity enable)
  39 //                        W   -------- -------x      (ODD - odd parity select)
  40 //      F10032          R     xxx-xxxx x-xxxxxx   ASISTAT - asynchronous serial status
  41 //                      R     x------- --------      (ERROR - OR of PE,FE,OE)
  42 //                      R     -x------ --------      (TXBRK - transmit break)
  43 //                      R     --x----- --------      (SERIN - serial input)
  44 //                      R     ----x--- --------      (OE - overrun error)
  45 //                      R     -----x-- --------      (FE - framing error)
  46 //                      R     ------x- --------      (PE - parity error)
  47 //                      R     -------x --------      (TBE - transmit buffer empty)
  48 //                      R     -------- x-------      (RBF - receive buffer full)
  49 //                      R     -------- ---x----      (TINTEN - enable transmitter interrupts)
  50 //                      R     -------- ----x---      (RXIPOL - receiver input polarity)
  51 //                      R     -------- -----x--      (TXOPOL - transmitter output polarity)
  52 //                      R     -------- ------x-      (PAREN - parity enable)
  53 //                      R     -------- -------x      (ODD - odd parity)
  54 //      F10034          R/W   xxxxxxxx xxxxxxxx   ASICLK - asynchronous serial interface clock
  55 //      F10036          R     xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
  56 //      F10038          R     xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
  57 //      F1003A          R     xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
  58 //      F1003C          R     xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
  59 //      ------------------------------------------------------------
  60 //      F14000-F17FFF   R/W   xxxxxxxx xxxxxxxx   Joysticks and GPIO0-5
  61 //      F14000          R     xxxxxxxx xxxxxxxx   JOYSTICK - read joystick state
  62 //      F14000            W   x------- xxxxxxxx   JOYSTICK - latch joystick output
  63 //                        W   x------- --------      (enable joystick outputs)
  64 //                        W   -------- xxxxxxxx      (joystick output data)
  65 //      F14002          R     xxxxxxxx xxxxxxxx   JOYBUTS - button register
  66 //      F14800-F14FFF   R/W   xxxxxxxx xxxxxxxx   GPI00 - reserved (CD-ROM?)
  67 //      F15000-F15FFF   R/W   xxxxxxxx xxxxxxxx   GPI01 - reserved
  68 //      F16000-F16FFF   R/W   xxxxxxxx xxxxxxxx   GPI02 - reserved
  69 //      F17000-F177FF   R/W   xxxxxxxx xxxxxxxx   GPI03 - reserved
  70 //      F17800-F17BFF   R/W   xxxxxxxx xxxxxxxx   GPI04 - reserved
  71 //      F17C00-F17FFF   R/W   xxxxxxxx xxxxxxxx   GPI05 - reserved
  72 //      ------------------------------------------------------------
  73 //      F18000-F1FFFF   R/W   xxxxxxxx xxxxxxxx   Jerry DSP
  74 //      F1A100          R/W   xxxxxxxx xxxxxxxx   D_FLAGS - DSP flags register
  75 //                      R/W   x------- --------      (DMAEN - DMA enable)
  76 //                      R/W   -x------ --------      (REGPAGE - register page)
  77 //                        W   --x----- --------      (D_EXT0CLR - clear external interrupt 0)
  78 //                        W   ---x---- --------      (D_TIM2CLR - clear timer 2 interrupt)
  79 //                        W   ----x--- --------      (D_TIM1CLR - clear timer 1 interrupt)
  80 //                        W   -----x-- --------      (D_I2SCLR - clear I2S interrupt)
  81 //                        W   ------x- --------      (D_CPUCLR - clear CPU interrupt)
  82 //                      R/W   -------x --------      (D_EXT0ENA - enable external interrupt 0)
  83 //                      R/W   -------- x-------      (D_TIM2ENA - enable timer 2 interrupt)
  84 //                      R/W   -------- -x------      (D_TIM1ENA - enable timer 1 interrupt)
  85 //                      R/W   -------- --x-----      (D_I2SENA - enable I2S interrupt)
  86 //                      R/W   -------- ---x----      (D_CPUENA - enable CPU interrupt)
  87 //                      R/W   -------- ----x---      (IMASK - interrupt mask)
  88 //                      R/W   -------- -----x--      (NEGA_FLAG - ALU negative)
  89 //                      R/W   -------- ------x-      (CARRY_FLAG - ALU carry)
  90 //                      R/W   -------- -------x      (ZERO_FLAG - ALU zero)
  91 //      F1A102          R/W   -------- ------xx   D_FLAGS - upper DSP flags
  92 //                      R/W   -------- ------x-      (D_EXT1ENA - enable external interrupt 1)
  93 //                      R/W   -------- -------x      (D_EXT1CLR - clear external interrupt 1)
  94 //      F1A104            W   -------- ----xxxx   D_MTXC - matrix control register
  95 //                        W   -------- ----x---      (MATCOL - column/row major)
  96 //                        W   -------- -----xxx      (MATRIX3-15 - matrix width)
  97 //      F1A108            W   ----xxxx xxxxxx--   D_MTXA - matrix address register
  98 //      F1A10C            W   -------- -----x-x   D_END - data organization register
  99 //                        W   -------- -----x--      (BIG_INST - big endian instruction fetch)
 100 //                        W   -------- -------x      (BIG_IO - big endian I/O)
 101 //      F1A110          R/W   xxxxxxxx xxxxxxxx   D_PC - DSP program counter
 102 //      F1A114          R/W   xxxxxxxx xx-xxxxx   D_CTRL - DSP control/status register
 103 //                      R     xxxx---- --------      (VERSION - DSP version code)
 104 //                      R/W   ----x--- --------      (BUS_HOG - hog the bus!)
 105 //                      R/W   -----x-- --------      (D_EXT0LAT - external interrupt 0 latch)
 106 //                      R/W   ------x- --------      (D_TIM2LAT - timer 2 interrupt latch)
 107 //                      R/W   -------x --------      (D_TIM1LAT - timer 1 interrupt latch)
 108 //                      R/W   -------- x-------      (D_I2SLAT - I2S interrupt latch)
 109 //                      R/W   -------- -x------      (D_CPULAT - CPU interrupt latch)
 110 //                      R/W   -------- ---x----      (SINGLE_GO - single step one instruction)
 111 //                      R/W   -------- ----x---      (SINGLE_STEP - single step mode)
 112 //                      R/W   -------- -----x--      (FORCEINT0 - cause interrupt 0 on GPU)
 113 //                      R/W   -------- ------x-      (CPUINT - send GPU interrupt to CPU)
 114 //                      R/W   -------- -------x      (DSPGO - enable DSP execution)
 115 //      F1A116          R/W   -------- -------x   D_CTRL - upper DSP control/status register
 116 //                      R/W   -------- -------x      (D_EXT1LAT - external interrupt 1 latch)
 117 //      F1A118-F1A11B     W   xxxxxxxx xxxxxxxx   D_MOD - modulo instruction mask
 118 //      F1A11C-F1A11F   R     xxxxxxxx xxxxxxxx   D_REMAIN - divide unit remainder
 119 //      F1A11C            W   -------- -------x   D_DIVCTRL - divide unit control
 120 //                        W   -------- -------x      (DIV_OFFSET - 1=16.16 divide, 0=32-bit divide)
 121 //      F1A120-F1A123   R     xxxxxxxx xxxxxxxx   D_MACHI - multiply & accumulate high bits
 122 //      F1A148            W   xxxxxxxx xxxxxxxx   R_DAC - right transmit data
 123 //      F1A14C            W   xxxxxxxx xxxxxxxx   L_DAC - left transmit data
 124 //      F1A150            W   -------- xxxxxxxx   SCLK - serial clock frequency
 125 //      F1A150          R     -------- ------xx   SSTAT
 126 //                      R     -------- ------x-      (left - no description)
 127 //                      R     -------- -------x      (WS - word strobe status)
 128 //      F1A154            W   -------- --xxxx-x   SMODE - serial mode
 129 //                        W   -------- --x-----      (EVERYWORD - interrupt on MSB of every word)
 130 //                        W   -------- ---x----      (FALLING - interrupt on falling edge)
 131 //                        W   -------- ----x---      (RISING - interrupt of rising edge)
 132 //                        W   -------- -----x--      (WSEN - enable word strobes)
 133 //                        W   -------- -------x      (INTERNAL - enables serial clock)
 134 //      ------------------------------------------------------------
 135 //      F1B000-F1CFFF   R/W   xxxxxxxx xxxxxxxx   Local DSP RAM
 136 //      ------------------------------------------------------------
 137 //      F1D000          R     xxxxxxxx xxxxxxxx   ROM_TRI - triangle wave
 138 //      F1D200          R     xxxxxxxx xxxxxxxx   ROM_SINE - full sine wave
 139 //      F1D400          R     xxxxxxxx xxxxxxxx   ROM_AMSINE - amplitude modulated sine wave
 140 //      F1D600          R     xxxxxxxx xxxxxxxx   ROM_12W - sine wave and second order harmonic
 141 //      F1D800          R     xxxxxxxx xxxxxxxx   ROM_CHIRP16 - chirp
 142 //      F1DA00          R     xxxxxxxx xxxxxxxx   ROM_NTRI - traingle wave with noise
 143 //      F1DC00          R     xxxxxxxx xxxxxxxx   ROM_DELTA - spike
 144 //      F1DE00          R     xxxxxxxx xxxxxxxx   ROM_NOISE - white noise
 145 //      ------------------------------------------------------------
 146
 147 //#include <math.h>
 148 #include "jaguar.h"
 149 #include "wavetable.h"
 150 #include "jerry.h"
 151 #include "clock.h"
 152
 153 //Note that 44100 Hz requires samples every 22.675737 usec.
 154 #define NEW_TIMER_SYSTEM
 155 //#define JERRY_DEBUG
 156
 157 /*static*/ uint8 * jerry_ram_8;
 158
 159 //#define JERRY_CONFIG  0x4002                                          // ??? What's this ???
 160
 161 uint8 analog_x, analog_y;
 162
 163 static uint32 JERRYPIT1Prescaler;
 164 static uint32 JERRYPIT1Divider;
 165 static uint32 JERRYPIT2Prescaler;
 166 static uint32 JERRYPIT2Divider;
 167 static int32 jerry_timer_1_counter;
 168 static int32 jerry_timer_2_counter;
 169
 170 static uint32 jerry_i2s_interrupt_divide = 8;
 171 static int32 jerry_i2s_interrupt_timer = -1;
 172 uint32 jerryI2SCycles;
 173 uint32 jerryIntPending;
 174
 175 // Private function prototypes
 176
 177 void JERRYResetPIT1(void);
 178 void JERRYResetPIT2(void);
 179 void JERRYResetI2S(void);
 180
 181 void JERRYPIT1Callback(void);
 182 void JERRYPIT2Callback(void);
 183 void JERRYI2SCallback(void);
 184
 185 //This approach is probably wrong, since the timer is continuously counting down, though
 186 //it might only be a problem if the # of interrupts generated is greater than 1--the M68K's
 187 //timeslice should be running during that phase... (The DSP needs to be aware of this!)
 188 void jerry_i2s_exec(uint32 cycles)
 189 {
 190 #ifndef NEW_TIMER_SYSTEM
 191         extern uint16 serialMode;                                               // From DAC.CPP
 192         if (serialMode & 0x01)                                                  // INTERNAL flag (JERRY is master)
 193         {
 194
 195         // Why is it called this? Instead of SCLK? Shouldn't this be read from DAC.CPP???
 196 //Yes, it should. !!! FIX !!!
 197                 jerry_i2s_interrupt_divide &= 0xFF;
 198
 199                 if (jerry_i2s_interrupt_timer == -1)
 200                 {
 201                 // We don't have to divide the RISC clock rate by this--the reason is a bit
 202                 // convoluted. Will put explanation here later...
 203 // What's needed here is to find the ratio of the frequency to the number of clock cycles
 204 // in one second. For example, if the sample rate is 44100, we divide the clock rate by
 205 // this: 26590906 / 44100 = 602 cycles.
 206 // Which means, every 602 cycles that go by we have to generate an interrupt.
 207                         jerryI2SCycles = 32 * (2 * (jerry_i2s_interrupt_divide + 1));
 208                 }
 209
 210                 jerry_i2s_interrupt_timer -= cycles;
 211                 if (jerry_i2s_interrupt_timer <= 0)
 212                 {
 213 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!!
 214                         DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
 215                         jerry_i2s_interrupt_timer += jerryI2SCycles;
 216 #ifdef JERRY_DEBUG
 217                         if (jerry_i2s_interrupt_timer < 0)
 218                                 WriteLog("JERRY: Missed generating an interrupt (missed %u)!\n", (-jerry_i2s_interrupt_timer / jerryI2SCycles) + 1);
 219 #endif
 220                 }
 221         }
 222         else                                                                                    // JERRY is slave to external word clock
 223         {
 224                 // This is just a temporary kludge to see if the CD bus mastering works
 225                 // I.e., this is totally faked...!
 226 // The whole interrupt system is pretty much borked and is need of an overhaul.
 227 // What we need is a way of handling these interrupts when they happen instead of
 228 // scanline boundaries the way it is now.
 229                 jerry_i2s_interrupt_timer -= cycles;
 230                 if (jerry_i2s_interrupt_timer <= 0)
 231                 {
 232 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!! [DONE]
 233                         if (ButchIsReadyToSend())//Not sure this is right spot to check...
 234                         {
 235 //      return GetWordFromButchSSI(offset, who);
 236                                 SetSSIWordsXmittedFromButch();
 237                                 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
 238                         }
 239                         jerry_i2s_interrupt_timer += 602;
 240                 }
 241         }
 242 #else
 243         RemoveCallback(JERRYI2SCallback);
 244         JERRYI2SCallback();
 245 #endif
 246 }
 247
 248 void JERRYExecPIT(uint32 cycles)
 249 {
 250 //This is wrong too: Counters are *always* spinning! !!! FIX !!! [DONE]
 251 //      if (jerry_timer_1_counter)
 252                 jerry_timer_1_counter -= cycles;
 253
 254         if (jerry_timer_1_counter <= 0)
 255         {
 256 //Also, it can generate a CPU interrupt as well... !!! FIX !!! or does it? Maybe it goes Timer->GPU->CPU?
 257                 DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 258 //              JERRYResetPIT1();
 259                 jerry_timer_1_counter += (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 260         }
 261
 262 //This is wrong too: Counters are *always* spinning! !!! FIX !!! [DONE]
 263 //      if (jerry_timer_2_counter)
 264                 jerry_timer_2_counter -= cycles;
 265
 266         if (jerry_timer_2_counter <= 0)
 267         {
 268 //Also, it can generate a CPU interrupt as well... !!! FIX !!! or does it? Maybe it goes Timer->GPU->CPU?
 269                 DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 270 //              JERRYResetPIT2();
 271                 jerry_timer_2_counter += (JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1);
 272         }
 273 }
 274
 275 void JERRYResetI2S(void)
 276 {
 277         //WriteLog("i2s: reseting\n");
 278 //This is really SCLK... !!! FIX !!!
 279         jerry_i2s_interrupt_divide = 8;
 280         jerry_i2s_interrupt_timer = -1;
 281 }
 282
 283 void JERRYResetPIT1(void)
 284 {
 285 #ifndef NEW_TIMER_SYSTEM
 286 /*      if (!JERRYPIT1Prescaler || !JERRYPIT1Divider)
 287                 jerry_timer_1_counter = 0;
 288         else//*/
 289 //Small problem with this approach: Overflow if both are = $FFFF. !!! FIX !!!
 290                 jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 291
 292 //      if (jerry_timer_1_counter)
 293 //              WriteLog("jerry: reseting timer 1 to 0x%.8x (%i)\n",jerry_timer_1_counter,jerry_timer_1_counter);
 294
 295 #else
 296         RemoveCallback(JERRYPIT1Callback);
 297         double usecs = (float)(JERRYPIT1Prescaler + 1) * (float)(JERRYPIT1Divider + 1) * RISC_CYCLE_IN_USEC;
 298         SetCallbackTime(JERRYPIT1Callback, usecs);
 299 #endif
 300 }
 301
 302 void JERRYResetPIT2(void)
 303 {
 304 #ifndef NEW_TIMER_SYSTEM
 305 /*      if (!JERRYPIT2Prescaler || !JERRYPIT2Divider)
 306         {
 307                 jerry_timer_2_counter = 0;
 308                 return;
 309         }
 310         else//*/
 311                 jerry_timer_2_counter = (JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1);
 312
 313 //      if (jerry_timer_2_counter)
 314 //              WriteLog("jerry: reseting timer 2 to 0x%.8x (%i)\n",jerry_timer_2_counter,jerry_timer_2_counter);
 315
 316 #else
 317         RemoveCallback(JERRYPIT2Callback);
 318         double usecs = (float)(JERRYPIT2Prescaler + 1) * (float)(JERRYPIT2Divider + 1) * RISC_CYCLE_IN_USEC;
 319         SetCallbackTime(JERRYPIT2Callback, usecs);
 320 #endif
 321 }
 322
 323 void JERRYPIT1Callback(void)
 324 {
 325         DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 326         JERRYResetPIT1();
 327 }
 328
 329 void JERRYPIT2Callback(void)
 330 {
 331         DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE);      // This does the 'IRQ enabled' checking...
 332         JERRYResetPIT2();
 333 }
 334
 335 void JERRYI2SCallback(void)
 336 {
 337         // Why is it called this? Instead of SCLK? Shouldn't this be read from DAC.CPP???
 338 //Yes, it should. !!! FIX !!!
 339         jerry_i2s_interrupt_divide &= 0xFF;
 340         // We don't have to divide the RISC clock rate by this--the reason is a bit
 341         // convoluted. Will put explanation here later...
 342 // What's needed here is to find the ratio of the frequency to the number of clock cycles
 343 // in one second. For example, if the sample rate is 44100, we divide the clock rate by
 344 // this: 26590906 / 44100 = 602 cycles.
 345 // Which means, every 602 cycles that go by we have to generate an interrupt.
 346         jerryI2SCycles = 32 * (2 * (jerry_i2s_interrupt_divide + 1));
 347
 348 //This should be in this file with an extern reference in the header file so that
 349 //DAC.CPP can see it... !!! FIX !!!
 350         extern uint16 serialMode;                                               // From DAC.CPP
 351
 352         if (serialMode & 0x01)                                                  // INTERNAL flag (JERRY is master)
 353         {
 354                 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);         // This does the 'IRQ enabled' checking...
 355                 double usecs = (float)jerryI2SCycles * RISC_CYCLE_IN_USEC;
 356                 SetCallbackTime(JERRYI2SCallback, usecs);
 357         }
 358         else                                                                                    // JERRY is slave to external word clock
 359         {
 360 //Note that 44100 Hz requires samples every 22.675737 usec.
 361 //When JERRY is slave to the word clock, we need to do interrupts either at 44.1K
 362 //sample rate or at a 88.2K sample rate (11.332... usec).
 363 /*              // This is just a temporary kludge to see if the CD bus mastering works
 364                 // I.e., this is totally faked...!
 365 // The whole interrupt system is pretty much borked and is need of an overhaul.
 366 // What we need is a way of handling these interrupts when they happen instead of
 367 // scanline boundaries the way it is now.
 368                 jerry_i2s_interrupt_timer -= cycles;
 369                 if (jerry_i2s_interrupt_timer <= 0)
 370                 {
 371 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!! [DONE]
 372                         if (ButchIsReadyToSend())//Not sure this is right spot to check...
 373                         {
 374 //      return GetWordFromButchSSI(offset, who);
 375                                 SetSSIWordsXmittedFromButch();
 376                                 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
 377                         }
 378                         jerry_i2s_interrupt_timer += 602;
 379                 }*/
 380         }
 381 }
 382
 383
 384 void jerry_init(void)
 385 {
 386 //      clock_init();
 387 //      anajoy_init();
 388         joystick_init();
 389         DACInit();
 390 //This should be handled with the cart initialization...
 391 //      eeprom_init();
 392         memory_malloc_secure((void **)&jerry_ram_8, 0x10000, "JERRY RAM/ROM");
 393         memcpy(&jerry_ram_8[0xD000], wave_table, 0x1000);
 394
 395         JERRYPIT1Prescaler = 0xFFFF;
 396         JERRYPIT2Prescaler = 0xFFFF;
 397         JERRYPIT1Divider = 0xFFFF;
 398         JERRYPIT2Divider = 0xFFFF;
 399 }
 400
 401 void jerry_reset(void)
 402 {
 403 //      clock_reset();
 404 //      anajoy_reset();
 405         joystick_reset();
 406         eeprom_reset();
 407         JERRYResetI2S();
 408         DACReset();
 409
 410         memset(jerry_ram_8, 0x00, 0xD000);              // Don't clear out the Wavetable ROM...!
 411         JERRYPIT1Prescaler = 0xFFFF;
 412         JERRYPIT2Prescaler = 0xFFFF;
 413         JERRYPIT1Divider = 0xFFFF;
 414         JERRYPIT2Divider = 0xFFFF;
 415         jerry_timer_1_counter = 0;
 416         jerry_timer_2_counter = 0;
 417 }
 418
 419 void jerry_done(void)
 420 {
 421         WriteLog("JERRY: M68K Interrupt control ($F10020) = %04X\n", GET16(jerry_ram_8, 0x20));
 422         memory_free(jerry_ram_8);
 423 //      clock_done();
 424 //      anajoy_done();
 425         joystick_done();
 426         DACDone();
 427         eeprom_done();
 428 }
 429
 430 bool JERRYIRQEnabled(int irq)
 431 {
 432         // Read the word @ $F10020
 433         return jerry_ram_8[0x21] & (1 << irq);
 434 }
 435
 436 void JERRYSetPendingIRQ(int irq)
 437 {
 438         // This is the shadow of INT (it's a split RO/WO register)
 439         jerryIntPending |= (1 << irq);
 440 }
 441
 442 //
 443 // JERRY byte access (read)
 444 //
 445 uint8 JERRYReadByte(uint32 offset, uint32 who/*=UNKNOWN*/)
 446 {
 447 #ifdef JERRY_DEBUG
 448         WriteLog("JERRY: Reading byte at %06X\n", offset);
 449 #endif
 450         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 451                 return DSPReadByte(offset, who);
 452         else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
 453                 return DSPReadByte(offset, who);
 454         // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
 455         else if (offset >= 0xF1A148 && offset <= 0xF1A153)
 456                 return DACReadByte(offset, who);
 457 //      F10036          R     xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
 458 //      F10038          R     xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
 459 //      F1003A          R     xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
 460 //      F1003C          R     xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
 461 //This is WRONG!
 462 //      else if (offset >= 0xF10000 && offset <= 0xF10007)
 463 //This is still wrong. What needs to be returned here are the values being counted down
 464 //in the jerry_timer_n_counter variables... !!! FIX !!! [DONE]
 465
 466 //This is probably the problem with the new timer code... This is invalid
 467 //under the new system... !!! FIX !!!
 468         else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
 469         {
 470 #ifndef NEW_TIMER_SYSTEM
 471 //              jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 472                 uint32 counter1Hi = (jerry_timer_1_counter / (JERRYPIT1Divider + 1)) - 1;
 473                 uint32 counter1Lo = (jerry_timer_1_counter % (JERRYPIT1Divider + 1)) - 1;
 474                 uint32 counter2Hi = (jerry_timer_2_counter / (JERRYPIT2Divider + 1)) - 1;
 475                 uint32 counter2Lo = (jerry_timer_2_counter % (JERRYPIT2Divider + 1)) - 1;
 476
 477                 switch(offset & 0x0F)
 478                 {
 479                 case 6:
 480 //                      return JERRYPIT1Prescaler >> 8;
 481                         return counter1Hi >> 8;
 482                 case 7:
 483 //                      return JERRYPIT1Prescaler & 0xFF;
 484                         return counter1Hi & 0xFF;
 485                 case 8:
 486 //                      return JERRYPIT1Divider >> 8;
 487                         return counter1Lo >> 8;
 488                 case 9:
 489 //                      return JERRYPIT1Divider & 0xFF;
 490                         return counter1Lo & 0xFF;
 491                 case 10:
 492 //                      return JERRYPIT2Prescaler >> 8;
 493                         return counter2Hi >> 8;
 494                 case 11:
 495 //                      return JERRYPIT2Prescaler & 0xFF;
 496                         return counter2Hi & 0xFF;
 497                 case 12:
 498 //                      return JERRYPIT2Divider >> 8;
 499                         return counter2Lo >> 8;
 500                 case 13:
 501 //                      return JERRYPIT2Divider & 0xFF;
 502                         return counter2Lo & 0xFF;
 503                 }
 504 #else
 505 #endif
 506         }
 507 //      else if (offset >= 0xF10010 && offset <= 0xF10015)
 508 //              return clock_byte_read(offset);
 509 //      else if (offset >= 0xF17C00 && offset <= 0xF17C01)
 510 //              return anajoy_byte_read(offset);
 511         else if (offset >= 0xF14000 && offset <= 0xF14003)
 512                 return joystick_byte_read(offset) | eeprom_byte_read(offset);
 513         else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
 514                 return eeprom_byte_read(offset);
 515
 516         return jerry_ram_8[offset & 0xFFFF];
 517 }
 518
 519 //
 520 // JERRY word access (read)
 521 //
 522 uint16 JERRYReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
 523 {
 524 #ifdef JERRY_DEBUG
 525         WriteLog("JERRY: Reading word at %06X\n", offset);
 526 #endif
 527
 528         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 529                 return DSPReadWord(offset, who);
 530         else if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE + 0x1FFF)
 531                 return DSPReadWord(offset, who);
 532         // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
 533         else if (offset >= 0xF1A148 && offset <= 0xF1A153)
 534                 return DACReadWord(offset, who);
 535 //      F10036          R     xxxxxxxx xxxxxxxx   JPIT1 - timer 1 pre-scaler
 536 //      F10038          R     xxxxxxxx xxxxxxxx   JPIT2 - timer 1 divider
 537 //      F1003A          R     xxxxxxxx xxxxxxxx   JPIT3 - timer 2 pre-scaler
 538 //      F1003C          R     xxxxxxxx xxxxxxxx   JPIT4 - timer 2 divider
 539 //This is WRONG!
 540 //      else if ((offset >= 0xF10000) && (offset <= 0xF10007))
 541 //This is still wrong. What needs to be returned here are the values being counted down
 542 //in the jerry_timer_n_counter variables... !!! FIX !!! [DONE]
 543         else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
 544         {
 545 //              jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
 546                 uint32 counter1Hi = (jerry_timer_1_counter / (JERRYPIT1Divider + 1)) - 1;
 547                 uint32 counter1Lo = (jerry_timer_1_counter % (JERRYPIT1Divider + 1)) - 1;
 548                 uint32 counter2Hi = (jerry_timer_2_counter / (JERRYPIT2Divider + 1)) - 1;
 549                 uint32 counter2Lo = (jerry_timer_2_counter % (JERRYPIT2Divider + 1)) - 1;
 550
 551                 switch(offset & 0x0F)
 552                 {
 553                 case 6:
 554 //                      return JERRYPIT1Prescaler;
 555                         return counter1Hi;
 556                 case 8:
 557 //                      return JERRYPIT1Divider;
 558                         return counter1Lo;
 559                 case 10:
 560 //                      return JERRYPIT2Prescaler;
 561                         return counter2Hi;
 562                 case 12:
 563 //                      return JERRYPIT2Divider;
 564                         return counter2Lo;
 565                 }
 566                 // Unaligned word reads???
 567         }
 568 //      else if ((offset >= 0xF10010) && (offset <= 0xF10015))
 569 //              return clock_word_read(offset);
 570         else if (offset == 0xF10020)
 571                 return jerryIntPending;
 572 //      else if ((offset >= 0xF17C00) && (offset <= 0xF17C01))
 573 //              return anajoy_word_read(offset);
 574         else if (offset == 0xF14000)
 575                 return (joystick_word_read(offset) & 0xFFFE) | eeprom_word_read(offset);
 576         else if ((offset >= 0xF14002) && (offset < 0xF14003))
 577                 return joystick_word_read(offset);
 578         else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
 579                 return eeprom_word_read(offset);
 580
 581 /*if (offset >= 0xF1D000)
 582         WriteLog("JERRY: Reading word at %08X [%04X]...\n", offset, ((uint16)jerry_ram_8[(offset+0)&0xFFFF] << 8) | jerry_ram_8[(offset+1)&0xFFFF]);//*/
 583
 584         offset &= 0xFFFF;                               // Prevent crashing...!
 585         return ((uint16)jerry_ram_8[offset+0] << 8) | jerry_ram_8[offset+1];
 586 }
 587
 588 //
 589 // JERRY byte access (write)
 590 //
 591 void JERRYWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
 592 {
 593 #ifdef JERRY_DEBUG
 594         WriteLog("jerry: writing byte %.2x at 0x%.6x\n",data,offset);
 595 #endif
 596         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 597         {
 598                 DSPWriteByte(offset, data, who);
 599                 return;
 600         }
 601         else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
 602         {
 603                 DSPWriteByte(offset, data, who);
 604                 return;
 605         }
 606         // SCLK ($F1A150--8 bits wide)
 607 //NOTE: This should be taken care of in DAC...
 608         else if ((offset >= 0xF1A152) && (offset <= 0xF1A153))
 609         {
 610 //              WriteLog("JERRY: Writing %02X to SCLK...\n", data);
 611                 if ((offset & 0x03) == 2)
 612                         jerry_i2s_interrupt_divide = (jerry_i2s_interrupt_divide & 0x00FF) | ((uint32)data << 8);
 613                 else
 614                         jerry_i2s_interrupt_divide = (jerry_i2s_interrupt_divide & 0xFF00) | (uint32)data;
 615
 616                 jerry_i2s_interrupt_timer = -1;
 617                 jerry_i2s_exec(0);
 618 //              return;
 619         }
 620         // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
 621         else if (offset >= 0xF1A148 && offset <= 0xF1A157)
 622         {
 623                 DACWriteByte(offset, data, who);
 624                 return;
 625         }
 626         else if (offset >= 0xF10000 && offset <= 0xF10007)
 627         {
 628                 switch (offset & 0x07)
 629                 {
 630                 case 0:
 631                         JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0x00FF) | (data << 8);
 632                         JERRYResetPIT1();
 633                         break;
 634                 case 1:
 635                         JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0xFF00) | data;
 636                         JERRYResetPIT1();
 637                         break;
 638                 case 2:
 639                         JERRYPIT1Divider = (JERRYPIT1Divider & 0x00FF) | (data << 8);
 640                         JERRYResetPIT1();
 641                         break;
 642                 case 3:
 643                         JERRYPIT1Divider = (JERRYPIT1Divider & 0xFF00) | data;
 644                         JERRYResetPIT1();
 645                         break;
 646                 case 4:
 647                         JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0x00FF) | (data << 8);
 648                         JERRYResetPIT2();
 649                         break;
 650                 case 5:
 651                         JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0xFF00) | data;
 652                         JERRYResetPIT2();
 653                         break;
 654                 case 6:
 655                         JERRYPIT2Divider = (JERRYPIT2Divider & 0x00FF) | (data << 8);
 656                         JERRYResetPIT2();
 657                         break;
 658                 case 7:
 659                         JERRYPIT2Divider = (JERRYPIT2Divider & 0xFF00) | data;
 660                         JERRYResetPIT2();
 661                 }
 662                 return;
 663         }
 664 /*      else if ((offset >= 0xF10010) && (offset <= 0xF10015))
 665         {
 666                 clock_byte_write(offset, data);
 667                 return;
 668         }//*/
 669         // JERRY -> 68K interrupt enables/latches (need to be handled!)
 670         else if (offset >= 0xF10020 && offset <= 0xF10023)
 671         {
 672 WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%02X to $%08X!\n", data, offset);
 673         }
 674 /*      else if ((offset >= 0xF17C00) && (offset <= 0xF17C01))
 675         {
 676                 anajoy_byte_write(offset, data);
 677                 return;
 678         }*/
 679         else if ((offset >= 0xF14000) && (offset <= 0xF14003))
 680         {
 681                 joystick_byte_write(offset, data);
 682                 eeprom_byte_write(offset, data);
 683                 return;
 684         }
 685         else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
 686         {
 687                 eeprom_byte_write(offset, data);
 688                 return;
 689         }
 690
 691 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
 692         if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
 693                 return;
 694
 695         jerry_ram_8[offset & 0xFFFF] = data;
 696 }
 697
 698 //
 699 // JERRY word access (write)
 700 //
 701 void JERRYWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
 702 {
 703 #ifdef JERRY_DEBUG
 704         WriteLog( "JERRY: Writing word %04X at %06X\n", data, offset);
 705 #endif
 706
 707         if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
 708         {
 709                 DSPWriteWord(offset, data, who);
 710                 return;
 711         }
 712         else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
 713         {
 714                 DSPWriteWord(offset, data, who);
 715                 return;
 716         }
 717 //NOTE: This should be taken care of in DAC...
 718         else if (offset == 0xF1A152)                                    // Bottom half of SCLK ($F1A150)
 719         {
 720                 WriteLog("JERRY: Writing %04X to SCLK (by %s)...\n", data, whoName[who]);
 721 //This should *only* be enabled when SMODE has its INTERNAL bit set! !!! FIX !!!
 722                 jerry_i2s_interrupt_divide = (uint8)data;
 723                 jerry_i2s_interrupt_timer = -1;
 724                 jerry_i2s_exec(0);
 725
 726                 DACWriteWord(offset, data, who);
 727                 return;
 728         }
 729         // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
 730         else if (offset >= 0xF1A148 && offset <= 0xF1A156)
 731         {
 732                 DACWriteWord(offset, data, who);
 733                 return;
 734         }
 735         else if (offset >= 0xF10000 && offset <= 0xF10007)
 736         {
 737                 switch(offset & 0x07)
 738                 {
 739                 case 0:
 740                         JERRYPIT1Prescaler = data;
 741                         JERRYResetPIT1();
 742                         break;
 743                 case 2:
 744                         JERRYPIT1Divider = data;
 745                         JERRYResetPIT1();
 746                         break;
 747                 case 4:
 748                         JERRYPIT2Prescaler = data;
 749                         JERRYResetPIT2();
 750                         break;
 751                 case 6:
 752                         JERRYPIT2Divider = data;
 753                         JERRYResetPIT2();
 754                 }
 755                 // Need to handle (unaligned) cases???
 756                 return;
 757         }
 758 /*      else if (offset >= 0xF10010 && offset < 0xF10016)
 759         {
 760                 clock_word_write(offset, data);
 761                 return;
 762         }//*/
 763         // JERRY -> 68K interrupt enables/latches (need to be handled!)
 764         else if (offset >= 0xF10020 && offset <= 0xF10022)
 765         {
 766 WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%04X to $%08X!\n", data, offset);
 767         }
 768 /*      else if (offset >= 0xF17C00 && offset < 0xF17C02)
 769         {
 770 //I think this was removed from the Jaguar. If so, then we don't need this...!
 771                 anajoy_word_write(offset, data);
 772                 return;
 773         }*/
 774         else if (offset >= 0xF14000 && offset < 0xF14003)
 775         {
 776                 joystick_word_write(offset, data);
 777                 eeprom_word_write(offset, data);
 778                 return;
 779         }
 780         else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
 781         {
 782                 eeprom_word_write(offset, data);
 783                 return;
 784         }
 785
 786 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
 787         if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
 788                 return;
 789
 790         jerry_ram_8[(offset+0) & 0xFFFF] = (data >> 8) & 0xFF;
 791         jerry_ram_8[(offset+1) & 0xFFFF] = data & 0xFF;
 792 }