4 // Originally by David Raingeard
5 // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS)
6 // Cleanups/rewrites/fixes by James L. Hammons
8 // ------------------------------------------------------------
9 // JERRY REGISTERS (Mapped by Aaron Giles)
10 // ------------------------------------------------------------
11 // F10000-F13FFF R/W xxxxxxxx xxxxxxxx Jerry
12 // F10000 W xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
13 // F10002 W xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
14 // F10004 W xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
15 // F10008 W xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
16 // F10010 W ------xx xxxxxxxx CLK1 - processor clock divider
17 // F10012 W ------xx xxxxxxxx CLK2 - video clock divider
18 // F10014 W -------- --xxxxxx CLK3 - chroma clock divider
19 // F10020 R/W ---xxxxx ---xxxxx JINTCTRL - interrupt control register
20 // W ---x---- -------- (J_SYNCLR - clear synchronous serial intf ints)
21 // W ----x--- -------- (J_ASYNCLR - clear asynchronous serial intf ints)
22 // W -----x-- -------- (J_TIM2CLR - clear timer 2 [tempo] interrupts)
23 // W ------x- -------- (J_TIM1CLR - clear timer 1 [sample] interrupts)
24 // W -------x -------- (J_EXTCLR - clear external interrupts)
25 // R/W -------- ---x---- (J_SYNENA - enable synchronous serial intf ints)
26 // R/W -------- ----x--- (J_ASYNENA - enable asynchronous serial intf ints)
27 // R/W -------- -----x-- (J_TIM2ENA - enable timer 2 [tempo] interrupts)
28 // R/W -------- ------x- (J_TIM1ENA - enable timer 1 [sample] interrupts)
29 // R/W -------- -------x (J_EXTENA - enable external interrupts)
30 // F10030 R/W -------- xxxxxxxx ASIDATA - asynchronous serial data
31 // F10032 W -x------ -xxxxxxx ASICTRL - asynchronous serial control
32 // W -x------ -------- (TXBRK - transmit break)
33 // W -------- -x------ (CLRERR - clear error)
34 // W -------- --x----- (RINTEN - enable receiver interrupts)
35 // W -------- ---x---- (TINTEN - enable transmitter interrupts)
36 // W -------- ----x--- (RXIPOL - receiver input polarity)
37 // W -------- -----x-- (TXOPOL - transmitter output polarity)
38 // W -------- ------x- (PAREN - parity enable)
39 // W -------- -------x (ODD - odd parity select)
40 // F10032 R xxx-xxxx x-xxxxxx ASISTAT - asynchronous serial status
41 // R x------- -------- (ERROR - OR of PE,FE,OE)
42 // R -x------ -------- (TXBRK - transmit break)
43 // R --x----- -------- (SERIN - serial input)
44 // R ----x--- -------- (OE - overrun error)
45 // R -----x-- -------- (FE - framing error)
46 // R ------x- -------- (PE - parity error)
47 // R -------x -------- (TBE - transmit buffer empty)
48 // R -------- x------- (RBF - receive buffer full)
49 // R -------- ---x---- (TINTEN - enable transmitter interrupts)
50 // R -------- ----x--- (RXIPOL - receiver input polarity)
51 // R -------- -----x-- (TXOPOL - transmitter output polarity)
52 // R -------- ------x- (PAREN - parity enable)
53 // R -------- -------x (ODD - odd parity)
54 // F10034 R/W xxxxxxxx xxxxxxxx ASICLK - asynchronous serial interface clock
55 // F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
56 // F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
57 // F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
58 // F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
59 // ------------------------------------------------------------
60 // F14000-F17FFF R/W xxxxxxxx xxxxxxxx Joysticks and GPIO0-5
61 // F14000 R xxxxxxxx xxxxxxxx JOYSTICK - read joystick state
62 // F14000 W x------- xxxxxxxx JOYSTICK - latch joystick output
63 // W x------- -------- (enable joystick outputs)
64 // W -------- xxxxxxxx (joystick output data)
65 // F14002 R xxxxxxxx xxxxxxxx JOYBUTS - button register
66 // F14800-F14FFF R/W xxxxxxxx xxxxxxxx GPI00 - reserved (CD-ROM?)
67 // F15000-F15FFF R/W xxxxxxxx xxxxxxxx GPI01 - reserved
68 // F16000-F16FFF R/W xxxxxxxx xxxxxxxx GPI02 - reserved
69 // F17000-F177FF R/W xxxxxxxx xxxxxxxx GPI03 - reserved
70 // F17800-F17BFF R/W xxxxxxxx xxxxxxxx GPI04 - reserved
71 // F17C00-F17FFF R/W xxxxxxxx xxxxxxxx GPI05 - reserved
72 // ------------------------------------------------------------
73 // F18000-F1FFFF R/W xxxxxxxx xxxxxxxx Jerry DSP
74 // F1A100 R/W xxxxxxxx xxxxxxxx D_FLAGS - DSP flags register
75 // R/W x------- -------- (DMAEN - DMA enable)
76 // R/W -x------ -------- (REGPAGE - register page)
77 // W --x----- -------- (D_EXT0CLR - clear external interrupt 0)
78 // W ---x---- -------- (D_TIM2CLR - clear timer 2 interrupt)
79 // W ----x--- -------- (D_TIM1CLR - clear timer 1 interrupt)
80 // W -----x-- -------- (D_I2SCLR - clear I2S interrupt)
81 // W ------x- -------- (D_CPUCLR - clear CPU interrupt)
82 // R/W -------x -------- (D_EXT0ENA - enable external interrupt 0)
83 // R/W -------- x------- (D_TIM2ENA - enable timer 2 interrupt)
84 // R/W -------- -x------ (D_TIM1ENA - enable timer 1 interrupt)
85 // R/W -------- --x----- (D_I2SENA - enable I2S interrupt)
86 // R/W -------- ---x---- (D_CPUENA - enable CPU interrupt)
87 // R/W -------- ----x--- (IMASK - interrupt mask)
88 // R/W -------- -----x-- (NEGA_FLAG - ALU negative)
89 // R/W -------- ------x- (CARRY_FLAG - ALU carry)
90 // R/W -------- -------x (ZERO_FLAG - ALU zero)
91 // F1A102 R/W -------- ------xx D_FLAGS - upper DSP flags
92 // R/W -------- ------x- (D_EXT1ENA - enable external interrupt 1)
93 // R/W -------- -------x (D_EXT1CLR - clear external interrupt 1)
94 // F1A104 W -------- ----xxxx D_MTXC - matrix control register
95 // W -------- ----x--- (MATCOL - column/row major)
96 // W -------- -----xxx (MATRIX3-15 - matrix width)
97 // F1A108 W ----xxxx xxxxxx-- D_MTXA - matrix address register
98 // F1A10C W -------- -----x-x D_END - data organization register
99 // W -------- -----x-- (BIG_INST - big endian instruction fetch)
100 // W -------- -------x (BIG_IO - big endian I/O)
101 // F1A110 R/W xxxxxxxx xxxxxxxx D_PC - DSP program counter
102 // F1A114 R/W xxxxxxxx xx-xxxxx D_CTRL - DSP control/status register
103 // R xxxx---- -------- (VERSION - DSP version code)
104 // R/W ----x--- -------- (BUS_HOG - hog the bus!)
105 // R/W -----x-- -------- (D_EXT0LAT - external interrupt 0 latch)
106 // R/W ------x- -------- (D_TIM2LAT - timer 2 interrupt latch)
107 // R/W -------x -------- (D_TIM1LAT - timer 1 interrupt latch)
108 // R/W -------- x------- (D_I2SLAT - I2S interrupt latch)
109 // R/W -------- -x------ (D_CPULAT - CPU interrupt latch)
110 // R/W -------- ---x---- (SINGLE_GO - single step one instruction)
111 // R/W -------- ----x--- (SINGLE_STEP - single step mode)
112 // R/W -------- -----x-- (FORCEINT0 - cause interrupt 0 on GPU)
113 // R/W -------- ------x- (CPUINT - send GPU interrupt to CPU)
114 // R/W -------- -------x (DSPGO - enable DSP execution)
115 // F1A116 R/W -------- -------x D_CTRL - upper DSP control/status register
116 // R/W -------- -------x (D_EXT1LAT - external interrupt 1 latch)
117 // F1A118-F1A11B W xxxxxxxx xxxxxxxx D_MOD - modulo instruction mask
118 // F1A11C-F1A11F R xxxxxxxx xxxxxxxx D_REMAIN - divide unit remainder
119 // F1A11C W -------- -------x D_DIVCTRL - divide unit control
120 // W -------- -------x (DIV_OFFSET - 1=16.16 divide, 0=32-bit divide)
121 // F1A120-F1A123 R xxxxxxxx xxxxxxxx D_MACHI - multiply & accumulate high bits
122 // F1A148 W xxxxxxxx xxxxxxxx R_DAC - right transmit data
123 // F1A14C W xxxxxxxx xxxxxxxx L_DAC - left transmit data
124 // F1A150 W -------- xxxxxxxx SCLK - serial clock frequency
125 // F1A150 R -------- ------xx SSTAT
126 // R -------- ------x- (left - no description)
127 // R -------- -------x (WS - word strobe status)
128 // F1A154 W -------- --xxxx-x SMODE - serial mode
129 // W -------- --x----- (EVERYWORD - interrupt on MSB of every word)
130 // W -------- ---x---- (FALLING - interrupt on falling edge)
131 // W -------- ----x--- (RISING - interrupt of rising edge)
132 // W -------- -----x-- (WSEN - enable word strobes)
133 // W -------- -------x (INTERNAL - enables serial clock)
134 // ------------------------------------------------------------
135 // F1B000-F1CFFF R/W xxxxxxxx xxxxxxxx Local DSP RAM
136 // ------------------------------------------------------------
137 // F1D000 R xxxxxxxx xxxxxxxx ROM_TRI - triangle wave
138 // F1D200 R xxxxxxxx xxxxxxxx ROM_SINE - full sine wave
139 // F1D400 R xxxxxxxx xxxxxxxx ROM_AMSINE - amplitude modulated sine wave
140 // F1D600 R xxxxxxxx xxxxxxxx ROM_12W - sine wave and second order harmonic
141 // F1D800 R xxxxxxxx xxxxxxxx ROM_CHIRP16 - chirp
142 // F1DA00 R xxxxxxxx xxxxxxxx ROM_NTRI - traingle wave with noise
143 // F1DC00 R xxxxxxxx xxxxxxxx ROM_DELTA - spike
144 // F1DE00 R xxxxxxxx xxxxxxxx ROM_NOISE - white noise
145 // ------------------------------------------------------------
149 #include "wavetable.h"
153 //Note that 44100 Hz requires samples every 22.675737 usec.
154 #define NEW_TIMER_SYSTEM
155 //#define JERRY_DEBUG
157 /*static*/ uint8 * jerry_ram_8;
159 //#define JERRY_CONFIG 0x4002 // ??? What's this ???
161 uint8 analog_x, analog_y;
163 static uint32 JERRYPIT1Prescaler;
164 static uint32 JERRYPIT1Divider;
165 static uint32 JERRYPIT2Prescaler;
166 static uint32 JERRYPIT2Divider;
167 static int32 jerry_timer_1_counter;
168 static int32 jerry_timer_2_counter;
170 static uint32 jerry_i2s_interrupt_divide = 8;
171 static int32 jerry_i2s_interrupt_timer = -1;
172 uint32 jerryI2SCycles;
173 uint32 jerryIntPending;
175 // Private function prototypes
177 void JERRYResetPIT1(void);
178 void JERRYResetPIT2(void);
179 void JERRYResetI2S(void);
181 void JERRYPIT1Callback(void);
182 void JERRYPIT2Callback(void);
183 void JERRYI2SCallback(void);
185 //This approach is probably wrong, since the timer is continuously counting down, though
186 //it might only be a problem if the # of interrupts generated is greater than 1--the M68K's
187 //timeslice should be running during that phase... (The DSP needs to be aware of this!)
188 void jerry_i2s_exec(uint32 cycles)
190 #ifndef NEW_TIMER_SYSTEM
191 extern uint16 serialMode; // From DAC.CPP
192 if (serialMode & 0x01) // INTERNAL flag (JERRY is master)
195 // Why is it called this? Instead of SCLK? Shouldn't this be read from DAC.CPP???
196 //Yes, it should. !!! FIX !!!
197 jerry_i2s_interrupt_divide &= 0xFF;
199 if (jerry_i2s_interrupt_timer == -1)
201 // We don't have to divide the RISC clock rate by this--the reason is a bit
202 // convoluted. Will put explanation here later...
203 // What's needed here is to find the ratio of the frequency to the number of clock cycles
204 // in one second. For example, if the sample rate is 44100, we divide the clock rate by
205 // this: 26590906 / 44100 = 602 cycles.
206 // Which means, every 602 cycles that go by we have to generate an interrupt.
207 jerryI2SCycles = 32 * (2 * (jerry_i2s_interrupt_divide + 1));
210 jerry_i2s_interrupt_timer -= cycles;
211 if (jerry_i2s_interrupt_timer <= 0)
213 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!!
214 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
215 jerry_i2s_interrupt_timer += jerryI2SCycles;
217 if (jerry_i2s_interrupt_timer < 0)
218 WriteLog("JERRY: Missed generating an interrupt (missed %u)!\n", (-jerry_i2s_interrupt_timer / jerryI2SCycles) + 1);
222 else // JERRY is slave to external word clock
224 // This is just a temporary kludge to see if the CD bus mastering works
225 // I.e., this is totally faked...!
226 // The whole interrupt system is pretty much borked and is need of an overhaul.
227 // What we need is a way of handling these interrupts when they happen instead of
228 // scanline boundaries the way it is now.
229 jerry_i2s_interrupt_timer -= cycles;
230 if (jerry_i2s_interrupt_timer <= 0)
232 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!! [DONE]
233 if (ButchIsReadyToSend())//Not sure this is right spot to check...
235 // return GetWordFromButchSSI(offset, who);
236 SetSSIWordsXmittedFromButch();
237 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
239 jerry_i2s_interrupt_timer += 602;
243 RemoveCallback(JERRYI2SCallback);
248 //NOTE: This is only used by the old execution core. Safe to nuke once it's stable.
249 void JERRYExecPIT(uint32 cycles)
251 //This is wrong too: Counters are *always* spinning! !!! FIX !!! [DONE]
252 // if (jerry_timer_1_counter)
253 jerry_timer_1_counter -= cycles;
255 if (jerry_timer_1_counter <= 0)
257 //Also, it can generate a CPU interrupt as well... !!! FIX !!! or does it? Maybe it goes Timer->GPU->CPU?
258 DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE); // This does the 'IRQ enabled' checking...
260 jerry_timer_1_counter += (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
263 //This is wrong too: Counters are *always* spinning! !!! FIX !!! [DONE]
264 // if (jerry_timer_2_counter)
265 jerry_timer_2_counter -= cycles;
267 if (jerry_timer_2_counter <= 0)
269 //Also, it can generate a CPU interrupt as well... !!! FIX !!! or does it? Maybe it goes Timer->GPU->CPU?
270 DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE); // This does the 'IRQ enabled' checking...
272 jerry_timer_2_counter += (JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1);
276 void JERRYResetI2S(void)
278 //WriteLog("i2s: reseting\n");
279 //This is really SCLK... !!! FIX !!!
280 jerry_i2s_interrupt_divide = 8;
281 jerry_i2s_interrupt_timer = -1;
284 void JERRYResetPIT1(void)
286 #ifndef NEW_TIMER_SYSTEM
287 /* if (!JERRYPIT1Prescaler || !JERRYPIT1Divider)
288 jerry_timer_1_counter = 0;
290 //Small problem with this approach: Overflow if both are = $FFFF. !!! FIX !!!
291 jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
293 // if (jerry_timer_1_counter)
294 // WriteLog("jerry: reseting timer 1 to 0x%.8x (%i)\n",jerry_timer_1_counter,jerry_timer_1_counter);
297 RemoveCallback(JERRYPIT1Callback);
299 if (JERRYPIT1Prescaler | JERRYPIT1Divider)
301 double usecs = (float)(JERRYPIT1Prescaler + 1) * (float)(JERRYPIT1Divider + 1) * RISC_CYCLE_IN_USEC;
302 SetCallbackTime(JERRYPIT1Callback, usecs);
307 void JERRYResetPIT2(void)
309 #ifndef NEW_TIMER_SYSTEM
310 /* if (!JERRYPIT2Prescaler || !JERRYPIT2Divider)
312 jerry_timer_2_counter = 0;
316 jerry_timer_2_counter = (JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1);
318 // if (jerry_timer_2_counter)
319 // WriteLog("jerry: reseting timer 2 to 0x%.8x (%i)\n",jerry_timer_2_counter,jerry_timer_2_counter);
322 RemoveCallback(JERRYPIT2Callback);
324 if (JERRYPIT1Prescaler | JERRYPIT1Divider)
326 double usecs = (float)(JERRYPIT2Prescaler + 1) * (float)(JERRYPIT2Divider + 1) * RISC_CYCLE_IN_USEC;
327 SetCallbackTime(JERRYPIT2Callback, usecs);
332 void JERRYPIT1Callback(void)
334 DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE); // This does the 'IRQ enabled' checking...
338 void JERRYPIT2Callback(void)
340 DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE); // This does the 'IRQ enabled' checking...
344 void JERRYI2SCallback(void)
346 // Why is it called this? Instead of SCLK? Shouldn't this be read from DAC.CPP???
347 //Yes, it should. !!! FIX !!!
348 jerry_i2s_interrupt_divide &= 0xFF;
349 // We don't have to divide the RISC clock rate by this--the reason is a bit
350 // convoluted. Will put explanation here later...
351 // What's needed here is to find the ratio of the frequency to the number of clock cycles
352 // in one second. For example, if the sample rate is 44100, we divide the clock rate by
353 // this: 26590906 / 44100 = 602 cycles.
354 // Which means, every 602 cycles that go by we have to generate an interrupt.
355 jerryI2SCycles = 32 * (2 * (jerry_i2s_interrupt_divide + 1));
357 //This should be in this file with an extern reference in the header file so that
358 //DAC.CPP can see it... !!! FIX !!!
359 extern uint16 serialMode; // From DAC.CPP
361 if (serialMode & 0x01) // INTERNAL flag (JERRY is master)
363 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE); // This does the 'IRQ enabled' checking...
364 double usecs = (float)jerryI2SCycles * RISC_CYCLE_IN_USEC;
365 SetCallbackTime(JERRYI2SCallback, usecs);
367 else // JERRY is slave to external word clock
369 //Note that 44100 Hz requires samples every 22.675737 usec.
370 //When JERRY is slave to the word clock, we need to do interrupts either at 44.1K
371 //sample rate or at a 88.2K sample rate (11.332... usec).
372 /* // This is just a temporary kludge to see if the CD bus mastering works
373 // I.e., this is totally faked...!
374 // The whole interrupt system is pretty much borked and is need of an overhaul.
375 // What we need is a way of handling these interrupts when they happen instead of
376 // scanline boundaries the way it is now.
377 jerry_i2s_interrupt_timer -= cycles;
378 if (jerry_i2s_interrupt_timer <= 0)
380 //This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!! [DONE]
381 if (ButchIsReadyToSend())//Not sure this is right spot to check...
383 // return GetWordFromButchSSI(offset, who);
384 SetSSIWordsXmittedFromButch();
385 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
387 jerry_i2s_interrupt_timer += 602;
393 void jerry_init(void)
399 //This should be handled with the cart initialization...
401 memory_malloc_secure((void **)&jerry_ram_8, 0x10000, "JERRY RAM/ROM");
402 memcpy(&jerry_ram_8[0xD000], wave_table, 0x1000);
404 JERRYPIT1Prescaler = 0xFFFF;
405 JERRYPIT2Prescaler = 0xFFFF;
406 JERRYPIT1Divider = 0xFFFF;
407 JERRYPIT2Divider = 0xFFFF;
410 void jerry_reset(void)
419 memset(jerry_ram_8, 0x00, 0xD000); // Don't clear out the Wavetable ROM...!
420 JERRYPIT1Prescaler = 0xFFFF;
421 JERRYPIT2Prescaler = 0xFFFF;
422 JERRYPIT1Divider = 0xFFFF;
423 JERRYPIT2Divider = 0xFFFF;
424 jerry_timer_1_counter = 0;
425 jerry_timer_2_counter = 0;
428 void jerry_done(void)
430 WriteLog("JERRY: M68K Interrupt control ($F10020) = %04X\n", GET16(jerry_ram_8, 0x20));
431 memory_free(jerry_ram_8);
439 bool JERRYIRQEnabled(int irq)
441 // Read the word @ $F10020
442 return jerry_ram_8[0x21] & (1 << irq);
445 void JERRYSetPendingIRQ(int irq)
447 // This is the shadow of INT (it's a split RO/WO register)
448 jerryIntPending |= (1 << irq);
452 // JERRY byte access (read)
454 uint8 JERRYReadByte(uint32 offset, uint32 who/*=UNKNOWN*/)
457 WriteLog("JERRY: Reading byte at %06X\n", offset);
459 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
460 return DSPReadByte(offset, who);
461 else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
462 return DSPReadByte(offset, who);
463 // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
464 else if (offset >= 0xF1A148 && offset <= 0xF1A153)
465 return DACReadByte(offset, who);
466 // F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
467 // F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
468 // F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
469 // F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
471 // else if (offset >= 0xF10000 && offset <= 0xF10007)
472 //This is still wrong. What needs to be returned here are the values being counted down
473 //in the jerry_timer_n_counter variables... !!! FIX !!! [DONE]
475 //This is probably the problem with the new timer code... This is invalid
476 //under the new system... !!! FIX !!!
477 else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
479 #ifndef NEW_TIMER_SYSTEM
480 // jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
481 uint32 counter1Hi = (jerry_timer_1_counter / (JERRYPIT1Divider + 1)) - 1;
482 uint32 counter1Lo = (jerry_timer_1_counter % (JERRYPIT1Divider + 1)) - 1;
483 uint32 counter2Hi = (jerry_timer_2_counter / (JERRYPIT2Divider + 1)) - 1;
484 uint32 counter2Lo = (jerry_timer_2_counter % (JERRYPIT2Divider + 1)) - 1;
486 switch(offset & 0x0F)
489 // return JERRYPIT1Prescaler >> 8;
490 return counter1Hi >> 8;
492 // return JERRYPIT1Prescaler & 0xFF;
493 return counter1Hi & 0xFF;
495 // return JERRYPIT1Divider >> 8;
496 return counter1Lo >> 8;
498 // return JERRYPIT1Divider & 0xFF;
499 return counter1Lo & 0xFF;
501 // return JERRYPIT2Prescaler >> 8;
502 return counter2Hi >> 8;
504 // return JERRYPIT2Prescaler & 0xFF;
505 return counter2Hi & 0xFF;
507 // return JERRYPIT2Divider >> 8;
508 return counter2Lo >> 8;
510 // return JERRYPIT2Divider & 0xFF;
511 return counter2Lo & 0xFF;
514 WriteLog("JERRY: Unhandled timer read (BYTE) at %08X...\n", offset);
517 // else if (offset >= 0xF10010 && offset <= 0xF10015)
518 // return clock_byte_read(offset);
519 // else if (offset >= 0xF17C00 && offset <= 0xF17C01)
520 // return anajoy_byte_read(offset);
521 else if (offset >= 0xF14000 && offset <= 0xF14003)
522 return joystick_byte_read(offset) | eeprom_byte_read(offset);
523 else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
524 return eeprom_byte_read(offset);
526 return jerry_ram_8[offset & 0xFFFF];
530 // JERRY word access (read)
532 uint16 JERRYReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
535 WriteLog("JERRY: Reading word at %06X\n", offset);
538 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
539 return DSPReadWord(offset, who);
540 else if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE + 0x1FFF)
541 return DSPReadWord(offset, who);
542 // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
543 else if (offset >= 0xF1A148 && offset <= 0xF1A153)
544 return DACReadWord(offset, who);
545 // F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
546 // F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
547 // F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
548 // F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
550 // else if ((offset >= 0xF10000) && (offset <= 0xF10007))
551 //This is still wrong. What needs to be returned here are the values being counted down
552 //in the jerry_timer_n_counter variables... !!! FIX !!! [DONE]
553 else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
555 #ifndef NEW_TIMER_SYSTEM
556 // jerry_timer_1_counter = (JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1);
557 uint32 counter1Hi = (jerry_timer_1_counter / (JERRYPIT1Divider + 1)) - 1;
558 uint32 counter1Lo = (jerry_timer_1_counter % (JERRYPIT1Divider + 1)) - 1;
559 uint32 counter2Hi = (jerry_timer_2_counter / (JERRYPIT2Divider + 1)) - 1;
560 uint32 counter2Lo = (jerry_timer_2_counter % (JERRYPIT2Divider + 1)) - 1;
562 switch(offset & 0x0F)
565 // return JERRYPIT1Prescaler;
568 // return JERRYPIT1Divider;
571 // return JERRYPIT2Prescaler;
574 // return JERRYPIT2Divider;
577 // Unaligned word reads???
579 WriteLog("JERRY: Unhandled timer read (WORD) at %08X...\n", offset);
582 // else if ((offset >= 0xF10010) && (offset <= 0xF10015))
583 // return clock_word_read(offset);
584 else if (offset == 0xF10020)
585 return jerryIntPending;
586 // else if ((offset >= 0xF17C00) && (offset <= 0xF17C01))
587 // return anajoy_word_read(offset);
588 else if (offset == 0xF14000)
589 return (joystick_word_read(offset) & 0xFFFE) | eeprom_word_read(offset);
590 else if ((offset >= 0xF14002) && (offset < 0xF14003))
591 return joystick_word_read(offset);
592 else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
593 return eeprom_word_read(offset);
595 /*if (offset >= 0xF1D000)
596 WriteLog("JERRY: Reading word at %08X [%04X]...\n", offset, ((uint16)jerry_ram_8[(offset+0)&0xFFFF] << 8) | jerry_ram_8[(offset+1)&0xFFFF]);//*/
598 offset &= 0xFFFF; // Prevent crashing...!
599 return ((uint16)jerry_ram_8[offset+0] << 8) | jerry_ram_8[offset+1];
603 // JERRY byte access (write)
605 void JERRYWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
608 WriteLog("jerry: writing byte %.2x at 0x%.6x\n",data,offset);
610 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
612 DSPWriteByte(offset, data, who);
615 else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
617 DSPWriteByte(offset, data, who);
620 // SCLK ($F1A150--8 bits wide)
621 //NOTE: This should be taken care of in DAC...
622 else if ((offset >= 0xF1A152) && (offset <= 0xF1A153))
624 // WriteLog("JERRY: Writing %02X to SCLK...\n", data);
625 if ((offset & 0x03) == 2)
626 jerry_i2s_interrupt_divide = (jerry_i2s_interrupt_divide & 0x00FF) | ((uint32)data << 8);
628 jerry_i2s_interrupt_divide = (jerry_i2s_interrupt_divide & 0xFF00) | (uint32)data;
630 jerry_i2s_interrupt_timer = -1;
634 // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
635 else if (offset >= 0xF1A148 && offset <= 0xF1A157)
637 DACWriteByte(offset, data, who);
640 else if (offset >= 0xF10000 && offset <= 0xF10007)
642 #ifndef NEW_TIMER_SYSTEM
643 switch (offset & 0x07)
646 JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0x00FF) | (data << 8);
650 JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0xFF00) | data;
654 JERRYPIT1Divider = (JERRYPIT1Divider & 0x00FF) | (data << 8);
658 JERRYPIT1Divider = (JERRYPIT1Divider & 0xFF00) | data;
662 JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0x00FF) | (data << 8);
666 JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0xFF00) | data;
670 JERRYPIT2Divider = (JERRYPIT2Divider & 0x00FF) | (data << 8);
674 JERRYPIT2Divider = (JERRYPIT2Divider & 0xFF00) | data;
678 WriteLog("JERRY: Unhandled timer write (BYTE) at %08X...\n", offset);
682 /* else if ((offset >= 0xF10010) && (offset <= 0xF10015))
684 clock_byte_write(offset, data);
687 // JERRY -> 68K interrupt enables/latches (need to be handled!)
688 else if (offset >= 0xF10020 && offset <= 0xF10023)
690 WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%02X to $%08X!\n", data, offset);
692 /* else if ((offset >= 0xF17C00) && (offset <= 0xF17C01))
694 anajoy_byte_write(offset, data);
697 else if ((offset >= 0xF14000) && (offset <= 0xF14003))
699 joystick_byte_write(offset, data);
700 eeprom_byte_write(offset, data);
703 else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
705 eeprom_byte_write(offset, data);
709 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
710 if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
713 jerry_ram_8[offset & 0xFFFF] = data;
717 // JERRY word access (write)
719 void JERRYWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
722 WriteLog( "JERRY: Writing word %04X at %06X\n", data, offset);
725 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
727 DSPWriteWord(offset, data, who);
730 else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
732 DSPWriteWord(offset, data, who);
735 //NOTE: This should be taken care of in DAC...
736 else if (offset == 0xF1A152) // Bottom half of SCLK ($F1A150)
738 WriteLog("JERRY: Writing %04X to SCLK (by %s)...\n", data, whoName[who]);
739 //This should *only* be enabled when SMODE has its INTERNAL bit set! !!! FIX !!!
740 jerry_i2s_interrupt_divide = (uint8)data;
741 jerry_i2s_interrupt_timer = -1;
744 DACWriteWord(offset, data, who);
747 // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
748 else if (offset >= 0xF1A148 && offset <= 0xF1A156)
750 DACWriteWord(offset, data, who);
753 else if (offset >= 0xF10000 && offset <= 0xF10007)
755 //#ifndef NEW_TIMER_SYSTEM
757 switch(offset & 0x07)
760 JERRYPIT1Prescaler = data;
764 JERRYPIT1Divider = data;
768 JERRYPIT2Prescaler = data;
772 JERRYPIT2Divider = data;
775 // Need to handle (unaligned) cases???
777 WriteLog("JERRY: Unhandled timer write %04X (WORD) at %08X by %s...\n", data, offset, whoName[who]);
781 /* else if (offset >= 0xF10010 && offset < 0xF10016)
783 clock_word_write(offset, data);
786 // JERRY -> 68K interrupt enables/latches (need to be handled!)
787 else if (offset >= 0xF10020 && offset <= 0xF10022)
789 WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%04X to $%08X!\n", data, offset);
791 /* else if (offset >= 0xF17C00 && offset < 0xF17C02)
793 //I think this was removed from the Jaguar. If so, then we don't need this...!
794 anajoy_word_write(offset, data);
797 else if (offset >= 0xF14000 && offset < 0xF14003)
799 joystick_word_write(offset, data);
800 eeprom_word_write(offset, data);
803 else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
805 eeprom_word_write(offset, data);
809 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
810 if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
813 jerry_ram_8[(offset+0) & 0xFFFF] = (data >> 8) & 0xFF;
814 jerry_ram_8[(offset+1) & 0xFFFF] = data & 0xFF;