10 #define DSP_CONTROL_RAM_BASE 0x00F1A100
11 #define DSP_WORK_RAM_BASE 0x00F1B000
17 void DSPUpdateRegisterBanks(void);
18 void DSPHandleIRQs(void);
19 void DSPSetIRQLine(int irqline, int state);
20 uint8 DSPReadByte(uint32 offset, uint32 who = UNKNOWN);
21 uint16 DSPReadWord(uint32 offset, uint32 who = UNKNOWN);
22 uint32 DSPReadLong(uint32 offset, uint32 who = UNKNOWN);
23 void DSPWriteByte(uint32 offset, uint8 data, uint32 who = UNKNOWN);
24 void DSPWriteWord(uint32 offset, uint16 data, uint32 who = UNKNOWN);
25 void DSPWriteLong(uint32 offset, uint32 data, uint32 who = UNKNOWN);
26 void dsp_releaseTimeslice(void);
28 void DSPExecP(int32 cycles);
29 void DSPExecP2(int32 cycles);
30 //void DSPExecP3(int32 cycles);
31 void DSPExecComp(int32 cycles);
33 // DSP interrupt numbers (in $F1A100, bits 4-8 & 16)
35 enum { DSPIRQ_CPU = 0, DSPIRQ_SSI, DSPIRQ_TIMER0, DSPIRQ_TIMER1, DSPIRQ_EXT0, DSPIRQ_EXT1 };