11 #define GPU_CONTROL_RAM_BASE 0x00F02100
12 #define GPU_WORK_RAM_BASE 0x00F03000
16 void GPUExec(int32_t);
18 void GPUUpdateRegisterBanks(void);
19 void GPUHandleIRQs(void);
20 void GPUSetIRQLine(int irqline, int state);
22 uint8_t GPUReadByte(uint32_t offset, uint32_t who = UNKNOWN);
23 uint16_t GPUReadWord(uint32_t offset, uint32_t who = UNKNOWN);
24 uint32_t GPUReadLong(uint32_t offset, uint32_t who = UNKNOWN);
25 void GPUWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN);
26 void GPUWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN);
27 void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who = UNKNOWN);
29 uint32_t GPUGetPC(void);
30 void GPUReleaseTimeslice(void);
31 void GPUResetStats(void);
32 uint32_t GPUReadPC(void);
34 // GPU interrupt numbers (from $F00100, bits 4-8)
36 enum { GPUIRQ_CPU = 0, GPUIRQ_DSP, GPUIRQ_TIMER, GPUIRQ_OBJECT, GPUIRQ_BLITTER };
40 extern uint32_t gpu_reg_bank_0[], gpu_reg_bank_1[];