11 #define GPU_CONTROL_RAM_BASE 0x00F02100
12 #define GPU_WORK_RAM_BASE 0x00F03000
18 void gpu_update_register_banks(void);
19 void GPUHandleIRQs(void);
20 void GPUSetIRQLine(int irqline, int state);
22 uint8 GPUReadByte(uint32 offset, uint32 who = UNKNOWN);
23 uint16 GPUReadWord(uint32 offset, uint32 who = UNKNOWN);
24 uint32 GPUReadLong(uint32 offset, uint32 who = UNKNOWN);
25 void GPUWriteByte(uint32 offset, uint8 data, uint32 who = UNKNOWN);
26 void GPUWriteWord(uint32 offset, uint16 data, uint32 who = UNKNOWN);
27 void GPUWriteLong(uint32 offset, uint32 data, uint32 who = UNKNOWN);
29 uint32 gpu_get_pc(void);
30 void gpu_releaseTimeslice(void);
31 void gpu_reset_stats(void);
32 uint32 gpu_read_pc(void);
34 // GPU interrupt numbers (from $F00100, bits 4-8)
36 enum { GPUIRQ_CPU = 0, GPUIRQ_DSP, GPUIRQ_TIMER, GPUIRQ_OBJECT, GPUIRQ_BLITTER };