10 #define DSP_CONTROL_RAM_BASE 0x00F1A100
11 #define DSP_WORK_RAM_BASE 0x00F1B000
15 void DSPExec(int32_t);
17 void DSPUpdateRegisterBanks(void);
18 void DSPHandleIRQs(void);
19 void DSPSetIRQLine(int irqline, int state);
20 uint8_t DSPReadByte(uint32_t offset, uint32_t who = UNKNOWN);
21 uint16_t DSPReadWord(uint32_t offset, uint32_t who = UNKNOWN);
22 uint32_t DSPReadLong(uint32_t offset, uint32_t who = UNKNOWN);
23 void DSPWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN);
24 void DSPWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN);
25 void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who = UNKNOWN);
26 void DSPReleaseTimeslice(void);
27 bool DSPIsRunning(void);
29 void DSPExecP(int32_t cycles);
30 void DSPExecP2(int32_t cycles);
31 //void DSPExecP3(int32_t cycles);
32 void DSPExecComp(int32_t cycles);
37 extern uint32_t dsp_reg_bank_0[], dsp_reg_bank_1[];
39 // DSP interrupt numbers (in $F1A100, bits 4-8 & 16)
41 enum { DSPIRQ_CPU = 0, DSPIRQ_SSI, DSPIRQ_TIMER0, DSPIRQ_TIMER1, DSPIRQ_EXT0, DSPIRQ_EXT1 };