11 #define DSP_CONTROL_RAM_BASE 0x00F1A100
12 #define DSP_WORK_RAM_BASE 0x00F1B000
18 void DSPUpdateRegisterBanks(void);
19 void DSPHandleIRQs(void);
20 void DSPSetIRQLine(int irqline, int state);
21 uint8 DSPReadByte(uint32 offset, uint32 who = UNKNOWN);
22 uint16 DSPReadWord(uint32 offset, uint32 who = UNKNOWN);
23 uint32 DSPReadLong(uint32 offset, uint32 who = UNKNOWN);
24 void DSPWriteByte(uint32 offset, uint8 data, uint32 who = UNKNOWN);
25 void DSPWriteWord(uint32 offset, uint16 data, uint32 who = UNKNOWN);
26 void DSPWriteLong(uint32 offset, uint32 data, uint32 who = UNKNOWN);
27 void DSPReleaseTimeslice(void);
28 bool DSPIsRunning(void);
30 void DSPExecP(int32 cycles);
31 void DSPExecP2(int32 cycles);
32 //void DSPExecP3(int32 cycles);
33 void DSPExecComp(int32 cycles);
38 extern uint32 dsp_reg_bank_0[], dsp_reg_bank_1[];
40 // DSP interrupt numbers (in $F1A100, bits 4-8 & 16)
42 enum { DSPIRQ_CPU = 0, DSPIRQ_SSI, DSPIRQ_TIMER0, DSPIRQ_TIMER1, DSPIRQ_EXT0, DSPIRQ_EXT1 };