6 // I owe a debt of gratitude to Curt Vendel and to John Mathieson--to Curt
7 // for supplying the Oberon ASIC nets and to John for making them available
8 // to Curt. ;-) Without that excellent documentation which shows *exactly*
9 // what's going on inside the TOM chip, we'd all still be guessing as to how
10 // the wily blitter and other pieces of the Jaguar puzzle actually work.
16 // Various conditional compilation goodies...
18 //#define USE_ORIGINAL_BLITTER
19 //#define USE_MIDSUMMER_BLITTER
20 #define USE_MIDSUMMER_BLITTER_MKII
22 // External global variables
24 extern int jaguar_active_memory_dumps;
26 // Local global variables
28 int start_logging = 0;
29 uint8 blitter_working = 0;
31 // Blitter register RAM (most of it is hidden from the user)
33 static uint8 blitter_ram[0x100];
37 bool specialLog = false;
38 extern int effect_start;
39 extern int blit_start_log;
40 void BlitterMidsummer(uint32 cmd);
41 void BlitterMidsummer2(void);
43 #define REG(A) (((uint32)blitter_ram[(A)] << 24) | ((uint32)blitter_ram[(A)+1] << 16) \
44 | ((uint32)blitter_ram[(A)+2] << 8) | (uint32)blitter_ram[(A)+3])
45 #define WREG(A,D) (blitter_ram[(A)] = ((D)>>24)&0xFF, blitter_ram[(A)+1] = ((D)>>16)&0xFF, \
46 blitter_ram[(A)+2] = ((D)>>8)&0xFF, blitter_ram[(A)+3] = (D)&0xFF)
48 // Blitter registers (offsets from F02200)
50 #define A1_BASE ((UINT32)0x00)
51 #define A1_FLAGS ((UINT32)0x04)
52 #define A1_CLIP ((UINT32)0x08) // Height and width values for clipping
53 #define A1_PIXEL ((UINT32)0x0C) // Integer part of the pixel (Y.i and X.i)
54 #define A1_STEP ((UINT32)0x10) // Integer part of the step
55 #define A1_FSTEP ((UINT32)0x14) // Fractional part of the step
56 #define A1_FPIXEL ((UINT32)0x18) // Fractional part of the pixel (Y.f and X.f)
57 #define A1_INC ((UINT32)0x1C) // Integer part of the increment
58 #define A1_FINC ((UINT32)0x20) // Fractional part of the increment
59 #define A2_BASE ((UINT32)0x24)
60 #define A2_FLAGS ((UINT32)0x28)
61 #define A2_MASK ((UINT32)0x2C) // Modulo values for x and y (M.y and M.x)
62 #define A2_PIXEL ((UINT32)0x30) // Integer part of the pixel (no fractional part for A2)
63 #define A2_STEP ((UINT32)0x34) // Integer part of the step (no fractional part for A2)
64 #define COMMAND ((UINT32)0x38)
65 #define PIXLINECOUNTER ((UINT32)0x3C) // Inner & outer loop values
66 #define SRCDATA ((UINT32)0x40)
67 #define DSTDATA ((UINT32)0x48)
68 #define DSTZ ((UINT32)0x50)
69 #define SRCZINT ((UINT32)0x58)
70 #define SRCZFRAC ((UINT32)0x60)
71 #define PATTERNDATA ((UINT32)0x68)
72 #define INTENSITYINC ((UINT32)0x70)
73 #define ZINC ((UINT32)0x74)
74 #define COLLISIONCTRL ((UINT32)0x78)
75 #define PHRASEINT0 ((UINT32)0x7C)
76 #define PHRASEINT1 ((UINT32)0x80)
77 #define PHRASEINT2 ((UINT32)0x84)
78 #define PHRASEINT3 ((UINT32)0x88)
79 #define PHRASEZ0 ((UINT32)0x8C)
80 #define PHRASEZ1 ((UINT32)0x90)
81 #define PHRASEZ2 ((UINT32)0x94)
82 #define PHRASEZ3 ((UINT32)0x98)
84 // Blitter command bits
86 #define SRCEN (cmd & 0x00000001)
87 #define SRCENZ (cmd & 0x00000002)
88 #define SRCENX (cmd & 0x00000004)
89 #define DSTEN (cmd & 0x00000008)
90 #define DSTENZ (cmd & 0x00000010)
91 #define DSTWRZ (cmd & 0x00000020)
92 #define CLIPA1 (cmd & 0x00000040)
94 #define UPDA1F (cmd & 0x00000100)
95 #define UPDA1 (cmd & 0x00000200)
96 #define UPDA2 (cmd & 0x00000400)
98 #define DSTA2 (cmd & 0x00000800)
100 #define Z_OP_INF (cmd & 0x00040000)
101 #define Z_OP_EQU (cmd & 0x00080000)
102 #define Z_OP_SUP (cmd & 0x00100000)
104 #define LFU_NAN (cmd & 0x00200000)
105 #define LFU_NA (cmd & 0x00400000)
106 #define LFU_AN (cmd & 0x00800000)
107 #define LFU_A (cmd & 0x01000000)
109 #define CMPDST (cmd & 0x02000000)
110 #define BCOMPEN (cmd & 0x04000000)
111 #define DCOMPEN (cmd & 0x08000000)
113 #define PATDSEL (cmd & 0x00010000)
114 #define ADDDSEL (cmd & 0x00020000)
115 #define TOPBEN (cmd & 0x00004000)
116 #define TOPNEN (cmd & 0x00008000)
117 #define BKGWREN (cmd & 0x10000000)
118 #define GOURD (cmd & 0x00001000)
119 #define GOURZ (cmd & 0x00002000)
120 #define SRCSHADE (cmd & 0x40000000)
128 #define XSIGNSUB_A1 (REG(A1_FLAGS)&0x080000)
129 #define XSIGNSUB_A2 (REG(A2_FLAGS)&0x080000)
131 #define YSIGNSUB_A1 (REG(A1_FLAGS)&0x100000)
132 #define YSIGNSUB_A2 (REG(A2_FLAGS)&0x100000)
134 #define YADD1_A1 (REG(A1_FLAGS)&0x040000)
135 #define YADD1_A2 (REG(A2_FLAGS)&0x040000)
137 /*******************************************************************************
138 ********************** STUFF CUT BELOW THIS LINE! ******************************
139 *******************************************************************************/
140 #ifdef USE_ORIGINAL_BLITTER // We're ditching this crap for now...
142 //Put 'em back, once we fix the problem!!! [KO]
144 #define PIXEL_SHIFT_1(a) (((~a##_x) >> 16) & 7)
145 #define PIXEL_OFFSET_1(a) (((((UINT32)a##_y >> 16) * a##_width / 8) + (((UINT32)a##_x >> 19) & ~7)) * (1 + a##_pitch) + (((UINT32)a##_x >> 19) & 7))
146 #define READ_PIXEL_1(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_1(a), BLITTER) >> PIXEL_SHIFT_1(a)) & 0x01)
147 //#define READ_PIXEL_1(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_1(a)) >> PIXEL_SHIFT_1(a)) & 0x01)
150 #define PIXEL_SHIFT_2(a) (((~a##_x) >> 15) & 6)
151 #define PIXEL_OFFSET_2(a) (((((UINT32)a##_y >> 16) * a##_width / 4) + (((UINT32)a##_x >> 18) & ~7)) * (1 + a##_pitch) + (((UINT32)a##_x >> 18) & 7))
152 #define READ_PIXEL_2(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_2(a), BLITTER) >> PIXEL_SHIFT_2(a)) & 0x03)
153 //#define READ_PIXEL_2(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_2(a)) >> PIXEL_SHIFT_2(a)) & 0x03)
156 #define PIXEL_SHIFT_4(a) (((~a##_x) >> 14) & 4)
157 #define PIXEL_OFFSET_4(a) (((((UINT32)a##_y >> 16) * (a##_width/2)) + (((UINT32)a##_x >> 17) & ~7)) * (1 + a##_pitch) + (((UINT32)a##_x >> 17) & 7))
158 #define READ_PIXEL_4(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_4(a), BLITTER) >> PIXEL_SHIFT_4(a)) & 0x0f)
159 //#define READ_PIXEL_4(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_4(a)) >> PIXEL_SHIFT_4(a)) & 0x0f)
162 #define PIXEL_OFFSET_8(a) (((((UINT32)a##_y >> 16) * a##_width) + (((UINT32)a##_x >> 16) & ~7)) * (1 + a##_pitch) + (((UINT32)a##_x >> 16) & 7))
163 #define READ_PIXEL_8(a) (JaguarReadByte(a##_addr+PIXEL_OFFSET_8(a), BLITTER))
164 //#define READ_PIXEL_8(a) (JaguarReadByte(a##_addr+PIXEL_OFFSET_8(a)))
167 #define PIXEL_OFFSET_16(a) (((((UINT32)a##_y >> 16) * a##_width) + (((UINT32)a##_x >> 16) & ~3)) * (1 + a##_pitch) + (((UINT32)a##_x >> 16) & 3))
168 #define READ_PIXEL_16(a) (JaguarReadWord(a##_addr+(PIXEL_OFFSET_16(a)<<1), BLITTER))
169 //#define READ_PIXEL_16(a) (JaguarReadWord(a##_addr+(PIXEL_OFFSET_16(a)<<1)))
172 #define PIXEL_OFFSET_32(a) (((((UINT32)a##_y >> 16) * a##_width) + (((UINT32)a##_x >> 16) & ~1)) * (1 + a##_pitch) + (((UINT32)a##_x >> 16) & 1))
173 #define READ_PIXEL_32(a) (JaguarReadLong(a##_addr+(PIXEL_OFFSET_32(a)<<2), BLITTER))
174 //#define READ_PIXEL_32(a) (JaguarReadLong(a##_addr+(PIXEL_OFFSET_32(a)<<2)))
177 #define READ_PIXEL(a,f) (\
178 (((f>>3)&0x07) == 0) ? (READ_PIXEL_1(a)) : \
179 (((f>>3)&0x07) == 1) ? (READ_PIXEL_2(a)) : \
180 (((f>>3)&0x07) == 2) ? (READ_PIXEL_4(a)) : \
181 (((f>>3)&0x07) == 3) ? (READ_PIXEL_8(a)) : \
182 (((f>>3)&0x07) == 4) ? (READ_PIXEL_16(a)) : \
183 (((f>>3)&0x07) == 5) ? (READ_PIXEL_32(a)) : 0)
185 // 16 bpp z data read
186 #define ZDATA_OFFSET_16(a) (PIXEL_OFFSET_16(a) + a##_zoffs * 4)
187 #define READ_ZDATA_16(a) (JaguarReadWord(a##_addr+(ZDATA_OFFSET_16(a)<<1), BLITTER))
188 //#define READ_ZDATA_16(a) (JaguarReadWord(a##_addr+(ZDATA_OFFSET_16(a)<<1)))
191 #define READ_ZDATA(a,f) (READ_ZDATA_16(a))
193 // 16 bpp z data write
194 #define WRITE_ZDATA_16(a,d) { JaguarWriteWord(a##_addr+(ZDATA_OFFSET_16(a)<<1), d, BLITTER); }
195 //#define WRITE_ZDATA_16(a,d) { JaguarWriteWord(a##_addr+(ZDATA_OFFSET_16(a)<<1), d); }
198 #define WRITE_ZDATA(a,f,d) WRITE_ZDATA_16(a,d);
201 #define READ_RDATA_1(r,a,p) ((p) ? ((REG(r+(((UINT32)a##_x >> 19) & 0x04))) >> (((UINT32)a##_x >> 16) & 0x1F)) & 0x0001 : (REG(r) & 0x0001))
204 #define READ_RDATA_2(r,a,p) ((p) ? ((REG(r+(((UINT32)a##_x >> 18) & 0x04))) >> (((UINT32)a##_x >> 15) & 0x3E)) & 0x0003 : (REG(r) & 0x0003))
207 #define READ_RDATA_4(r,a,p) ((p) ? ((REG(r+(((UINT32)a##_x >> 17) & 0x04))) >> (((UINT32)a##_x >> 14) & 0x28)) & 0x000F : (REG(r) & 0x000F))
210 #define READ_RDATA_8(r,a,p) ((p) ? ((REG(r+(((UINT32)a##_x >> 16) & 0x04))) >> (((UINT32)a##_x >> 13) & 0x18)) & 0x00FF : (REG(r) & 0x00FF))
212 // 16 bpp r data read
213 #define READ_RDATA_16(r,a,p) ((p) ? ((REG(r+(((UINT32)a##_x >> 15) & 0x04))) >> (((UINT32)a##_x >> 12) & 0x10)) & 0xFFFF : (REG(r) & 0xFFFF))
215 // 32 bpp r data read
216 #define READ_RDATA_32(r,a,p) ((p) ? REG(r+(((UINT32)a##_x >> 14) & 0x04)) : REG(r))
218 // register data read
219 #define READ_RDATA(r,a,f,p) (\
220 (((f>>3)&0x07) == 0) ? (READ_RDATA_1(r,a,p)) : \
221 (((f>>3)&0x07) == 1) ? (READ_RDATA_2(r,a,p)) : \
222 (((f>>3)&0x07) == 2) ? (READ_RDATA_4(r,a,p)) : \
223 (((f>>3)&0x07) == 3) ? (READ_RDATA_8(r,a,p)) : \
224 (((f>>3)&0x07) == 4) ? (READ_RDATA_16(r,a,p)) : \
225 (((f>>3)&0x07) == 5) ? (READ_RDATA_32(r,a,p)) : 0)
228 #define WRITE_PIXEL_1(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_1(a), (JaguarReadByte(a##_addr+PIXEL_OFFSET_1(a), BLITTER)&(~(0x01 << PIXEL_SHIFT_1(a))))|(d<<PIXEL_SHIFT_1(a)), BLITTER); }
229 //#define WRITE_PIXEL_1(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_1(a), (JaguarReadByte(a##_addr+PIXEL_OFFSET_1(a))&(~(0x01 << PIXEL_SHIFT_1(a))))|(d<<PIXEL_SHIFT_1(a))); }
232 #define WRITE_PIXEL_2(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_2(a), (JaguarReadByte(a##_addr+PIXEL_OFFSET_2(a), BLITTER)&(~(0x03 << PIXEL_SHIFT_2(a))))|(d<<PIXEL_SHIFT_2(a)), BLITTER); }
233 //#define WRITE_PIXEL_2(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_2(a), (JaguarReadByte(a##_addr+PIXEL_OFFSET_2(a))&(~(0x03 << PIXEL_SHIFT_2(a))))|(d<<PIXEL_SHIFT_2(a))); }
236 #define WRITE_PIXEL_4(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_4(a), (JaguarReadByte(a##_addr+PIXEL_OFFSET_4(a), BLITTER)&(~(0x0f << PIXEL_SHIFT_4(a))))|(d<<PIXEL_SHIFT_4(a)), BLITTER); }
237 //#define WRITE_PIXEL_4(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_4(a), (JaguarReadByte(a##_addr+PIXEL_OFFSET_4(a))&(~(0x0f << PIXEL_SHIFT_4(a))))|(d<<PIXEL_SHIFT_4(a))); }
240 #define WRITE_PIXEL_8(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_8(a), d, BLITTER); }
241 //#define WRITE_PIXEL_8(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_8(a), d); }
243 // 16 bpp pixel write
244 //#define WRITE_PIXEL_16(a,d) { JaguarWriteWord(a##_addr+(PIXEL_OFFSET_16(a)<<1),d); }
245 #define WRITE_PIXEL_16(a,d) { JaguarWriteWord(a##_addr+(PIXEL_OFFSET_16(a)<<1), d, BLITTER); if (specialLog) WriteLog("Pixel write address: %08X\n", a##_addr+(PIXEL_OFFSET_16(a)<<1)); }
246 //#define WRITE_PIXEL_16(a,d) { JaguarWriteWord(a##_addr+(PIXEL_OFFSET_16(a)<<1), d); if (specialLog) WriteLog("Pixel write address: %08X\n", a##_addr+(PIXEL_OFFSET_16(a)<<1)); }
248 // 32 bpp pixel write
249 #define WRITE_PIXEL_32(a,d) { JaguarWriteLong(a##_addr+(PIXEL_OFFSET_32(a)<<2), d, BLITTER); }
250 //#define WRITE_PIXEL_32(a,d) { JaguarWriteLong(a##_addr+(PIXEL_OFFSET_32(a)<<2), d); }
253 #define WRITE_PIXEL(a,f,d) {\
254 switch ((f>>3)&0x07) { \
255 case 0: WRITE_PIXEL_1(a,d); break; \
256 case 1: WRITE_PIXEL_2(a,d); break; \
257 case 2: WRITE_PIXEL_4(a,d); break; \
258 case 3: WRITE_PIXEL_8(a,d); break; \
259 case 4: WRITE_PIXEL_16(a,d); break; \
260 case 5: WRITE_PIXEL_32(a,d); break; \
263 // Width in Pixels of a Scanline
264 // This is a pretranslation of the value found in the A1 & A2 flags: It's really a floating point value
265 // of the form EEEEMM where MM is the mantissa with an implied "1." in front of it and the EEEE value is
266 // the exponent. Valid values for the exponent range from 0 to 11 (decimal). It's easiest to think of it
267 // as a floating point bit pattern being followed by a number of zeroes. So, e.g., 001101 translates to
268 // 1.01 (the "1." being implied) x (2 ^ 3) or 1010 -> 10 in base 10 (i.e., 1.01 with the decimal place
269 // being shifted to the right 3 places).
270 /*static uint32 blitter_scanline_width[48] =
272 0, 0, 0, 0, // Note: This would really translate to 1, 1, 1, 1
282 1024, 1280, 1536, 1792,
283 2048, 2560, 3072, 3584
286 //static uint8 * tom_ram_8;
287 //static uint8 * paletteRam;
297 static uint32 a1_addr;
298 static uint32 a2_addr;
299 static int32 a1_zoffs;
300 static int32 a2_zoffs;
301 static uint32 xadd_a1_control;
302 static uint32 xadd_a2_control;
303 static int32 a1_pitch;
304 static int32 a2_pitch;
305 static uint32 n_pixels;
306 static uint32 n_lines;
309 static int32 a1_width;
312 static int32 a2_width;
313 static int32 a2_mask_x;
314 static int32 a2_mask_y;
315 static int32 a1_xadd;
316 static int32 a1_yadd;
317 static int32 a2_xadd;
318 static int32 a2_yadd;
319 static uint8 a1_phrase_mode;
320 static uint8 a2_phrase_mode;
321 static int32 a1_step_x = 0;
322 static int32 a1_step_y = 0;
323 static int32 a2_step_x = 0;
324 static int32 a2_step_y = 0;
325 static uint32 outer_loop;
326 static uint32 inner_loop;
327 static uint32 a2_psize;
328 static uint32 a1_psize;
329 static uint32 gouraud_add;
330 //static uint32 gouraud_data;
331 //static uint16 gint[4];
332 //static uint16 gfrac[4];
333 //static uint8 gcolour[4];
336 static int gd_ia, gd_ca;
337 static int colour_index = 0;
339 static uint32 z_i[4];
341 static int32 a1_clip_x, a1_clip_y;
343 // In the spirit of "get it right first, *then* optimize" I've taken the liberty
344 // of removing all the unnecessary code caching. If it turns out to be a good way
345 // to optimize the blitter, then we may revisit it in the future...
348 // Generic blit handler
350 void blitter_generic(uint32 cmd)
353 Blit! (0018FA70 <- 008DDC40) count: 2 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C]
354 CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN
355 A1 step values: -2 (X), 1 (Y)
356 A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
357 A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
358 A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
359 A1 x/y: 100/12, A2 x/y: 106/0 Pattern: 000000F300000000
362 // specialLog = true;
363 /*if (cmd == 0x1401060C && blit_start_log)
364 specialLog = true;//*/
366 //uint32 logGo = ((cmd == 0x01800E01 && REG(A1_BASE) == 0x898000) ? 1 : 0);
367 uint32 srcdata, srczdata, dstdata, dstzdata, writedata, inhibit;
368 uint32 bppSrc = (DSTA2 ? 1 << ((REG(A1_FLAGS) >> 3) & 0x07) : 1 << ((REG(A2_FLAGS) >> 3) & 0x07));
372 WriteLog("About to do n x m blit (BM width is ? pixels)...\n");
373 WriteLog("A1_STEP_X/Y = %08X/%08X, A2_STEP_X/Y = %08X/%08X\n", a1_step_x, a1_step_y, a2_step_x, a2_step_y);
387 WriteLog(" A1_X/Y = %08X/%08X, A2_X/Y = %08X/%08X\n", a1_x, a1_y, a2_x, a2_y);
389 uint32 a1_start = a1_x, a2_start = a2_x, bitPos = 0;
391 //Kludge for Hover Strike...
392 //I wonder if this kludge is in conjunction with the SRCENX down below...
393 // This isn't so much a kludge but the way things work in BCOMPEN mode...!
394 if (BCOMPEN && SRCENX)
396 if (n_pixels < bppSrc)
397 bitPos = bppSrc - n_pixels;
400 inner_loop = n_pixels;
405 WriteLog(" A1_X/Y = %08X/%08X, A2_X/Y = %08X/%08X\n", a1_x, a1_y, a2_x, a2_y);
407 srcdata = srczdata = dstdata = dstzdata = writedata = inhibit = 0;
409 if (!DSTA2) // Data movement: A1 <- A2
411 // load src data and Z
413 if (SRCEN || SRCENX) // Not sure if this is correct... (seems to be...!)
415 srcdata = READ_PIXEL(a2, REG(A2_FLAGS));
418 srczdata = READ_ZDATA(a2, REG(A2_FLAGS));
419 else if (cmd & 0x0001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ
420 srczdata = READ_RDATA(SRCZINT, a2, REG(A2_FLAGS), a2_phrase_mode);
422 else // Use SRCDATA register...
424 srcdata = READ_RDATA(SRCDATA, a2, REG(A2_FLAGS), a2_phrase_mode);
426 if (cmd & 0x0001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ
427 srczdata = READ_RDATA(SRCZINT, a2, REG(A2_FLAGS), a2_phrase_mode);
430 // load dst data and Z
433 dstdata = READ_PIXEL(a1, REG(A1_FLAGS));
436 dstzdata = READ_ZDATA(a1, REG(A1_FLAGS));
438 dstzdata = READ_RDATA(DSTZ, a1, REG(A1_FLAGS), a1_phrase_mode);
442 dstdata = READ_RDATA(DSTDATA, a1, REG(A1_FLAGS), a1_phrase_mode);
445 dstzdata = READ_RDATA(DSTZ, a1, REG(A1_FLAGS), a1_phrase_mode);
448 /*This wasn't working... // a1 clipping
449 if (cmd & 0x00000040)
451 if (a1_x < 0 || a1_y < 0 || (a1_x >> 16) >= (REG(A1_CLIP) & 0x7FFF)
452 || (a1_y >> 16) >= ((REG(A1_CLIP) >> 16) & 0x7FFF))
457 srczdata = z_i[colour_index] >> 16;
459 // apply z comparator
460 if (Z_OP_INF && srczdata < dstzdata) inhibit = 1;
461 if (Z_OP_EQU && srczdata == dstzdata) inhibit = 1;
462 if (Z_OP_SUP && srczdata > dstzdata) inhibit = 1;
464 // apply data comparator
465 // Note: DCOMPEN only works in 8/16 bpp modes! !!! FIX !!!
466 // Does BCOMPEN only work in 1 bpp mode???
467 // No, but it always does a 1 bit expansion no matter what the BPP of the channel is set to. !!! FIX !!!
468 // This is bit tricky... We need to fix the XADD value so that it acts like a 1BPP value while inside
470 if (DCOMPEN | BCOMPEN)
472 //Temp, for testing Hover Strike
473 //Doesn't seem to do it... Why?
474 //What needs to happen here is twofold. First, the address generator in the outer loop has
475 //to honor the BPP when calculating the start address (which it kinda does already). Second,
476 //it has to step bit by bit when using BCOMPEN. How to do this???
478 //small problem with this approach: it's not accurate... We need a proper address to begin with
479 //and *then* we can do the bit stepping from there the way it's *supposed* to be done... !!! FIX !!!
482 uint32 pixShift = (~bitPos) & (bppSrc - 1);
483 srcdata = (srcdata >> pixShift) & 0x01;
486 // if (bitPos % bppSrc == 0)
487 // a2_x += 0x00010000;
490 Interesting (Hover Strike--large letter):
492 Blit! (0018FA70 <- 008DDC40) count: 2 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C]
493 CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN
494 A1 step values: -2 (X), 1 (Y)
495 A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
496 A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
497 A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
498 A1 x/y: 100/12, A2 x/y: 106/0 Pattern: 000000F300000000
500 Blit! (0018FA70 <- 008DDC40) count: 8 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C]
501 CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN
502 A1 step values: -8 (X), 1 (Y)
503 A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
504 A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
505 A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
506 A1 x/y: 102/12, A2 x/y: 107/0 Pattern: 000000F300000000
508 Blit! (0018FA70 <- 008DDC40) count: 1 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C]
509 CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN
510 A1 step values: -1 (X), 1 (Y)
511 A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
512 A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
513 A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
514 A1 x/y: 118/12, A2 x/y: 70/0 Pattern: 000000F300000000
516 Blit! (0018FA70 <- 008DDC40) count: 8 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C]
517 CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN
518 A1 step values: -8 (X), 1 (Y)
519 A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
520 A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
521 A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
522 A1 x/y: 119/12, A2 x/y: 71/0 Pattern: 000000F300000000
524 Blit! (0018FA70 <- 008DDC40) count: 1 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C]
525 CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN
526 A1 step values: -1 (X), 1 (Y)
527 A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
528 A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
529 A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
530 A1 x/y: 127/12, A2 x/y: 66/0 Pattern: 000000F300000000
532 Blit! (0018FA70 <- 008DDC40) count: 8 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C]
533 CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN
534 A1 step values: -8 (X), 1 (Y)
535 A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
536 A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
537 A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
538 A1 x/y: 128/12, A2 x/y: 67/0 Pattern: 000000F300000000
544 //WriteLog("Blitter: BCOMPEN set on command %08X inhibit prev:%u, now:", cmd, inhibit);
545 // compare source pixel with pattern pixel
547 Blit! (000B8250 <- 0012C3A0) count: 16 x 1, A1/2_FLAGS: 00014420/00012000 [cmd: 05810001]
548 CMD -> src: SRCEN dst: misc: a1ctl: mode: ity: PATDSEL z-op: op: LFU_REPLACE ctrl: BCOMPEN
549 A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 384 (22), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
550 A2 -> pitch: 1 phrases, depth: 1bpp, z-off: 0, width: 16 (10), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
554 // AvP is still wrong, could be cuz it's doing A1 -> A2...
556 // Src is the 1bpp bitmap... DST is the PATTERN!!!
557 // This seems to solve at least ONE of the problems with MC3D...
558 // Why should this be inverted???
559 // Bcuz it is. This is supposed to be used only for a bit -> pixel expansion...
560 /* if (srcdata == READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode))
561 // if (srcdata != READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode))
563 /* uint32 A2bpp = 1 << ((REG(A2_FLAGS) >> 3) & 0x07);
564 if (A2bpp == 1 || A2bpp == 16 || A2bpp == 8)
565 inhibit = (srcdata == 0 ? 1: 0);
566 // inhibit = !srcdata;
568 WriteLog("Blitter: Bad BPP (%u) selected for BCOMPEN mode!\n", A2bpp);//*/
569 // What it boils down to is this:
576 // compare destination pixel with pattern pixel
577 if (dstdata == READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode))
578 // if (dstdata != READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode))
582 // This is DEFINITELY WRONG
583 // if (a1_phrase_mode || a2_phrase_mode)
584 // inhibit = !inhibit;
589 inhibit |= (((a1_x >> 16) < a1_clip_x && (a1_x >> 16) >= 0
590 && (a1_y >> 16) < a1_clip_y && (a1_y >> 16) >= 0) ? 0 : 1);
593 // compute the write data and store
596 // Houston, we have a problem...
597 // Look here, at PATDSEL and GOURD. If both are active (as they are on the BIOS intro), then there's
599 //Blit! (00100000 <- 000095D0) count: 3 x 1, A1/2_FLAGS: 00014220/00004020 [cmd: 00011008]
600 // CMD -> src: dst: DSTEN misc: a1ctl: mode: GOURD ity: PATDSEL z-op: op: LFU_CLEAR ctrl:
601 // A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
602 // A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 256 (20), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
603 // A1 x/y: 90/171, A2 x/y: 808/0 Pattern: 776D770077007700
607 // use pattern data for write data
608 writedata = READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode);
612 /*if (blit_start_log)
613 WriteLog("BLIT: ADDDSEL srcdata: %08X\, dstdata: %08X, ", srcdata, dstdata);//*/
615 // intensity addition
616 //Ok, this is wrong... Or is it? Yes, it's wrong! !!! FIX !!!
617 /* writedata = (srcdata & 0xFF) + (dstdata & 0xFF);
618 if (!(TOPBEN) && writedata > 0xFF)
621 writedata |= (srcdata & 0xF00) + (dstdata & 0xF00);
622 if (!(TOPNEN) && writedata > 0xFFF)
623 // writedata = 0xFFF;
625 writedata |= (srcdata & 0xF000) + (dstdata & 0xF000);//*/
626 //notneeded--writedata &= 0xFFFF;
627 /*if (blit_start_log)
628 WriteLog("writedata: %08X\n", writedata);//*/
630 Hover Strike ADDDSEL blit:
632 Blit! (00098D90 <- 0081DDC0) count: 320 x 287, A1/2_FLAGS: 00004220/00004020 [cmd: 00020208]
633 CMD -> src: dst: DSTEN misc: a1ctl: UPDA1 mode: ity: ADDDSEL z-op: op: LFU_CLEAR ctrl:
634 A1 step values: -320 (X), 1 (Y)
635 A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
636 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 256 (20), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
637 A1 x/y: 0/0, A2 x/y: 3288/0 Pattern: 0000000000000000 SRCDATA: 00FD00FD00FD00FD
639 writedata = (srcdata & 0xFF) + (dstdata & 0xFF);
643 //This is correct now, but slow...
644 int16 s = (srcdata & 0xFF) | (srcdata & 0x80 ? 0xFF00 : 0x0000),
653 writedata = (uint32)sum;
656 //This doesn't seem right... Looks like it would muck up the low byte... !!! FIX !!!
657 writedata |= (srcdata & 0xF00) + (dstdata & 0xF00);
659 if (!TOPNEN && writedata > 0xFFF)
664 writedata |= (srcdata & 0xF000) + (dstdata & 0xF000);
668 if (LFU_NAN) writedata |= ~srcdata & ~dstdata;
669 if (LFU_NA) writedata |= ~srcdata & dstdata;
670 if (LFU_AN) writedata |= srcdata & ~dstdata;
671 if (LFU_A) writedata |= srcdata & dstdata;
674 //Although, this looks like it's OK... (even if it is shitty!)
675 //According to JTRM, this is part of the four things the blitter does with the write data (the other
676 //three being PATDSEL, ADDDSEL, and LFU (default). I'm not sure which gets precedence, this or PATDSEL
677 //(see above blit example)...
679 writedata = ((gd_c[colour_index]) << 8) | (gd_i[colour_index] >> 16);
683 int intensity = srcdata & 0xFF;
684 int ia = gd_ia >> 16;
686 ia = 0xFFFFFF00 | ia;
690 if (intensity > 0xFF)
692 writedata = (srcdata & 0xFF00) | intensity;
701 //Tried 2nd below for Hover Strike: No dice.
702 if (/*a1_phrase_mode || */BKGWREN || !inhibit)
703 // if (/*a1_phrase_mode || BKGWREN ||*/ !inhibit)
705 /*if (((REG(A1_FLAGS) >> 3) & 0x07) == 5)
707 uint32 offset = a1_addr+(PIXEL_OFFSET_32(a1)<<2);
708 // (((((UINT32)a##_y >> 16) * a##_width) + (((UINT32)a##_x >> 16) & ~1)) * (1 + a##_pitch) + (((UINT32)a##_x >> 16) & 1))
709 if ((offset >= 0x1FF020 && offset <= 0x1FF03F) || (offset >= 0x1FF820 && offset <= 0x1FF83F))
710 WriteLog("32bpp pixel write: A1 Phrase mode --> ");
712 // write to the destination
713 WRITE_PIXEL(a1, REG(A1_FLAGS), writedata);
715 WRITE_ZDATA(a1, REG(A1_FLAGS), srczdata);
718 else // if (DSTA2) // Data movement: A1 -> A2
720 // load src data and Z
723 srcdata = READ_PIXEL(a1, REG(A1_FLAGS));
725 srczdata = READ_ZDATA(a1, REG(A1_FLAGS));
726 else if (cmd & 0x0001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ
727 srczdata = READ_RDATA(SRCZINT, a1, REG(A1_FLAGS), a1_phrase_mode);
731 srcdata = READ_RDATA(SRCDATA, a1, REG(A1_FLAGS), a1_phrase_mode);
732 if (cmd & 0x001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ
733 srczdata = READ_RDATA(SRCZINT, a1, REG(A1_FLAGS), a1_phrase_mode);
736 // load dst data and Z
739 dstdata = READ_PIXEL(a2, REG(A2_FLAGS));
741 dstzdata = READ_ZDATA(a2, REG(A2_FLAGS));
743 dstzdata = READ_RDATA(DSTZ, a2, REG(A2_FLAGS), a2_phrase_mode);
747 dstdata = READ_RDATA(DSTDATA, a2, REG(A2_FLAGS), a2_phrase_mode);
749 dstzdata = READ_RDATA(DSTZ, a2, REG(A2_FLAGS), a2_phrase_mode);
753 srczdata = z_i[colour_index] >> 16;
755 // apply z comparator
756 if (Z_OP_INF && srczdata < dstzdata) inhibit = 1;
757 if (Z_OP_EQU && srczdata == dstzdata) inhibit = 1;
758 if (Z_OP_SUP && srczdata > dstzdata) inhibit = 1;
760 // apply data comparator
761 //NOTE: The bit comparator (BCOMPEN) is NOT the same at the data comparator!
762 if (DCOMPEN | BCOMPEN)
766 // compare source pixel with pattern pixel
767 // AvP: Numbers are correct, but sprites are not!
768 //This doesn't seem to be a problem... But could still be wrong...
769 /* if (srcdata == READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode))
770 // if (srcdata != READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode))
772 // This is probably not 100% correct... It works in the 1bpp case
773 // (in A1 <- A2 mode, that is...)
774 // AvP: This is causing blocks to be written instead of bit patterns...
776 // NOTE: We really should separate out the BCOMPEN & DCOMPEN stuff!
777 /* uint32 A1bpp = 1 << ((REG(A1_FLAGS) >> 3) & 0x07);
778 if (A1bpp == 1 || A1bpp == 16 || A1bpp == 8)
779 inhibit = (srcdata == 0 ? 1: 0);
781 WriteLog("Blitter: Bad BPP (%u) selected for BCOMPEN mode!\n", A1bpp);//*/
782 // What it boils down to is this:
788 // compare destination pixel with pattern pixel
789 if (dstdata == READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode))
790 // if (dstdata != READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode))
794 // This is DEFINITELY WRONG
795 // if (a1_phrase_mode || a2_phrase_mode)
796 // inhibit = !inhibit;
801 inhibit |= (((a1_x >> 16) < a1_clip_x && (a1_x >> 16) >= 0
802 && (a1_y >> 16) < a1_clip_y && (a1_y >> 16) >= 0) ? 0 : 1);
805 // compute the write data and store
810 // use pattern data for write data
811 writedata = READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode);
815 // intensity addition
816 writedata = (srcdata & 0xFF) + (dstdata & 0xFF);
817 if (!(TOPBEN) && writedata > 0xFF)
819 writedata |= (srcdata & 0xF00) + (dstdata & 0xF00);
820 if (!(TOPNEN) && writedata > 0xFFF)
822 writedata |= (srcdata & 0xF000) + (dstdata & 0xF000);
827 writedata |= ~srcdata & ~dstdata;
829 writedata |= ~srcdata & dstdata;
831 writedata |= srcdata & ~dstdata;
833 writedata |= srcdata & dstdata;
837 writedata = ((gd_c[colour_index]) << 8) | (gd_i[colour_index] >> 16);
841 int intensity = srcdata & 0xFF;
842 int ia = gd_ia >> 16;
844 ia = 0xFFFFFF00 | ia;
848 if (intensity > 0xFF)
850 writedata = (srcdata & 0xFF00) | intensity;
859 if (/*a2_phrase_mode || */BKGWREN || !inhibit)
863 uint32 offset = a2_addr+(PIXEL_OFFSET_16(a2)<<1);
864 // (((((UINT32)a##_y >> 16) * a##_width) + (((UINT32)a##_x >> 16) & ~1)) * (1 + a##_pitch) + (((UINT32)a##_x >> 16) & 1))
865 WriteLog("[%08X:%04X] ", offset, writedata);
867 // write to the destination
868 WRITE_PIXEL(a2, REG(A2_FLAGS), writedata);
871 WRITE_ZDATA(a2, REG(A2_FLAGS), srczdata);
875 // Update x and y (inner loop)
876 //Now it does! But crappy, crappy, crappy! !!! FIX !!! [DONE]
877 //This is less than ideal, but it works...
880 a1_x += a1_xadd, a1_y += a1_yadd;
881 a2_x = (a2_x + a2_xadd) & a2_mask_x, a2_y = (a2_y + a2_yadd) & a2_mask_y;
885 a1_y += a1_yadd, a2_y = (a2_y + a2_yadd) & a2_mask_y;
889 if (bitPos % bppSrc == 0)
890 a2_x = (a2_x + a2_xadd) & a2_mask_x;
894 a2_x = (a2_x + a2_xadd) & a2_mask_x;
895 if (bitPos % bppSrc == 0)
901 z_i[colour_index] += zadd;
903 if (GOURD || SRCSHADE)
905 gd_i[colour_index] += gd_ia;
906 //Hmm, this doesn't seem to do anything...
907 //But it is correct according to the JTRM...!
908 if ((int32)gd_i[colour_index] < 0)
909 gd_i[colour_index] = 0;
910 if (gd_i[colour_index] > 0x00FFFFFF)
911 gd_i[colour_index] = 0x00FFFFFF;//*/
913 gd_c[colour_index] += gd_ca;
914 if ((int32)gd_c[colour_index] < 0)
915 gd_c[colour_index] = 0;
916 if (gd_c[colour_index] > 0x000000FF)
917 gd_c[colour_index] = 0x000000FF;//*/
920 if (GOURD || SRCSHADE || GOURZ)
923 //This screws things up WORSE (for the BIOS opening screen)
924 // if (a1_phrase_mode || a2_phrase_mode)
925 colour_index = (colour_index + 1) & 0x03;
930 Here's the problem... The phrase mode code!
931 Blit! (00100000 -> 00148000) count: 327 x 267, A1/2_FLAGS: 00004420/00004420 [cmd: 41802E01]
932 CMD -> src: SRCEN dst: misc: a1ctl: UPDA1 UPDA2 mode: DSTA2 GOURZ ity: z-op: op: LFU_REPLACE ctrl: SRCSHADE
933 A1 step values: -327 (X), 1 (Y)
934 A2 step values: -327 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
935 A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 384 (22), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
936 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 384 (22), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
937 A1 x/y: 28/58, A2 x/y: 28/58 Pattern: 00EA7BEA77EA77EA SRCDATA: 7BFF7BFF7BFF7BFF
939 Below fixes it, but then borks:
942 Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609]
943 CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN
944 A1 step values: -15 (X), 1 (Y)
945 A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
946 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
947 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
948 A1 x/y: 173/144, A2 x/y: 4052/0
950 Lesse, with pre-add we'd have:
953 00001111222233334444555566667777
956 |rolls back to here. Hmm.
959 //NOTE: The way to fix the CD BIOS is to uncomment below and comment the stuff after
960 // the phrase mode mucking around. But it fucks up everything else...
961 #define SCREWY_CD_DEPENDENT
962 #ifdef SCREWY_CD_DEPENDENT
966 a2_y += a2_step_y;//*/
969 //New: Phrase mode taken into account! :-p
970 /* if (a1_phrase_mode) // v1
972 // Bump the pointer to the next phrase boundary
973 // Even though it works, this is crappy... Clean it up!
974 uint32 size = 64 / a1_psize;
976 // Crappy kludge... ('aligning' source to destination)
977 if (a2_phrase_mode && DSTA2)
979 uint32 extra = (a2_start >> 16) % size;
983 uint32 newx = (a1_x >> 16) / size;
984 uint32 newxrem = (a1_x >> 16) % size;
986 a1_x |= (((newx + (newxrem == 0 ? 0 : 1)) * size) & 0xFFFF) << 16;
988 if (a1_phrase_mode) // v2
990 // Bump the pointer to the next phrase boundary
991 // Even though it works, this is crappy... Clean it up!
992 uint32 size = 64 / a1_psize;
994 // Crappy kludge... ('aligning' source to destination)
995 if (a2_phrase_mode && DSTA2)
997 uint32 extra = (a2_start >> 16) % size;
1001 uint32 pixelSize = (size - 1) << 16;
1002 a1_x = (a1_x + pixelSize) & ~pixelSize;
1005 /* if (a2_phrase_mode) // v1
1007 // Bump the pointer to the next phrase boundary
1008 // Even though it works, this is crappy... Clean it up!
1009 uint32 size = 64 / a2_psize;
1011 // Crappy kludge... ('aligning' source to destination)
1012 // Prolly should do this for A1 channel as well... [DONE]
1013 if (a1_phrase_mode && !DSTA2)
1015 uint32 extra = (a1_start >> 16) % size;
1016 a2_x += extra << 16;
1019 uint32 newx = (a2_x >> 16) / size;
1020 uint32 newxrem = (a2_x >> 16) % size;
1022 a2_x |= (((newx + (newxrem == 0 ? 0 : 1)) * size) & 0xFFFF) << 16;
1024 if (a2_phrase_mode) // v1
1026 // Bump the pointer to the next phrase boundary
1027 // Even though it works, this is crappy... Clean it up!
1028 uint32 size = 64 / a2_psize;
1030 // Crappy kludge... ('aligning' source to destination)
1031 // Prolly should do this for A1 channel as well... [DONE]
1032 if (a1_phrase_mode && !DSTA2)
1034 uint32 extra = (a1_start >> 16) % size;
1035 a2_x += extra << 16;
1038 uint32 pixelSize = (size - 1) << 16;
1039 a2_x = (a2_x + pixelSize) & ~pixelSize;
1042 //Not entirely: This still mucks things up... !!! FIX !!!
1043 //Should this go before or after the phrase mode mucking around?
1044 #ifndef SCREWY_CD_DEPENDENT
1048 a2_y += a2_step_y;//*/
1052 // write values back to registers
1053 WREG(A1_PIXEL, (a1_y & 0xFFFF0000) | ((a1_x >> 16) & 0xFFFF));
1054 WREG(A1_FPIXEL, (a1_y << 16) | (a1_x & 0xFFFF));
1055 WREG(A2_PIXEL, (a2_y & 0xFFFF0000) | ((a2_x >> 16) & 0xFFFF));
1059 void blitter_blit(uint32 cmd)
1061 //Apparently this is doing *something*, just not sure exactly what...
1062 /*if (cmd == 0x41802E01)
1064 WriteLog("BLIT: Found our blit. Was: %08X ", cmd);
1066 WriteLog("Is: %08X\n", cmd);
1069 uint32 pitchValue[4] = { 0, 1, 3, 2 };
1072 dst = (cmd >> 3) & 0x07;
1073 misc = (cmd >> 6) & 0x03;
1074 a1ctl = (cmd >> 8) & 0x7;
1075 mode = (cmd >> 11) & 0x07;
1076 ity = (cmd >> 14) & 0x0F;
1077 zop = (cmd >> 18) & 0x07;
1078 op = (cmd >> 21) & 0x0F;
1079 ctrl = (cmd >> 25) & 0x3F;
1081 // Addresses in A1/2_BASE are *phrase* aligned, i.e., bottom three bits are ignored!
1082 // NOTE: This fixes Rayman's bad collision detection AND keeps T2K working!
1083 a1_addr = REG(A1_BASE) & 0xFFFFFFF8;
1084 a2_addr = REG(A2_BASE) & 0xFFFFFFF8;
1086 a1_zoffs = (REG(A1_FLAGS) >> 6) & 7;
1087 a2_zoffs = (REG(A2_FLAGS) >> 6) & 7;
1089 xadd_a1_control = (REG(A1_FLAGS) >> 16) & 0x03;
1090 xadd_a2_control = (REG(A2_FLAGS) >> 16) & 0x03;
1092 a1_pitch = pitchValue[(REG(A1_FLAGS) & 0x03)];
1093 a2_pitch = pitchValue[(REG(A2_FLAGS) & 0x03)];
1095 n_pixels = REG(PIXLINECOUNTER) & 0xFFFF;
1096 n_lines = (REG(PIXLINECOUNTER) >> 16) & 0xFFFF;
1098 a1_x = (REG(A1_PIXEL) << 16) | (REG(A1_FPIXEL) & 0xFFFF);
1099 a1_y = (REG(A1_PIXEL) & 0xFFFF0000) | (REG(A1_FPIXEL) >> 16);
1100 //According to the JTRM, X is restricted to 15 bits and Y is restricted to 12.
1101 //But it seems to fuck up T2K! !!! FIX !!!
1102 //Could it be sign extended??? Doesn't seem to be so according to JTRM
1103 // a1_x &= 0x7FFFFFFF, a1_y &= 0x0FFFFFFF;
1104 //Actually, it says that the X is 16 bits. But it still seems to mess with the Y when restricted to 12...
1105 // a1_y &= 0x0FFFFFFF;
1107 // a1_width = blitter_scanline_width[((REG(A1_FLAGS) & 0x00007E00) >> 9)];
1108 // According to JTRM, this must give a *whole number* of phrases in the current
1109 // pixel size (this means the lookup above is WRONG)... !!! FIX !!!
1110 UINT32 m = (REG(A1_FLAGS) >> 9) & 0x03, e = (REG(A1_FLAGS) >> 11) & 0x0F;
1111 a1_width = ((0x04 | m) << e) >> 2;//*/
1113 a2_x = (REG(A2_PIXEL) & 0x0000FFFF) << 16;
1114 a2_y = (REG(A2_PIXEL) & 0xFFFF0000);
1115 //According to the JTRM, X is restricted to 15 bits and Y is restricted to 12.
1116 //But it seems to fuck up T2K! !!! FIX !!!
1117 // a2_x &= 0x7FFFFFFF, a2_y &= 0x0FFFFFFF;
1118 //Actually, it says that the X is 16 bits. But it still seems to mess with the Y when restricted to 12...
1119 // a2_y &= 0x0FFFFFFF;
1121 // a2_width = blitter_scanline_width[((REG(A2_FLAGS) & 0x00007E00) >> 9)];
1122 // According to JTRM, this must give a *whole number* of phrases in the current
1123 // pixel size (this means the lookup above is WRONG)... !!! FIX !!!
1124 m = (REG(A2_FLAGS) >> 9) & 0x03, e = (REG(A2_FLAGS) >> 11) & 0x0F;
1125 a2_width = ((0x04 | m) << e) >> 2;//*/
1126 a2_mask_x = ((REG(A2_MASK) & 0x0000FFFF) << 16) | 0xFFFF;
1127 a2_mask_y = (REG(A2_MASK) & 0xFFFF0000) | 0xFFFF;
1129 // Check for "use mask" flag
1130 if (!(REG(A2_FLAGS) & 0x8000))
1132 a2_mask_x = 0xFFFFFFFF; // must be 16.16
1133 a2_mask_y = 0xFFFFFFFF; // must be 16.16
1138 // According to the official documentation, a hardware bug ties A2's yadd bit to A1's...
1139 a2_yadd = a1_yadd = (YADD1_A1 ? 1 << 16 : 0);
1144 // determine a1_xadd
1145 switch (xadd_a1_control)
1148 // This is a documented Jaguar bug relating to phrase mode and truncation... Look into it!
1149 // add phrase offset to X and truncate
1154 // add pixelsize (1) to X
1158 // add zero (for those nice vertical lines)
1162 // add the contents of the increment register
1163 a1_xadd = (REG(A1_INC) << 16) | (REG(A1_FINC) & 0x0000FFFF);
1164 a1_yadd = (REG(A1_INC) & 0xFFFF0000) | (REG(A1_FINC) >> 16);
1169 //Blit! (0011D000 -> 000B9600) count: 228 x 1, A1/2_FLAGS: 00073820/00064220 [cmd: 41802801]
1170 // A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 128 (1C), addctl: XADDINC YADD1 XSIGNADD YSIGNADD
1171 // A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 320 (21), addctl: XADD0 YADD1 XSIGNADD YSIGNADD
1172 //if (YADD1_A1 && YADD1_A2 && xadd_a2_control == XADD0 && xadd_a1_control == XADDINC)// &&
1173 // UINT32 a1f = REG(A1_FLAGS), a2f = REG(A2_FLAGS);
1174 //Ok, so this ISN'T it... Prolly the XADDPHR code above that's doing it...
1175 //if (REG(A1_FLAGS) == 0x00073820 && REG(A2_FLAGS) == 0x00064220 && cmd == 0x41802801)
1176 // A1 x/y: 14368/7, A2 x/y: 150/36
1177 //This is it... The problem...
1178 //if ((a1_x >> 16) == 14368) // 14368 = $3820
1179 // return; //Lesse what we got...
1189 // determine a2_xadd
1190 switch (xadd_a2_control)
1193 // add phrase offset to X and truncate
1198 // add pixelsize (1) to X
1202 // add zero (for those nice vertical lines)
1205 //This really isn't a valid bit combo for A2... Shouldn't this cause the blitter to just say no?
1207 WriteLog("BLIT: Asked to use invalid bit combo (XADDINC) for A2...\n");
1208 // add the contents of the increment register
1209 // since there is no register for a2 we just add 1
1210 //Let's do nothing, since it's not listed as a valid bit combo...
1211 // a2_xadd = 1 << 16;
1218 // Modify outer loop steps based on blitter command
1226 a1_step_x = (REG(A1_FSTEP) & 0xFFFF),
1227 a1_step_y = (REG(A1_FSTEP) >> 16);
1230 a1_step_x |= ((REG(A1_STEP) & 0x0000FFFF) << 16),
1231 a1_step_y |= ((REG(A1_STEP) & 0xFFFF0000));
1234 a2_step_x = (REG(A2_STEP) & 0x0000FFFF) << 16,
1235 a2_step_y = (REG(A2_STEP) & 0xFFFF0000);
1237 outer_loop = n_lines;
1242 a1_clip_x = REG(A1_CLIP) & 0x7FFF,
1243 a1_clip_y = (REG(A1_CLIP) >> 16) & 0x7FFF;
1245 // This phrase sizing is incorrect as well... !!! FIX !!! [NOTHING TO FIX]
1246 // Err, this is pixel size... (and it's OK)
1247 a2_psize = 1 << ((REG(A2_FLAGS) >> 3) & 0x07);
1248 a1_psize = 1 << ((REG(A1_FLAGS) >> 3) & 0x07);
1255 for(int v=0; v<4; v++)
1256 z_i[v] = REG(PHRASEZ0 + v*4);
1260 if (GOURD || GOURZ || SRCSHADE)
1262 gd_c[0] = blitter_ram[PATTERNDATA + 6];
1263 gd_i[0] = ((uint32)blitter_ram[PATTERNDATA + 7] << 16)
1264 | ((uint32)blitter_ram[SRCDATA + 6] << 8) | blitter_ram[SRCDATA + 1];
1266 gd_c[1] = blitter_ram[PATTERNDATA + 4];
1267 gd_i[1] = ((uint32)blitter_ram[PATTERNDATA + 5] << 16)
1268 | ((uint32)blitter_ram[SRCDATA + 4] << 8) | blitter_ram[SRCDATA + 3];
1270 gd_c[2] = blitter_ram[PATTERNDATA + 2];
1271 gd_i[2] = ((uint32)blitter_ram[PATTERNDATA + 3] << 16)
1272 | ((uint32)blitter_ram[SRCDATA + 2] << 8) | blitter_ram[SRCDATA + 5];
1274 gd_c[3] = blitter_ram[PATTERNDATA + 0];
1275 gd_i[3] = ((uint32)blitter_ram[PATTERNDATA + 1] << 16)
1276 | ((uint32)blitter_ram[SRCDATA + 0] << 8) | blitter_ram[SRCDATA + 7];
1278 gouraud_add = REG(INTENSITYINC);
1280 gd_ia = gouraud_add & 0x00FFFFFF;
1281 if (gd_ia & 0x00800000)
1282 gd_ia = 0xFF000000 | gd_ia;
1284 gd_ca = (gouraud_add >> 24) & 0xFF;
1285 if (gd_ca & 0x00000080)
1286 gd_ca = 0xFFFFFF00 | gd_ca;
1289 // Bit comparitor fixing...
1292 // Determine the data flow direction...
1294 a2_step_x /= (1 << ((REG(A2_FLAGS) >> 3) & 0x07));
1298 /* if (BCOMPEN)//Kludge for Hover Strike... !!! FIX !!!
1300 // Determine the data flow direction...
1308 WriteLog("Blit!\n");
1309 WriteLog(" cmd = 0x%.8x\n",cmd);
1310 WriteLog(" a1_base = %08X\n", a1_addr);
1311 WriteLog(" a1_pitch = %d\n", a1_pitch);
1312 WriteLog(" a1_psize = %d\n", a1_psize);
1313 WriteLog(" a1_width = %d\n", a1_width);
1314 WriteLog(" a1_xadd = %f (phrase=%d)\n", (float)a1_xadd / 65536.0, a1_phrase_mode);
1315 WriteLog(" a1_yadd = %f\n", (float)a1_yadd / 65536.0);
1316 WriteLog(" a1_xstep = %f\n", (float)a1_step_x / 65536.0);
1317 WriteLog(" a1_ystep = %f\n", (float)a1_step_y / 65536.0);
1318 WriteLog(" a1_x = %f\n", (float)a1_x / 65536.0);
1319 WriteLog(" a1_y = %f\n", (float)a1_y / 65536.0);
1320 WriteLog(" a1_zoffs = %i\n",a1_zoffs);
1322 WriteLog(" a2_base = %08X\n", a2_addr);
1323 WriteLog(" a2_pitch = %d\n", a2_pitch);
1324 WriteLog(" a2_psize = %d\n", a2_psize);
1325 WriteLog(" a2_width = %d\n", a2_width);
1326 WriteLog(" a2_xadd = %f (phrase=%d)\n", (float)a2_xadd / 65536.0, a2_phrase_mode);
1327 WriteLog(" a2_yadd = %f\n", (float)a2_yadd / 65536.0);
1328 WriteLog(" a2_xstep = %f\n", (float)a2_step_x / 65536.0);
1329 WriteLog(" a2_ystep = %f\n", (float)a2_step_y / 65536.0);
1330 WriteLog(" a2_x = %f\n", (float)a2_x / 65536.0);
1331 WriteLog(" a2_y = %f\n", (float)a2_y / 65536.0);
1332 WriteLog(" a2_mask_x= 0x%.4x\n",a2_mask_x);
1333 WriteLog(" a2_mask_y= 0x%.4x\n",a2_mask_y);
1334 WriteLog(" a2_zoffs = %i\n",a2_zoffs);
1336 WriteLog(" count = %d x %d\n", n_pixels, n_lines);
1338 WriteLog(" command = %08X\n", cmd);
1339 WriteLog(" dsten = %i\n",DSTEN);
1340 WriteLog(" srcen = %i\n",SRCEN);
1341 WriteLog(" patdsel = %i\n",PATDSEL);
1342 WriteLog(" color = 0x%.8x\n",REG(PATTERNDATA));
1343 WriteLog(" dcompen = %i\n",DCOMPEN);
1344 WriteLog(" bcompen = %i\n",BCOMPEN);
1345 WriteLog(" cmpdst = %i\n",CMPDST);
1346 WriteLog(" GOURZ = %i\n",GOURZ);
1347 WriteLog(" GOURD = %i\n",GOURD);
1348 WriteLog(" SRCSHADE= %i\n",SRCSHADE);
1352 //NOTE: Pitch is ignored!
1354 //This *might* be the altimeter blits (they are)...
1355 //On captured screen, x-pos for black (inner) is 259, for pink is 257
1356 //Black is short by 3, pink is short by 1...
1358 Blit! (00110000 <- 000BF010) count: 9 x 31, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200]
1359 CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl:
1360 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1361 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
1362 A1 x/y: 262/124, A2 x/y: 128/0
1363 Blit! (00110000 <- 000BF010) count: 5 x 38, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200]
1364 CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl:
1365 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1366 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
1367 A1 x/y: 264/117, A2 x/y: 407/0
1369 Blit! (00110000 <- 000BF010) count: 9 x 23, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200]
1370 CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl:
1371 A1 step values: -10 (X), 1 (Y)
1372 A1 -> pitch: 4(2) phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1373 A2 -> pitch: 1(0) phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
1374 A1 x/y: 262/132, A2 x/y: 129/0
1375 Blit! (00110000 <- 000BF010) count: 5 x 27, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200]
1376 CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl:
1377 A1 step values: -8 (X), 1 (Y)
1378 A1 -> pitch: 4(2) phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1379 A2 -> pitch: 1(0) phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD
1380 A1 x/y: 264/128, A2 x/y: 336/0
1382 264v vCursor ends up here...
1386 262v vCursor ends up here...
1390 Fixed! Now for more:
1392 ; This looks like the ship icon in the upper left corner...
1394 Blit! (00110000 <- 0010B2A8) count: 11 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609]
1395 CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN
1396 A1 step values: -12 (X), 1 (Y)
1397 A2 step values: 0 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
1398 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1399 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1400 A1 x/y: 20/24, A2 x/y: 5780/0
1404 More (not sure this is a blitter problem as much as it's a GPU problem):
1405 All but the "M" are trashed...
1406 This does *NOT* look like a blitter problem, as it's rendering properly...
1407 Actually, if you look at the A1 step values, there IS a discrepancy!
1411 Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609]
1412 CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN
1413 A1 step values: -14 (X), 1 (Y)
1414 A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
1415 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1416 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1417 A1 x/y: 134/144, A2 x/y: 2516/0
1422 Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609]
1423 CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN
1424 A1 step values: -13 (X), 1 (Y)
1425 A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
1426 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1427 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1428 A1 x/y: 147/144, A2 x/y: 2660/0
1432 Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609]
1433 CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN
1434 A1 step values: -12 (X), 1 (Y)
1435 A2 step values: 0 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
1436 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1437 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1438 A1 x/y: 160/144, A2 x/y: 3764/0
1442 Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609]
1443 CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN
1444 A1 step values: -15 (X), 1 (Y)
1445 A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF]
1446 A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1447 A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD
1448 A1 x/y: 173/144, A2 x/y: 4052/0
1451 //extern int op_start_log;
1454 char * ctrlStr[4] = { "XADDPHR\0", "XADDPIX\0", "XADD0\0", "XADDINC\0" };
1455 char * bppStr[8] = { "1bpp\0", "2bpp\0", "4bpp\0", "8bpp\0", "16bpp\0", "32bpp\0", "???\0", "!!!\0" };
1456 char * opStr[16] = { "LFU_CLEAR", "LFU_NSAND", "LFU_NSAD", "LFU_NOTS", "LFU_SAND", "LFU_NOTD", "LFU_N_SXORD", "LFU_NSORND",
1457 "LFU_SAD", "LFU_XOR", "LFU_D", "LFU_NSORD", "LFU_REPLACE", "LFU_SORND", "LFU_SORD", "LFU_ONE" };
1458 uint32 /*src = cmd & 0x07, dst = (cmd >> 3) & 0x07, misc = (cmd >> 6) & 0x03,
1459 a1ctl = (cmd >> 8) & 0x07,*/ mode = (cmd >> 11) & 0x07/*, ity = (cmd >> 14) & 0x0F,
1460 zop = (cmd >> 18) & 0x07, op = (cmd >> 21) & 0x0F, ctrl = (cmd >> 25) & 0x3F*/;
1461 UINT32 a1f = REG(A1_FLAGS), a2f = REG(A2_FLAGS);
1462 uint32 p1 = a1f & 0x07, p2 = a2f & 0x07,
1463 d1 = (a1f >> 3) & 0x07, d2 = (a2f >> 3) & 0x07,
1464 zo1 = (a1f >> 6) & 0x07, zo2 = (a2f >> 6) & 0x07,
1465 w1 = (a1f >> 9) & 0x3F, w2 = (a2f >> 9) & 0x3F,
1466 ac1 = (a1f >> 16) & 0x1F, ac2 = (a2f >> 16) & 0x1F;
1467 UINT32 iw1 = ((0x04 | (w1 & 0x03)) << ((w1 & 0x3C) >> 2)) >> 2;
1468 UINT32 iw2 = ((0x04 | (w2 & 0x03)) << ((w2 & 0x3C) >> 2)) >> 2;
1469 WriteLog("Blit! (%08X %s %08X) count: %d x %d, A1/2_FLAGS: %08X/%08X [cmd: %08X]\n", a1_addr, (mode&0x01 ? "->" : "<-"), a2_addr, n_pixels, n_lines, a1f, a2f, cmd);
1470 // WriteLog(" CMD -> src: %d, dst: %d, misc: %d, a1ctl: %d, mode: %d, ity: %1X, z-op: %d, op: %1X, ctrl: %02X\n", src, dst, misc, a1ctl, mode, ity, zop, op, ctrl);
1472 WriteLog(" CMD -> src: %s%s%s ", (cmd & 0x0001 ? "SRCEN " : ""), (cmd & 0x0002 ? "SRCENZ " : ""), (cmd & 0x0004 ? "SRCENX" : ""));
1473 WriteLog("dst: %s%s%s ", (cmd & 0x0008 ? "DSTEN " : ""), (cmd & 0x0010 ? "DSTENZ " : ""), (cmd & 0x0020 ? "DSTWRZ" : ""));
1474 WriteLog("misc: %s%s ", (cmd & 0x0040 ? "CLIP_A1 " : ""), (cmd & 0x0080 ? "???" : ""));
1475 WriteLog("a1ctl: %s%s%s ", (cmd & 0x0100 ? "UPDA1F " : ""), (cmd & 0x0200 ? "UPDA1 " : ""), (cmd & 0x0400 ? "UPDA2" : ""));
1476 WriteLog("mode: %s%s%s ", (cmd & 0x0800 ? "DSTA2 " : ""), (cmd & 0x1000 ? "GOURD " : ""), (cmd & 0x2000 ? "GOURZ" : ""));
1477 WriteLog("ity: %s%s%s%s ", (cmd & 0x4000 ? "TOPBEN " : ""), (cmd & 0x8000 ? "TOPNEN " : ""), (cmd & 0x00010000 ? "PATDSEL" : ""), (cmd & 0x00020000 ? "ADDDSEL" : ""));
1478 WriteLog("z-op: %s%s%s ", (cmd & 0x00040000 ? "ZMODELT " : ""), (cmd & 0x00080000 ? "ZMODEEQ " : ""), (cmd & 0x00100000 ? "ZMODEGT" : ""));
1479 WriteLog("op: %s ", opStr[(cmd >> 21) & 0x0F]);
1480 WriteLog("ctrl: %s%s%s%s%s%s\n", (cmd & 0x02000000 ? "CMPDST " : ""), (cmd & 0x04000000 ? "BCOMPEN " : ""), (cmd & 0x08000000 ? "DCOMPEN " : ""), (cmd & 0x10000000 ? "BKGWREN " : ""), (cmd & 0x20000000 ? "BUSHI " : ""), (cmd & 0x40000000 ? "SRCSHADE" : ""));
1483 WriteLog(" A1 step values: %d (X), %d (Y)\n", a1_step_x >> 16, a1_step_y >> 16);
1486 WriteLog(" A2 step values: %d (X), %d (Y) [mask (%sused): %08X - %08X/%08X]\n", a2_step_x >> 16, a2_step_y >> 16, (a2f & 0x8000 ? "" : "un"), REG(A2_MASK), a2_mask_x, a2_mask_y);
1488 WriteLog(" A1 -> pitch: %d phrases, depth: %s, z-off: %d, width: %d (%02X), addctl: %s %s %s %s\n", 1 << p1, bppStr[d1], zo1, iw1, w1, ctrlStr[ac1&0x03], (ac1&0x04 ? "YADD1" : "YADD0"), (ac1&0x08 ? "XSIGNSUB" : "XSIGNADD"), (ac1&0x10 ? "YSIGNSUB" : "YSIGNADD"));
1489 WriteLog(" A2 -> pitch: %d phrases, depth: %s, z-off: %d, width: %d (%02X), addctl: %s %s %s %s\n", 1 << p2, bppStr[d2], zo2, iw2, w2, ctrlStr[ac2&0x03], (ac2&0x04 ? "YADD1" : "YADD0"), (ac2&0x08 ? "XSIGNSUB" : "XSIGNADD"), (ac2&0x10 ? "YSIGNSUB" : "YSIGNADD"));
1490 WriteLog(" A1 x/y: %d/%d, A2 x/y: %d/%d Pattern: %08X%08X SRCDATA: %08X%08X\n", a1_x >> 16, a1_y >> 16, a2_x >> 16, a2_y >> 16, REG(PATTERNDATA), REG(PATTERNDATA + 4), REG(SRCDATA), REG(SRCDATA + 4));
1491 // blit_start_log = 0;
1492 // op_start_log = 1;
1495 blitter_working = 1;
1496 //#ifndef USE_GENERIC_BLITTER
1497 // if (!blitter_execute_cached_code(blitter_in_cache(cmd)))
1499 blitter_generic(cmd);
1501 /*if (blit_start_log)
1503 if (a1_addr == 0xF03000 && a2_addr == 0x004D58)
1505 WriteLog("\nBytes at 004D58:\n");
1506 for(int i=0x004D58; i<0x004D58+(10*127*4); i++)
1507 WriteLog("%02X ", JaguarReadByte(i));
1508 WriteLog("\nBytes at F03000:\n");
1509 for(int i=0xF03000; i<0xF03000+(6*127*4); i++)
1510 WriteLog("%02X ", JaguarReadByte(i));
1515 blitter_working = 0;
1517 #endif // of the #if 0 near the top...
1518 /*******************************************************************************
1519 ********************** STUFF CUT ABOVE THIS LINE! ******************************
1520 *******************************************************************************/
1522 void blitter_init(void)
1527 void blitter_reset(void)
1529 memset(blitter_ram, 0x00, 0xA0);
1532 void blitter_done(void)
1534 WriteLog("BLIT: Done.\n");
1537 uint8 BlitterReadByte(uint32 offset, uint32 who/*=UNKNOWN*/)
1542 //This isn't cycle accurate--how to fix? !!! FIX !!!
1543 //Probably have to do some multi-threaded implementation or at least a reentrant safe implementation...
1544 if (offset == (0x38 + 3))
1545 return 0x01; // always idle
1547 // CHECK HERE ONCE THIS FIX HAS BEEN TESTED: [ ]
1549 if (offset >= 0x04 && offset <= 0x07)
1550 //This is it. I wonder if it just ignores the lower three bits?
1551 //No, this is a documented Jaguar I bug. It also bites the read at $F02230 as well...
1552 return blitter_ram[offset + 0x08]; // A1_PIXEL ($F0220C) read at $F02204
1554 if (offset >= 0x2C && offset <= 0x2F)
1555 return blitter_ram[offset + 0x04]; // A2_PIXEL ($F02230) read at $F0222C
1557 return blitter_ram[offset];
1561 uint16 BlitterReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
1563 return ((uint16)BlitterReadByte(offset, who) << 8) | (uint16)BlitterReadByte(offset+1, who);
1567 uint32 BlitterReadLong(uint32 offset, uint32 who/*=UNKNOWN*/)
1569 return (BlitterReadWord(offset, who) << 16) | BlitterReadWord(offset+2, who);
1572 void BlitterWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
1574 /*if (offset & 0xFF == 0x7B)
1575 WriteLog("--> Wrote to B_STOP: value -> %02X\n", data);*/
1577 /*if ((offset >= PATTERNDATA) && (offset < PATTERNDATA + 8))
1579 printf("--> %s wrote %02X to byte %u of PATTERNDATA...\n", whoName[who], data, offset - PATTERNDATA);
1583 // This handles writes to INTENSITY0-3 by also writing them to their proper places in
1584 // PATTERNDATA & SOURCEDATA (should do the same for the Z registers! !!! FIX !!! [DONE])
1585 if ((offset >= 0x7C) && (offset <= 0x9B))
1589 // INTENSITY registers 0-3
1591 case 0x7D: blitter_ram[PATTERNDATA + 7] = data; break;
1592 case 0x7E: blitter_ram[SRCDATA + 6] = data; break;
1593 case 0x7F: blitter_ram[SRCDATA + 7] = data; break;
1596 case 0x81: blitter_ram[PATTERNDATA + 5] = data; break;
1597 case 0x82: blitter_ram[SRCDATA + 4] = data; break;
1598 case 0x83: blitter_ram[SRCDATA + 5] = data; break;
1601 case 0x85: blitter_ram[PATTERNDATA + 3] = data; break;
1602 case 0x86: blitter_ram[SRCDATA + 2] = data; break;
1603 case 0x87: blitter_ram[SRCDATA + 3] = data; break;
1606 case 0x89: blitter_ram[PATTERNDATA + 1] = data; break;
1607 case 0x8A: blitter_ram[SRCDATA + 0] = data; break;
1608 case 0x8B: blitter_ram[SRCDATA + 1] = data; break;
1612 case 0x8C: blitter_ram[SRCZINT + 6] = data; break;
1613 case 0x8D: blitter_ram[SRCZINT + 7] = data; break;
1614 case 0x8E: blitter_ram[SRCZFRAC + 6] = data; break;
1615 case 0x8F: blitter_ram[SRCZFRAC + 7] = data; break;
1617 case 0x90: blitter_ram[SRCZINT + 4] = data; break;
1618 case 0x91: blitter_ram[SRCZINT + 5] = data; break;
1619 case 0x92: blitter_ram[SRCZFRAC + 4] = data; break;
1620 case 0x93: blitter_ram[SRCZFRAC + 5] = data; break;
1622 case 0x94: blitter_ram[SRCZINT + 2] = data; break;
1623 case 0x95: blitter_ram[SRCZINT + 3] = data; break;
1624 case 0x96: blitter_ram[SRCZFRAC + 2] = data; break;
1625 case 0x97: blitter_ram[SRCZFRAC + 3] = data; break;
1627 case 0x98: blitter_ram[SRCZINT + 0] = data; break;
1628 case 0x99: blitter_ram[SRCZINT + 1] = data; break;
1629 case 0x9A: blitter_ram[SRCZFRAC + 0] = data; break;
1630 case 0x9B: blitter_ram[SRCZFRAC + 1] = data; break;
1634 // It looks weird, but this is how the 64 bit registers are actually handled...!
1636 else if ((offset >= SRCDATA + 0) && (offset <= SRCDATA + 3)
1637 || (offset >= DSTDATA + 0) && (offset <= DSTDATA + 3)
1638 || (offset >= DSTZ + 0) && (offset <= DSTZ + 3)
1639 || (offset >= SRCZINT + 0) && (offset <= SRCZINT + 3)
1640 || (offset >= SRCZFRAC + 0) && (offset <= SRCZFRAC + 3)
1641 || (offset >= PATTERNDATA + 0) && (offset <= PATTERNDATA + 3))
1643 blitter_ram[offset + 4] = data;
1645 else if ((offset >= SRCDATA + 4) && (offset <= SRCDATA + 7)
1646 || (offset >= DSTDATA + 4) && (offset <= DSTDATA + 7)
1647 || (offset >= DSTZ + 4) && (offset <= DSTZ + 7)
1648 || (offset >= SRCZINT + 4) && (offset <= SRCZINT + 7)
1649 || (offset >= SRCZFRAC + 4) && (offset <= SRCZFRAC + 7)
1650 || (offset >= PATTERNDATA + 4) && (offset <= PATTERNDATA + 7))
1652 blitter_ram[offset - 4] = data;
1655 blitter_ram[offset] = data;
1658 void BlitterWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
1660 /*if (((offset & 0xFF) >= PATTERNDATA) && ((offset & 0xFF) < PATTERNDATA + 8))
1662 printf("----> %s wrote %04X to byte %u of PATTERNDATA...\n", whoName[who], data, offset - (0xF02200 + PATTERNDATA));
1666 /* if (offset & 0xFF == A1_PIXEL && data == 14368)
1668 WriteLog("\n1\nA1_PIXEL written by %s (%u)...\n\n\n", whoName[who], data);
1669 extern bool doGPUDis;
1672 if ((offset & 0xFF) == (A1_PIXEL + 2) && data == 14368)
1674 WriteLog("\n2\nA1_PIXEL written by %s (%u)...\n\n\n", whoName[who], data);
1675 extern bool doGPUDis;
1680 BlitterWriteByte(offset + 0, data >> 8, who);
1681 BlitterWriteByte(offset + 1, data & 0xFF, who);
1683 if ((offset & 0xFF) == 0x3A)
1684 // I.e., the second write of 32-bit value--not convinced this is the best way to do this!
1685 // But then again, according to the Jaguar docs, this is correct...!
1686 /*extern int blit_start_log;
1687 extern bool doGPUDis;
1690 WriteLog("BLIT: Blitter started by %s...\n", whoName[who]);
1693 #ifdef USE_ORIGINAL_BLITTER
1694 blitter_blit(GET32(blitter_ram, 0x38));
1696 #ifdef USE_MIDSUMMER_BLITTER
1697 BlitterMidsummer(GET32(blitter_ram, 0x38));
1699 #ifdef USE_MIDSUMMER_BLITTER_MKII
1700 BlitterMidsummer2();
1705 void BlitterWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
1707 /*if (((offset & 0xFF) >= PATTERNDATA) && ((offset & 0xFF) < PATTERNDATA + 8))
1709 printf("------> %s wrote %08X to byte %u of PATTERNDATA...\n", whoName[who], data, offset - (0xF02200 + PATTERNDATA));
1713 /* if ((offset & 0xFF) == A1_PIXEL && (data & 0xFFFF) == 14368)
1715 WriteLog("\n3\nA1_PIXEL written by %s (%u)...\n\n\n", whoName[who], data);
1716 extern bool doGPUDis;
1721 BlitterWriteWord(offset + 0, data >> 16, who);
1722 BlitterWriteWord(offset + 2, data & 0xFFFF, who);
1727 char * opStr[16] = { "LFU_CLEAR", "LFU_NSAND", "LFU_NSAD", "LFU_NOTS", "LFU_SAND", "LFU_NOTD", "LFU_N_SXORD", "LFU_NSORND",
1728 "LFU_SAD", "LFU_XOR", "LFU_D", "LFU_NSORD", "LFU_REPLACE", "LFU_SORND", "LFU_SORD", "LFU_ONE" };
1729 uint32 cmd = GET32(blitter_ram, 0x38);
1730 UINT32 m = (REG(A1_FLAGS) >> 9) & 0x03, e = (REG(A1_FLAGS) >> 11) & 0x0F;
1731 UINT32 a1_width = ((0x04 | m) << e) >> 2;
1732 m = (REG(A2_FLAGS) >> 9) & 0x03, e = (REG(A2_FLAGS) >> 11) & 0x0F;
1733 UINT32 a2_width = ((0x04 | m) << e) >> 2;
1735 WriteLog("Blit!\n");
1736 WriteLog(" COMMAND = %08X\n", cmd);
1737 WriteLog(" a1_base = %08X\n", REG(A1_BASE));
1738 WriteLog(" a1_flags = %08X (%c %c %c %c%c . %c%c%c%c%c%c %c%c%c %c%c%c . %c%c)\n", REG(A1_FLAGS),
1739 (REG(A1_FLAGS) & 0x100000 ? '1' : '0'),
1740 (REG(A1_FLAGS) & 0x080000 ? '1' : '0'),
1741 (REG(A1_FLAGS) & 0x040000 ? '1' : '0'),
1742 (REG(A1_FLAGS) & 0x020000 ? '1' : '0'),
1743 (REG(A1_FLAGS) & 0x010000 ? '1' : '0'),
1744 (REG(A1_FLAGS) & 0x004000 ? '1' : '0'),
1745 (REG(A1_FLAGS) & 0x002000 ? '1' : '0'),
1746 (REG(A1_FLAGS) & 0x001000 ? '1' : '0'),
1747 (REG(A1_FLAGS) & 0x000800 ? '1' : '0'),
1748 (REG(A1_FLAGS) & 0x000400 ? '1' : '0'),
1749 (REG(A1_FLAGS) & 0x000200 ? '1' : '0'),
1750 (REG(A1_FLAGS) & 0x000100 ? '1' : '0'),
1751 (REG(A1_FLAGS) & 0x000080 ? '1' : '0'),
1752 (REG(A1_FLAGS) & 0x000040 ? '1' : '0'),
1753 (REG(A1_FLAGS) & 0x000020 ? '1' : '0'),
1754 (REG(A1_FLAGS) & 0x000010 ? '1' : '0'),
1755 (REG(A1_FLAGS) & 0x000008 ? '1' : '0'),
1756 (REG(A1_FLAGS) & 0x000002 ? '1' : '0'),
1757 (REG(A1_FLAGS) & 0x000001 ? '1' : '0'));
1758 WriteLog(" pitch=%u, pixSz=%u, zOff=%u, width=%u, xCtrl=%u\n",
1759 REG(A1_FLAGS) & 0x00003, (REG(A1_FLAGS) & 0x00038) >> 3,
1760 (REG(A1_FLAGS) & 0x001C0) >> 6, a1_width, (REG(A1_FLAGS) & 0x30000) >> 16);
1761 WriteLog(" a1_clip = %u, %u (%08X)\n", GET16(blitter_ram, A1_CLIP + 2), GET16(blitter_ram, A1_CLIP + 0), GET32(blitter_ram, A1_CLIP));
1762 WriteLog(" a1_pixel = %d, %d (%08X)\n", (int16)GET16(blitter_ram, A1_PIXEL + 2), (int16)GET16(blitter_ram, A1_PIXEL + 0), GET32(blitter_ram, A1_PIXEL));
1763 WriteLog(" a1_step = %d, %d (%08X)\n", (int16)GET16(blitter_ram, A1_STEP + 2), (int16)GET16(blitter_ram, A1_STEP + 0), GET32(blitter_ram, A1_STEP));
1764 WriteLog(" a1_fstep = %u, %u (%08X)\n", GET16(blitter_ram, A1_FSTEP + 2), GET16(blitter_ram, A1_FSTEP + 0), GET32(blitter_ram, A1_FSTEP));
1765 WriteLog(" a1_fpixel= %u, %u (%08X)\n", GET16(blitter_ram, A1_FPIXEL + 2), GET16(blitter_ram, A1_FPIXEL + 0), GET32(blitter_ram, A1_FPIXEL));
1766 WriteLog(" a1_inc = %d, %d (%08X)\n", (int16)GET16(blitter_ram, A1_INC + 2), (int16)GET16(blitter_ram, A1_INC + 0), GET32(blitter_ram, A1_INC));
1767 WriteLog(" a1_finc = %u, %u (%08X)\n", GET16(blitter_ram, A1_FINC + 2), GET16(blitter_ram, A1_FINC + 0), GET32(blitter_ram, A1_FINC));
1769 WriteLog(" a2_base = %08X\n", REG(A2_BASE));
1770 WriteLog(" a2_flags = %08X (%c %c %c %c%c %c %c%c%c%c%c%c %c%c%c %c%c%c . %c%c)\n", REG(A2_FLAGS),
1771 (REG(A2_FLAGS) & 0x100000 ? '1' : '0'),
1772 (REG(A2_FLAGS) & 0x080000 ? '1' : '0'),
1773 (REG(A2_FLAGS) & 0x040000 ? '1' : '0'),
1774 (REG(A2_FLAGS) & 0x020000 ? '1' : '0'),
1775 (REG(A2_FLAGS) & 0x010000 ? '1' : '0'),
1776 (REG(A2_FLAGS) & 0x008000 ? '1' : '0'),
1777 (REG(A2_FLAGS) & 0x004000 ? '1' : '0'),
1778 (REG(A2_FLAGS) & 0x002000 ? '1' : '0'),
1779 (REG(A2_FLAGS) & 0x001000 ? '1' : '0'),
1780 (REG(A2_FLAGS) & 0x000800 ? '1' : '0'),
1781 (REG(A2_FLAGS) & 0x000400 ? '1' : '0'),
1782 (REG(A2_FLAGS) & 0x000200 ? '1' : '0'),
1783 (REG(A2_FLAGS) & 0x000100 ? '1' : '0'),
1784 (REG(A2_FLAGS) & 0x000080 ? '1' : '0'),
1785 (REG(A2_FLAGS) & 0x000040 ? '1' : '0'),
1786 (REG(A2_FLAGS) & 0x000020 ? '1' : '0'),
1787 (REG(A2_FLAGS) & 0x000010 ? '1' : '0'),
1788 (REG(A2_FLAGS) & 0x000008 ? '1' : '0'),
1789 (REG(A2_FLAGS) & 0x000002 ? '1' : '0'),
1790 (REG(A2_FLAGS) & 0x000001 ? '1' : '0'));
1791 WriteLog(" pitch=%u, pixSz=%u, zOff=%u, width=%u, xCtrl=%u\n",
1792 REG(A2_FLAGS) & 0x00003, (REG(A2_FLAGS) & 0x00038) >> 3,
1793 (REG(A2_FLAGS) & 0x001C0) >> 6, a2_width, (REG(A2_FLAGS) & 0x30000) >> 16);
1794 WriteLog(" a2_mask = %u, %u (%08X)\n", GET16(blitter_ram, A2_MASK + 2), GET16(blitter_ram, A2_MASK + 0), GET32(blitter_ram, A2_MASK));
1795 WriteLog(" a2_pixel = %d, %d (%08X)\n", (int16)GET16(blitter_ram, A2_PIXEL + 2), (int16)GET16(blitter_ram, A2_PIXEL + 0), GET32(blitter_ram, A2_PIXEL));
1796 WriteLog(" a2_step = %d, %d (%08X)\n", (int16)GET16(blitter_ram, A2_STEP + 2), (int16)GET16(blitter_ram, A2_STEP + 0), GET32(blitter_ram, A2_STEP));
1798 WriteLog(" count = %d x %d\n", GET16(blitter_ram, PIXLINECOUNTER + 2), GET16(blitter_ram, PIXLINECOUNTER));
1800 WriteLog(" SRCEN = %s\n", (SRCEN ? "1" : "0"));
1801 WriteLog(" SRCENZ = %s\n", (SRCENZ ? "1" : "0"));
1802 WriteLog(" SRCENX = %s\n", (SRCENX ? "1" : "0"));
1803 WriteLog(" DSTEN = %s\n", (DSTEN ? "1" : "0"));
1804 WriteLog(" DSTENZ = %s\n", (DSTENZ ? "1" : "0"));
1805 WriteLog(" DSTWRZ = %s\n", (DSTWRZ ? "1" : "0"));
1806 WriteLog(" CLIPA1 = %s\n", (CLIPA1 ? "1" : "0"));
1807 WriteLog(" UPDA1F = %s\n", (UPDA1F ? "1" : "0"));
1808 WriteLog(" UPDA1 = %s\n", (UPDA1 ? "1" : "0"));
1809 WriteLog(" UPDA2 = %s\n", (UPDA2 ? "1" : "0"));
1810 WriteLog(" DSTA2 = %s\n", (DSTA2 ? "1" : "0"));
1811 WriteLog(" ZOP = %s %s %s\n", (Z_OP_INF ? "<" : ""), (Z_OP_EQU ? "=" : ""), (Z_OP_SUP ? ">" : ""));
1812 WriteLog("--LFUFUNC = %s\n", opStr[(cmd >> 21) & 0x0F]);
1813 WriteLog("| PATDSEL = %s (PD=%08X%08X)\n", (PATDSEL ? "1" : "0"), REG(PATTERNDATA), REG(PATTERNDATA + 4));
1814 WriteLog("--ADDDSEL = %s\n", (ADDDSEL ? "1" : "0"));
1815 WriteLog(" CMPDST = %s\n", (CMPDST ? "1" : "0"));
1816 WriteLog(" BCOMPEN = %s\n", (BCOMPEN ? "1" : "0"));
1817 WriteLog(" DCOMPEN = %s\n", (DCOMPEN ? "1" : "0"));
1818 WriteLog(" TOPBEN = %s\n", (TOPBEN ? "1" : "0"));
1819 WriteLog(" TOPNEN = %s\n", (TOPNEN ? "1" : "0"));
1820 WriteLog(" BKGWREN = %s\n", (BKGWREN ? "1" : "0"));
1821 WriteLog(" GOURD = %s (II=%08X, SD=%08X%08X)\n", (GOURD ? "1" : "0"), REG(INTENSITYINC), REG(SRCDATA), REG(SRCDATA + 4));
1822 WriteLog(" GOURZ = %s (ZI=%08X, ZD=%08X%08X, SZ1=%08X%08X, SZ2=%08X%08X)\n", (GOURZ ? "1" : "0"), REG(ZINC), REG(DSTZ), REG(DSTZ + 4),
1823 REG(SRCZINT), REG(SRCZINT + 4), REG(SRCZFRAC), REG(SRCZFRAC + 4));
1824 WriteLog(" SRCSHADE = %s\n", (SRCSHADE ? "1" : "0"));
1828 #ifdef USE_MIDSUMMER_BLITTER
1830 // Here's an attempt to write a blitter that conforms to the Midsummer specs--since
1831 // it's supposedly backwards compatible, it should work well...
1833 //#define LOG_BLITTER_MEMORY_ACCESSES
1835 #define DATINIT (false)
1836 #define TXTEXT (false)
1837 #define POLYGON (false)
1839 void BlitterMidsummer(uint32 cmd)
1841 uint32 outer_loop, inner_loop, a1_addr, a2_addr;
1842 int32 a1_x, a1_y, a2_x, a2_y, a1_width, a2_width;
1843 uint8 a1_phrase_mode, a2_phrase_mode;
1845 a1_addr = REG(A1_BASE) & 0xFFFFFFF8;
1846 a2_addr = REG(A2_BASE) & 0xFFFFFFF8;
1847 a1_x = (REG(A1_PIXEL) << 16) | (REG(A1_FPIXEL) & 0xFFFF);
1848 a1_y = (REG(A1_PIXEL) & 0xFFFF0000) | (REG(A1_FPIXEL) >> 16);
1849 UINT32 m = (REG(A1_FLAGS) >> 9) & 0x03, e = (REG(A1_FLAGS) >> 11) & 0x0F;
1850 a1_width = ((0x04 | m) << e) >> 2;//*/
1851 a2_x = (REG(A2_PIXEL) & 0x0000FFFF) << 16;
1852 a2_y = (REG(A2_PIXEL) & 0xFFFF0000);
1853 m = (REG(A2_FLAGS) >> 9) & 0x03, e = (REG(A2_FLAGS) >> 11) & 0x0F;
1854 a2_width = ((0x04 | m) << e) >> 2;//*/
1856 a1_phrase_mode = a2_phrase_mode = 0;
1858 if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 0)
1861 if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 0)
1864 #define INNER0 (inner_loop == 0)
1865 #define OUTER0 (outer_loop == 0)
1867 // $01800005 has SRCENX, may have to investigate further...
1868 // $00011008 has GOURD & DSTEN.
1869 // $41802F41 has SRCSHADE, CLIPA1
1870 /*bool logBlit = false;
1871 if (cmd != 0x00010200 && cmd != 0x01800001 && cmd != 0x01800005
1872 && cmd != 0x00011008 && cmd !=0x41802F41)
1878 uint64 srcData = GET64(blitter_ram, SRCDATA), srcXtraData,
1879 dstData = GET64(blitter_ram, DSTDATA), writeData;
1880 uint32 srcAddr, dstAddr;
1881 uint8 bitCount, a1PixelSize, a2PixelSize;
1883 // JTRM says phrase mode only works for 8BPP or higher, so let's try this...
1884 uint32 phraseOffset[8] = { 8, 8, 8, 8, 4, 2, 0, 0 };
1885 uint8 pixelShift[8] = { 3, 2, 1, 0, 1, 2, 0, 0 };
1887 a1PixelSize = (blitter_ram[A1_FLAGS + 3] >> 3) & 0x07;
1888 a2PixelSize = (blitter_ram[A2_FLAGS + 3] >> 3) & 0x07;
1890 outer_loop = GET16(blitter_ram, PIXLINECOUNTER + 0);
1892 if (outer_loop == 0)
1893 outer_loop = 0x10000;
1895 // We just list the states here and jump from state to state in order to
1896 // keep things somewhat clear. Optimization/cleanups later.
1898 //idle: // Blitter is idle, and will not perform any bus activity
1900 idle Blitter is off the bus, and no activity takes place.
1901 if GO if DATINIT goto init_if
1910 inner Inner loop is active, read and write cycles are performed
1912 inner: // Run inner loop state machine (asserts step from its idle state)
1913 inner_loop = GET16(blitter_ram, PIXLINECOUNTER + 2);
1915 if (inner_loop == 0)
1916 inner_loop = 0x10000;
1919 ------------------------------
1920 idle: Inactive, blitter is idle or passing round outer loop
1921 idle Another state in the outer loop is active. No bus transfers are performed.
1923 if SRCENX goto sreadx
1924 else if TXTEXT goto txtread
1925 else if SRCEN goto sread
1926 else if DSTEN goto dread
1927 else if DSTENZ goto dzread
1944 sreadx Extra source data read at the start of an inner loop pass.
1946 if SRCENZ goto szreadx
1947 else if TXTEXT goto txtread
1948 else if SRCEN goto sread
1949 else if DSTEN goto dread
1950 else if DSTENZ goto dzread
1953 sreadx: // Extra source data read
1968 szreadx Extra source Z read as the start of an inner loop pass.
1970 if TXTEXT goto txtread
1973 szreadx: // Extra source Z read
1980 txtread Read texture data from external memory. This state is only used for external texture.
1981 TEXTEXT is the condition TEXTMODE=1.
1984 else if DSTEN goto dread
1985 else if DSTENZ goto dzread
1988 txtread: // Read external texture data
1999 sread Source data read.
2001 if SRCENZ goto szread
2002 else if DSTEN goto dread
2003 else if DSTENZ goto dzread
2006 sread: // Source data read
2007 //The JTRM doesn't really specify the internal structure of the source data read, but I would
2008 //imagine that if it's in phrase mode that it starts by reading the phrase that the window is
2009 //pointing at. Likewise, the pixel (if in BPP 1, 2 & 4, chopped) otherwise. It probably still
2010 //transfers an entire phrase even in pixel mode.
2011 //Odd thought: Does it expand, e.g., 1 BPP pixels into 32 BPP internally? Hmm...
2014 a1_addr = REG(A1_BASE) & 0xFFFFFFF8;
2015 a2_addr = REG(A2_BASE) & 0xFFFFFFF8;
2016 a1_zoffs = (REG(A1_FLAGS) >> 6) & 7;
2017 a2_zoffs = (REG(A2_FLAGS) >> 6) & 7;
2018 xadd_a1_control = (REG(A1_FLAGS) >> 16) & 0x03;
2019 xadd_a2_control = (REG(A2_FLAGS) >> 16) & 0x03;
2020 a1_pitch = pitchValue[(REG(A1_FLAGS) & 0x03)];
2021 a2_pitch = pitchValue[(REG(A2_FLAGS) & 0x03)];
2022 n_pixels = REG(PIXLINECOUNTER) & 0xFFFF;
2023 n_lines = (REG(PIXLINECOUNTER) >> 16) & 0xFFFF;
2024 a1_x = (REG(A1_PIXEL) << 16) | (REG(A1_FPIXEL) & 0xFFFF);
2025 a1_y = (REG(A1_PIXEL) & 0xFFFF0000) | (REG(A1_FPIXEL) >> 16);
2026 a2_psize = 1 << ((REG(A2_FLAGS) >> 3) & 0x07);
2027 a1_psize = 1 << ((REG(A1_FLAGS) >> 3) & 0x07);
2030 a1_width = ((0x04 | m) << e) >> 2;
2031 a2_width = ((0x04 | m) << e) >> 2;
2033 // write values back to registers
2034 WREG(A1_PIXEL, (a1_y & 0xFFFF0000) | ((a1_x >> 16) & 0xFFFF));
2035 WREG(A1_FPIXEL, (a1_y << 16) | (a1_x & 0xFFFF));
2036 WREG(A2_PIXEL, (a2_y & 0xFFFF0000) | ((a2_x >> 16) & 0xFFFF));
2038 // Calculate the address to be read...
2040 //Need to fix phrase mode calcs here, since they should *step* by eight, not mulitply.
2041 //Also, need to fix various differing BPP modes here, since offset won't be correct except
2042 //for 8BPP. !!! FIX !!!
2043 srcAddr = (DSTA2 ? a1_addr : a2_addr);
2045 /* if ((DSTA2 ? a1_phrase_mode : a2_phrase_mode) == 1)
2047 srcAddr += (((DSTA2 ? a1_x : a2_x) >> 16)
2048 + (((DSTA2 ? a1_y : a2_y) >> 16) * (DSTA2 ? a1_width : a2_width)));
2052 // uint32 pixAddr = ((DSTA2 ? a1_x : a2_x) >> 16)
2053 // + (((DSTA2 ? a1_y : a2_y) >> 16) * (DSTA2 ? a1_width : a2_width));
2054 int32 pixAddr = (int16)((DSTA2 ? a1_x : a2_x) >> 16)
2055 + ((int16)((DSTA2 ? a1_y : a2_y) >> 16) * (DSTA2 ? a1_width : a2_width));
2057 if ((DSTA2 ? a1PixelSize : a2PixelSize) < 3)
2058 pixAddr >>= pixelShift[(DSTA2 ? a1PixelSize : a2PixelSize)];
2059 else if ((DSTA2 ? a1PixelSize : a2PixelSize) > 3)
2060 pixAddr <<= pixelShift[(DSTA2 ? a1PixelSize : a2PixelSize)];
2067 if ((DSTA2 ? a1_phrase_mode : a2_phrase_mode) == 1)
2069 srcData = ((uint64)JaguarReadLong(srcAddr, BLITTER) << 32)
2070 | (uint64)JaguarReadLong(srcAddr + 4, BLITTER);
2074 //1,2,&4BPP are wrong here... !!! FIX !!!
2075 if ((DSTA2 ? a1PixelSize : a2PixelSize) == 0) // 1 BPP
2076 srcData = JaguarReadByte(srcAddr, BLITTER);
2077 if ((DSTA2 ? a1PixelSize : a2PixelSize) == 1) // 2 BPP
2078 srcData = JaguarReadByte(srcAddr, BLITTER);
2079 if ((DSTA2 ? a1PixelSize : a2PixelSize) == 2) // 4 BPP
2080 srcData = JaguarReadByte(srcAddr, BLITTER);
2081 if ((DSTA2 ? a1PixelSize : a2PixelSize) == 3) // 8 BPP
2082 srcData = JaguarReadByte(srcAddr, BLITTER);
2083 if ((DSTA2 ? a1PixelSize : a2PixelSize) == 4) // 16 BPP
2084 srcData = JaguarReadWord(srcAddr, BLITTER);
2085 if ((DSTA2 ? a1PixelSize : a2PixelSize) == 5) // 32 BPP
2086 srcData = JaguarReadLong(srcAddr, BLITTER);
2089 #ifdef LOG_BLITTER_MEMORY_ACCESSES
2091 WriteLog("BLITTER: srcAddr=%08X, srcData=%08X %08X\n", srcAddr, (uint32)(srcData >> 32), (uint32)(srcData & 0xFFFFFFFF));
2103 szread: // Source Z read
2105 szread Source Z read.
2108 else if DSTENZ goto dzread
2118 dread: // Destination data read
2120 dread Destination data read.
2122 if DSTENZ goto dzread
2125 // Calculate the destination address to be read...
2127 //Need to fix phrase mode calcs here, since they should *step* by eight, not mulitply.
2128 //Also, need to fix various differing BPP modes here, since offset won't be correct except
2129 //for 8BPP. !!! FIX !!!
2130 dstAddr = (DSTA2 ? a2_addr : a1_addr);
2133 // uint32 pixAddr = ((DSTA2 ? a2_x : a1_x) >> 16)
2134 // + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width));
2135 int32 pixAddr = (int16)((DSTA2 ? a2_x : a1_x) >> 16)
2136 + ((int16)((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width));
2138 if ((DSTA2 ? a2PixelSize : a1PixelSize) < 3)
2139 pixAddr >>= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)];
2140 else if ((DSTA2 ? a2PixelSize : a1PixelSize) > 3)
2141 pixAddr <<= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)];
2148 if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1)
2150 dstData = ((uint64)JaguarReadLong(srcAddr, BLITTER) << 32)
2151 | (uint64)JaguarReadLong(srcAddr + 4, BLITTER);
2155 //1,2,&4BPP are wrong here... !!! FIX !!!
2156 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 0) // 1 BPP
2157 dstData = JaguarReadByte(dstAddr, BLITTER);
2158 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 1) // 2 BPP
2159 dstData = JaguarReadByte(dstAddr, BLITTER);
2160 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 2) // 4 BPP
2161 dstData = JaguarReadByte(dstAddr, BLITTER);
2162 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 3) // 8 BPP
2163 dstData = JaguarReadByte(dstAddr, BLITTER);
2164 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 4) // 16 BPP
2165 dstData = JaguarReadWord(dstAddr, BLITTER);
2166 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 5) // 32 BPP
2167 dstData = JaguarReadLong(dstAddr, BLITTER);
2170 #ifdef LOG_BLITTER_MEMORY_ACCESSES
2172 WriteLog("BLITTER (dread): dstAddr=%08X, dstData=%08X %08X\n", dstAddr, (uint32)(dstData >> 32), (uint32)(dstData & 0xFFFFFFFF));
2180 dzread: // Destination Z read
2182 dzread Destination Z read.
2187 dwrite: // Destination data write
2189 dwrite Destination write. Every pass round the inner loop must go through this state..
2191 if DSTWRZ goto dzwrite
2192 else if INNER0 goto idle
2193 else if TXTEXT goto txtread
2194 else if SRCEN goto sread
2195 else if DSTEN goto dread
2196 else if DSTENZ goto dzread
2205 a1_xadd = 1.000000 (phrase=0)
2214 a2_xadd = 1.000000 (phrase=1)
2218 a2_mask_x= 0xFFFFFFFF
2219 a2_mask_y= 0xFFFFFFFF
2229 --LFUFUNC = LFU_CLEAR
2230 | PATDSEL = 1 (PD=77C7 7700 7700 7700)
2232 GOURD = 1 (II=00FC 1A00, SD=FF00 0000 0000 0000)
2235 //Still need to do CLIPA1 and SRCSHADE and GOURD and GOURZ...
2237 // Check clipping...
2241 uint16 x = a1_x >> 16, y = a1_y >> 16;
2243 if (x >= GET16(blitter_ram, A1_CLIP + 2) || y >= GET16(blitter_ram, A1_CLIP))
2247 // Figure out what gets written...
2251 writeData = GET64(blitter_ram, PATTERNDATA);
2252 //GOURD works properly only in 16BPP mode...
2253 //SRCDATA holds the intensity fractions...
2254 //Does GOURD get calc'ed here or somewhere else???
2255 //Temporary testing kludge...
2257 // writeData >>= 48;
2258 // writeData = 0xFF88;
2259 //OK, it's not writing an entire strip of pixels... Why?
2260 //bad incrementing, that's why!
2264 // Apparently this only works with 16-bit pixels. Not sure if it works in phrase mode either.
2265 //Also, take TOPBEN & TOPNEN into account here as well...
2266 writeData = srcData + dstData;
2268 else // LFUFUNC is the default...
2273 writeData |= ~srcData & ~dstData;
2275 writeData |= ~srcData & dstData;
2277 writeData |= srcData & ~dstData;
2279 writeData |= srcData & dstData;
2282 // Calculate the address to be written...
2284 dstAddr = (DSTA2 ? a2_addr : a1_addr);
2286 /* if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1)
2288 //both of these calculate the wrong address because they don't take into account
2290 dstAddr += ((DSTA2 ? a2_x : a1_x) >> 16)
2291 + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width));
2295 /* dstAddr += ((DSTA2 ? a2_x : a1_x) >> 16)
2296 + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width));*/
2297 // uint32 pixAddr = ((DSTA2 ? a2_x : a1_x) >> 16)
2298 // + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width));
2299 int32 pixAddr = (int16)((DSTA2 ? a2_x : a1_x) >> 16)
2300 + ((int16)((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width));
2302 if ((DSTA2 ? a2PixelSize : a1PixelSize) < 3)
2303 pixAddr >>= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)];
2304 else if ((DSTA2 ? a2PixelSize : a1PixelSize) > 3)
2305 pixAddr <<= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)];
2312 if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1)
2314 JaguarWriteLong(dstAddr, writeData >> 32, BLITTER);
2315 JaguarWriteLong(dstAddr + 4, writeData & 0xFFFFFFFF, BLITTER);
2319 //1,2,&4BPP are wrong here... !!! FIX !!!
2320 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 0) // 1 BPP
2321 JaguarWriteByte(dstAddr, writeData, BLITTER);
2322 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 1) // 2 BPP
2323 JaguarWriteByte(dstAddr, writeData, BLITTER);
2324 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 2) // 4 BPP
2325 JaguarWriteByte(dstAddr, writeData, BLITTER);
2326 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 3) // 8 BPP
2327 JaguarWriteByte(dstAddr, writeData, BLITTER);
2328 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 4) // 16 BPP
2329 JaguarWriteWord(dstAddr, writeData, BLITTER);
2330 if ((DSTA2 ? a2PixelSize : a1PixelSize) == 5) // 32 BPP
2331 JaguarWriteLong(dstAddr, writeData, BLITTER);
2334 #ifdef LOG_BLITTER_MEMORY_ACCESSES
2336 WriteLog("BLITTER: dstAddr=%08X, writeData=%08X %08X\n", dstAddr, (uint32)(writeData >> 32), (uint32)(writeData & 0xFFFFFFFF));
2339 inhibitWrite://Should this go here? or on the other side of the X/Y incrementing?
2340 //Seems OK here... for now.
2342 // Do funky X/Y incrementation here as well... !!! FIX !!!
2344 // Handle A1 channel stepping
2346 if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 0)
2347 a1_x += phraseOffset[a1PixelSize] << 16;
2348 else if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 1)
2349 a1_x += (blitter_ram[A1_FLAGS + 1] & 0x08 ? -1 << 16 : 1 << 16);
2350 /* else if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 2)
2352 else if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 3)
2354 //Always add the FINC here??? That was the problem with the BIOS screen... So perhaps.
2355 a1_x += GET16(blitter_ram, A1_FINC + 2);
2356 a1_y += GET16(blitter_ram, A1_FINC + 0);
2358 a1_x += GET16(blitter_ram, A1_INC + 2) << 16;
2359 a1_y += GET16(blitter_ram, A1_INC + 0) << 16;
2362 if ((blitter_ram[A1_FLAGS + 1] & 0x04) && (blitter_ram[A1_FLAGS + 1] & 0x03 != 3))
2363 a1_y += (blitter_ram[A1_FLAGS + 1] & 0x10 ? -1 << 16 : 1 << 16);
2365 // Handle A2 channel stepping
2367 if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 0)
2368 a2_x += phraseOffset[a2PixelSize] << 16;
2369 else if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 1)
2370 a2_x += (blitter_ram[A2_FLAGS + 1] & 0x08 ? -1 << 16 : 1 << 16);
2371 /* else if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 2)
2374 if (blitter_ram[A2_FLAGS + 1] & 0x04)
2375 a2_y += (blitter_ram[A2_FLAGS + 1] & 0x10 ? -1 << 16 : 1 << 16);
2377 //Need to fix this so that it subtracts (saturating, of course) the correct number of pixels
2378 //in phrase mode... !!! FIX !!! [DONE]
2379 //Need to fix this so that it counts down the correct item. Does it count the
2380 //source or the destination phrase mode???
2381 //It shouldn't matter, because we *should* end up processing the same amount
2382 //the same number of pixels... Not sure though.
2383 if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1)
2385 if (inner_loop < phraseOffset[DSTA2 ? a2PixelSize : a1PixelSize])
2388 inner_loop -= phraseOffset[DSTA2 ? a2PixelSize : a1PixelSize];
2409 dzwrite: // Destination Z write
2411 dzwrite Destination Z write.
2414 else if TXTEXT goto txtread
2415 else if SRCEN goto sread
2416 else if DSTEN goto dread
2417 else if DSTENZ goto dzread
2434 ------------------------------
2435 if INDONE if OUTER0 goto idle
2436 else if UPDA1F goto a1fupdate
2437 else if UPDA1 goto a1update
2438 else if GOURZ.POLYGON goto zfupdate
2439 else if UPDA2 goto a2update
2440 else if DATINIT goto init_if
2453 //kill this, for now...
2454 // else if (GOURZ.POLYGON)
2463 a1fupdate: // Update A1 pointer fractions and more (see below)
2465 a1fupdate A1 step fraction is added to A1 pointer fraction
2466 POLYGON true: A1 step delta X and Y fraction parts are added to the A1
2467 step X and Y fraction parts (the value prior to this add is used for
2468 the step to pointer add).
2469 POLYGON true: inner count step fraction is added to the inner count
2471 POLYGON.GOURD true: the I fraction step is added to the computed
2472 intensity fraction parts +
2473 POLYGON.GOURD true: the I fraction step delta is added to the I
2478 #define A1_PIXEL ((UINT32)0x0C) // Integer part of the pixel (Y.i and X.i)
2479 #define A1_STEP ((UINT32)0x10) // Integer part of the step
2480 #define A1_FSTEP ((UINT32)0x14) // Fractional part of the step
2481 #define A1_FPIXEL ((UINT32)0x18) // Fractional part of the pixel (Y.f and X.f)
2484 // This is all kinda murky. All we have are the Midsummer docs to give us any guidance,
2485 // and it's incomplete or filled with errors (like above). Aarrrgggghhhhh!
2487 //This isn't right. Is it? I don't think the fractional parts are signed...
2488 // a1_x += (int32)((int16)GET16(blitter_ram, A1_FSTEP + 2));
2489 // a1_y += (int32)((int16)GET16(blitter_ram, A1_FSTEP + 0));
2490 a1_x += GET16(blitter_ram, A1_FSTEP + 2);
2491 a1_y += GET16(blitter_ram, A1_FSTEP + 0);
2495 a1update: // Update A1 pointer integers
2497 a1update A1 step is added to A1 pointer, with carry from the fractional add
2498 POLYGON true: A1 step delta X and Y integer parts are added to the A1
2499 step X and Y integer parts, with carry from the corresponding
2500 fractional part add (again, the value prior to this add is used for
2501 the step to pointer add).
2502 POLYGON true: inner count step is added to the inner count, with carry
2503 POLYGON.GOURD true: the I step is added to the computed intensities,
2505 POLYGON.GOURD true: the I step delta is added to the I step, with
2506 carry the texture X and Y step delta values are added to the X and Y
2508 if GOURZ.POLYGON goto zfupdate
2509 else if UPDA2 goto a2update
2510 else if DATINIT goto init_if
2513 a1_x += (int32)(GET16(blitter_ram, A1_STEP + 2) << 16);
2514 a1_y += (int32)(GET16(blitter_ram, A1_STEP + 0) << 16);
2517 //kill this, for now...
2518 // if (GOURZ.POLYGON)
2528 zfupdate: // Update computed Z step fractions
2530 zfupdate the Z fraction step is added to the computed Z fraction parts +
2531 the Z fraction step delta is added to the Z fraction step
2536 zupdate: // Update computed Z step integers
2538 zupdate the Z step is added to the computed Zs, with carry +
2539 the Z step delta is added to the Z step, with carry
2540 if UPDA2 goto a2update
2541 else if DATINIT goto init_if
2551 a2update: // Update A2 pointer
2553 a2update A2 step is added to the A2 pointer
2554 if DATINIT goto init_if
2557 a2_x += (int32)(GET16(blitter_ram, A2_STEP + 2) << 16);
2558 a2_y += (int32)(GET16(blitter_ram, A2_STEP + 0) << 16);
2566 init_if: // Initialise intensity fractions and texture X
2568 init_if Initialise the fractional part of the computed intensity fields, from
2569 the increment and step registers. The texture X integer and fractional
2570 parts can also be initialised.
2575 init_ii: // Initialise intensity integers and texture Y
2577 init_ii Initialise the integer part of the computed intensity, and texture Y
2578 integer and fractional parts
2579 if GOURZ goto init_zf
2587 init_zf: // Initialise Z fractions
2589 init_zf Initialise the fractional part of the computed Z fields.
2594 init_zi: // Initialise Z integers
2596 init_zi Initialise the integer part of the computed Z fields.
2603 The outer loop state machine fires off the inner loop, and controls the updating
2604 process between passes through the inner loop.
2606 + -- these functions are irrelevant if the DATINIT function is enabled, which it
2609 All these states will complete in one clock cycle, with the exception of the idle
2610 state, which means the blitter is quiescent; and the inner state, which takes as
2611 long as is required to complete one strip of pixels. It is therefore possible for
2612 the blitter to spend a maximum of nine clock cycles of inactivity between passes
2613 through the inner loop.
2622 Here's a collection of various blits that aren't handled correctly yet...
2624 Spinning cube in Jaguar BIOS opening:
2628 a1_flags = 00033020 (0 0 0 11 . 011000 000 100 . 00)
2629 pitch=0, pixSz=4, zOff=0, width=64, xCtrl=3
2630 a1_clip = 64, 64 (00400040)
2631 a1_pixel = 0, 65534 (FFFE0000)
2632 a1_step = -64, -1 (FFFFFFC0)
2633 a1_fstep = 0, 18161 (46F10000)
2634 a1_fpixel= 32768, 42497 (A6018000)
2635 a1_inc = 1, 0 (00000001)
2636 a1_finc = 0, 1926 (07860000)
2638 a2_flags = 00013820 (0 0 0 01 0 011100 000 100 . 00)
2639 pitch=0, pixSz=4, zOff=0, width=128, xCtrl=1
2640 a2_mask = 0, 0 (00000000)
2641 a2_pixel = 33, 55 (00370021)
2642 a2_step = -64, 1 (0001FFC0)
2656 --LFUFUNC = LFU_REPLACE
2657 | PATDSEL = 0 (PD=0000000000000000)
2665 GOURD = 0 (II=00FCDC80, SD=FF00FF00FF00FF00)
2666 GOURZ = 1 (ZI=00000000, ZD=0000000000000000, SZ1=0000000000000000, SZ2=0000000000000000)
2671 #ifdef USE_MIDSUMMER_BLITTER_MKII
2672 // Here's attempt #2--taken from the Oberon chip specs!
2674 void ADDRGEN(uint32 &, uint32 &, bool, bool,
2675 uint16, uint16, uint32, uint8, uint8, uint8, uint8,
2676 uint16, uint16, uint32, uint8, uint8, uint8, uint8);
2677 void ADDARRAY(uint16 * addq, uint8 daddasel, uint8 daddbsel, uint8 daddmode,
2678 uint64 dstd, uint32 iinc, uint8 initcin[], uint64 initinc, uint16 initpix,
2679 uint32 istep, uint64 patd, uint64 srcd, uint64 srcz1, uint64 srcz2,
2680 uint32 zinc, uint32 zstep);
2681 void ADD16SAT(uint16 &r, uint8 &co, uint16 a, uint16 b, uint8 cin, bool sat, bool eightbit, bool hicinh);
2682 void ADDAMUX(int16 &adda_x, int16 &adda_y, uint8 addasel, int16 a1_step_x, int16 a1_step_y,
2683 int16 a1_stepf_x, int16 a1_stepf_y, int16 a2_step_x, int16 a2_step_y,
2684 int16 a1_inc_x, int16 a1_inc_y, int16 a1_incf_x, int16 a1_incf_y, uint8 adda_xconst,
2685 bool adda_yconst, bool addareg, bool suba_x, bool suba_y);
2686 void ADDBMUX(int16 &addb_x, int16 &addb_y, uint8 addbsel, int16 a1_x, int16 a1_y,
2687 int16 a2_x, int16 a2_y, int16 a1_frac_x, int16 a1_frac_y);
2688 void DATAMUX(int16 &data_x, int16 &data_y, uint32 gpu_din, int16 addq_x, int16 addq_y, bool addqsel);
2689 void ADDRADD(int16 &addq_x, int16 &addq_y, bool a1fracldi,
2690 uint16 adda_x, uint16 adda_y, uint16 addb_x, uint16 addb_y, uint8 modx, bool suba_x, bool suba_y);
2691 void DATA (uint64 &wdata, uint8 &dcomp, uint8 &zcomp, bool &nowrite,
2692 bool big_pix, bool cmpdst, uint8 daddasel, uint8 daddbsel, uint8 daddmode, bool daddq_sel, uint8 data_sel,
2693 uint8 dbinh, uint8 dend, uint8 dstart, uint64 dstd, uint32 iinc, uint8 lfu_func, uint64 patd, bool patdadd,
2694 bool phrase_mode, uint64 srcd, bool srcdread, bool srczread, bool srcz2add, uint8 zmode,
2695 bool bcompen, bool bkgwren, bool dcompen, uint8 icount, uint8 pixsize);
2696 void COMP_CTRL(uint8 &dbinh, bool &nowrite,
2697 bool bcompen, bool big_pix, bool bkgwren, uint8 dcomp, bool dcompen, uint8 icount,
2698 uint8 pixsize, bool phrase_mode, uint8 srcd, uint8 zcomp);
2699 #define VERBOSE_BLITTER_LOGGING
2700 bool logBlit = false;
2702 void BlitterMidsummer2(void)
2704 // Here's what the specs say the state machine does. Note that this can probably be
2705 // greatly simplified (also, it's different from what John has in his Oberon docs):
2706 //Will remove stuff that isn't in Jaguar I once fully described (stuff like texture won't
2707 //be described here at all)...
2709 uint32 cmd = GET32(blitter_ram, COMMAND);
2711 // $01800005 has SRCENX, may have to investigate further...
2712 // $00011008 has GOURD & DSTEN.
2713 // $41802F41 has SRCSHADE, CLIPA1
2717 && cmd != 0x01800001
2718 && cmd != 0x01800005
2719 //Boot ROM ATARI letters:
2720 && cmd != 0x00011008 // DSTEN GOURD PATDSEL
2721 //Boot ROM spinning cube:
2722 && cmd != 0x41802F41 // SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 DSTA2 GOURZ ZMODE=0 LFUFUNC=C SRCSHADE
2724 && cmd != 0x01800E01 // SRCEN UPDA1 UPDA2 DSTA2 LFUFUNC=C
2725 //T2K TEMPEST letters:
2726 && cmd != 0x09800741 // SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 LFUFUNC=C DCOMPEN
2727 //Static letters on Cybermorph intro screen:
2728 && cmd != 0x09800609 // DCOMPEN
2729 //Static pic on title screen:
2730 && cmd != 0x01800601 // SRCEN UPDA1 UPDA2 LFUFUNC=C
2731 //Turning letters on Cybermorph intro screen:
2732 && cmd != 0x09800F41 // SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 DSTA2 LFUFUNC=C DCOMPEN
2733 && cmd != 0x00113078 // DSTEN DSTENZ DSTWRZ CLIP_A1 GOURD GOURZ PATDSEL ZMODE=4
2734 && cmd != 0x09900F39 // SRCEN DSTEN DSTENZ DSTWRZ UPDA1 UPDA1F UPDA2 DSTA2 ZMODE=4 LFUFUNC=C DCOMPEN
2735 && cmd != 0x09800209 // SRCEN DSTEN UPDA1 LFUFUNC=C DCOMPEN
2736 && cmd != 0x00011200 // UPDA1 GOURD PATDSEL
2737 //Start of Hover Strike (clearing screen):
2738 && cmd != 0x00010000 // PATDSEL
2739 //Hover Strike text:
2740 && cmd != 0x1401060C // SRCENX DSTEN UPDA1 UPDA2 PATDSEL BCOMPEN BKGWREN
2744 //printf("logBlit = %s, cmd = %08X\n", (logBlit ? "T" : "F"), cmd);
2747 // Line states passed in via the command register
2749 bool srcen = (SRCEN), srcenx = (SRCENX), srcenz = (SRCENZ),
2750 dsten = (DSTEN), dstenz = (DSTENZ), dstwrz = (DSTWRZ), clip_a1 = (CLIPA1),
2751 upda1 = (UPDA1), upda1f = (UPDA1F), upda2 = (UPDA2), dsta2 = (DSTA2),
2752 gourd = (GOURD), gourz = (GOURZ), topben = (TOPBEN), topnen = (TOPNEN),
2753 patdsel = (PATDSEL), adddsel = (ADDDSEL), cmpdst = (CMPDST), bcompen = (BCOMPEN),
2754 dcompen = (DCOMPEN), bkgwren = (BKGWREN), srcshade = (SRCSHADE);
2756 uint8 zmode = (cmd & 0x01C0000) >> 18, lfufunc = (cmd & 0x1E00000) >> 21;
2757 //Missing: ZMODE, LFUFUNC, BUSHI
2758 //Where to find various lines:
2760 // gourd -> dcontrol, inner, outer, state
2761 // gourz -> dcontrol, inner, outer, state
2762 // cmpdst -> blit, data, datacomp, state
2763 // bcompen -> acontrol, inner, mcontrol, state
2764 // dcompen -> inner, state
2765 // bkgwren -> inner, state
2766 // srcshade -> dcontrol, inner, state
2767 // adddsel -> dcontrol
2768 //NOTE: ADDDSEL takes precedence over PATDSEL, PATDSEL over LFU_FUNC
2769 #ifdef VERBOSE_BLITTER_LOGGING
2772 char zfs[512], lfus[512];
2773 zfs[0] = lfus[0] = 0;
2774 if (dstwrz || dstenz || gourz)
2775 sprintf(zfs, " ZMODE=%X", zmode);
2776 if (!(patdsel || adddsel))
2777 sprintf(lfus, " LFUFUNC=%X", lfufunc);
2778 printf("\nBlit! (CMD = %08X)\nFlags:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", cmd,
2779 (srcen ? " SRCEN" : ""), (srcenx ? " SRCENX" : ""), (srcenz ? " SRCENZ" : ""),
2780 (dsten ? " DSTEN" : ""), (dstenz ? " DSTENZ" : ""), (dstwrz ? " DSTWRZ" : ""),
2781 (clip_a1 ? " CLIP_A1" : ""), (upda1 ? " UPDA1" : ""), (upda1f ? " UPDA1F" : ""),
2782 (upda2 ? " UPDA2" : ""), (dsta2 ? " DSTA2" : ""), (gourd ? " GOURD" : ""),
2783 (gourz ? " GOURZ" : ""), (topben ? " TOPBEN" : ""), (topnen ? " TOPNEN" : ""),
2784 (patdsel ? " PATDSEL" : ""), (adddsel ? " ADDDSEL" : ""), zfs, lfus, (cmpdst ? " CMPDST" : ""),
2785 (bcompen ? " BCOMPEN" : ""), (dcompen ? " DCOMPEN" : ""), (bkgwren ? " BKGWREN" : ""),
2786 (srcshade ? " SRCSHADE" : ""));
2787 printf(" count = %d x %d\n", GET16(blitter_ram, PIXLINECOUNTER + 2), GET16(blitter_ram, PIXLINECOUNTER));
2792 // Lines that don't exist in Jaguar I (and will never be asserted)
2794 bool polygon = false, datinit = false, a1_stepld = false, a2_stepld = false, ext_int = false;
2795 bool istepadd = false, istepfadd = false, finneradd = false, inneradd = false;
2796 bool zstepfadd = false, zstepadd = false;
2798 // Various state lines (initial state--basically the reset state of the FDSYNCs)
2800 bool go = true, idle = true, inner = false, a1fupdate = false, a1update = false,
2801 zfupdate = false, zupdate = false, a2update = false, init_if = false, init_ii = false,
2802 init_zf = false, init_zi = false;
2804 bool outer0 = false, indone = false;
2806 bool idlei, inneri, a1fupdatei, a1updatei, zfupdatei, zupdatei, a2updatei, init_ifi, init_iii,
2809 bool notgzandp = !(gourz && polygon);
2811 // Various registers set up by user
2813 uint16 ocount = GET16(blitter_ram, PIXLINECOUNTER);
2814 uint8 a1_pitch = blitter_ram[A1_FLAGS + 3] & 0x03;
2815 uint8 a2_pitch = blitter_ram[A2_FLAGS + 3] & 0x03;
2816 uint8 a1_pixsize = (blitter_ram[A1_FLAGS + 3] & 0x38) >> 3;
2817 uint8 a2_pixsize = (blitter_ram[A2_FLAGS + 3] & 0x38) >> 3;
2818 uint8 a1_zoffset = (GET16(blitter_ram, A1_FLAGS + 2) >> 6) & 0x07;
2819 uint8 a2_zoffset = (GET16(blitter_ram, A2_FLAGS + 2) >> 6) & 0x07;
2820 uint8 a1_width = (blitter_ram[A1_FLAGS + 2] >> 1) & 0x3F;
2821 uint8 a2_width = (blitter_ram[A2_FLAGS + 2] >> 1) & 0x3F;
2822 bool a2_mask = blitter_ram[A2_FLAGS + 2] & 0x80;
2823 uint8 a1addx = blitter_ram[A1_FLAGS + 1] & 0x03, a2addx = blitter_ram[A2_FLAGS + 1] & 0x03;
2824 bool a1addy = blitter_ram[A1_FLAGS + 1] & 0x04, a2addy = blitter_ram[A2_FLAGS + 1] & 0x04;
2825 bool a1xsign = blitter_ram[A1_FLAGS + 1] & 0x08, a2xsign = blitter_ram[A2_FLAGS + 1] & 0x08;
2826 bool a1ysign = blitter_ram[A1_FLAGS + 1] & 0x10, a2ysign = blitter_ram[A2_FLAGS + 1] & 0x10;
2827 uint32 a1_base = GET32(blitter_ram, A1_BASE) & 0xFFFFFFF8; // Phrase aligned by ignoring bottom 3 bits
2828 uint32 a2_base = GET32(blitter_ram, A2_BASE) & 0xFFFFFFF8;
2830 uint16 a1_win_x = GET16(blitter_ram, A1_CLIP + 2) & 0x7FFF;
2831 uint16 a1_win_y = GET16(blitter_ram, A1_CLIP + 0) & 0x7FFF;
2832 int16 a1_x = (int16)GET16(blitter_ram, A1_PIXEL + 2);
2833 int16 a1_y = (int16)GET16(blitter_ram, A1_PIXEL + 0);
2834 int16 a1_step_x = (int16)GET16(blitter_ram, A1_STEP + 2);
2835 int16 a1_step_y = (int16)GET16(blitter_ram, A1_STEP + 0);
2836 uint16 a1_stepf_x = GET16(blitter_ram, A1_FSTEP + 2);
2837 uint16 a1_stepf_y = GET16(blitter_ram, A1_FSTEP + 0);
2838 uint16 a1_frac_x = GET16(blitter_ram, A1_FPIXEL + 2);
2839 uint16 a1_frac_y = GET16(blitter_ram, A1_FPIXEL + 0);
2840 int16 a1_inc_x = (int16)GET16(blitter_ram, A1_INC + 2);
2841 int16 a1_inc_y = (int16)GET16(blitter_ram, A1_INC + 0);
2842 uint16 a1_incf_x = GET16(blitter_ram, A1_FINC + 2);
2843 uint16 a1_incf_y = GET16(blitter_ram, A1_FINC + 0);
2845 int16 a2_x = (int16)GET16(blitter_ram, A2_PIXEL + 2);
2846 int16 a2_y = (int16)GET16(blitter_ram, A2_PIXEL + 0);
2847 uint16 a2_mask_x = GET16(blitter_ram, A2_MASK + 2);
2848 uint16 a2_mask_y = GET16(blitter_ram, A2_MASK + 0);
2849 int16 a2_step_x = (int16)GET16(blitter_ram, A2_STEP + 2);
2850 int16 a2_step_y = (int16)GET16(blitter_ram, A2_STEP + 0);
2852 uint64 srcd1 = GET64(blitter_ram, SRCDATA);
2854 uint64 dstd = GET64(blitter_ram, DSTDATA);
2855 uint64 patd = GET64(blitter_ram, PATTERNDATA);
2856 uint32 iinc = GET32(blitter_ram, INTENSITYINC);
2857 uint64 srcz1 = GET64(blitter_ram, SRCZINT);
2858 uint64 srcz2 = GET64(blitter_ram, SRCZFRAC);
2859 uint64 dstz = GET64(blitter_ram, DSTZ);
2860 uint32 zinc = GET32(blitter_ram, ZINC);
2861 uint32 collision = GET32(blitter_ram, COLLISIONCTRL);// 0=RESUME, 1=ABORT, 2=STOPEN
2863 uint8 pixsize = (dsta2 ? a2_pixsize : a1_pixsize); // From ACONTROL
2866 //if (cmd == 0x1401060C) patd = 0xFFFFFFFFFFFFFFFFLL;
2867 //if (cmd == 0x1401060C) patd = 0x00000000000000FFLL;
2868 //If it's still not working (bcompen-patd) then see who's writing what to patd and where...
2869 //Still not OK. Check to see who's writing what to where in patd!
2870 //It looks like M68K is writing to the top half of patd... Hmm...
2872 ----> M68K wrote 0000 to byte 15737344 of PATTERNDATA...
2873 --> M68K wrote 00 to byte 0 of PATTERNDATA...
2874 --> M68K wrote 00 to byte 1 of PATTERNDATA...
2875 ----> M68K wrote 00FF to byte 15737346 of PATTERNDATA...
2876 --> M68K wrote 00 to byte 2 of PATTERNDATA...
2877 --> M68K wrote FF to byte 3 of PATTERNDATA...
2878 logBlit = F, cmd = 1401060C
2880 Wren0 := ND6 (wren\[0], gpua\[5], gpua\[6..8], bliten, gpu_memw);
2881 Wren1 := ND6 (wren\[1], gpua[5], gpua\[6..8], bliten, gpu_memw);
2882 Wren2 := ND6 (wren\[2], gpua\[5], gpua[6], gpua\[7..8], bliten, gpu_memw);
2883 Wren3 := ND6 (wren\[3], gpua[5], gpua[6], gpua\[7..8], bliten, gpu_memw);
2886 Dec0 := D38GH (a1baseld, a1flagld, a1winld, a1ptrld, a1stepld, a1stepfld, a1fracld, a1incld, gpua[2..4], wren\[0]);
2888 Dec1 := D38GH (a1incfld, a2baseld, a2flagld, a2maskld, a2ptrldg, a2stepld, cmdldt, countldt, gpua[2..4], wren\[1]);
2890 Dec2 := D38GH (srcd1ldg[0..1], dstdldg[0..1], dstzldg[0..1], srcz1ldg[0..1], gpua[2..4], wren\[2]);
2892 Dec3 := D38GH (srcz2ld[0..1], patdld[0..1], iincld, zincld, stopld, intld[0], gpua[2..4], wren\[3]);
2894 wren[3] is asserted when gpu address bus = 0 011x xx00
2895 patdld[0] -> 0 0110 1000 -> $F02268 (lo 32 bits)
2896 patdld[1] -> 0 0110 1100 -> $F0226C (hi 32 bits)
2898 So... It's reversed! The data organization of the patd register is [low 32][high 32]! !!! FIX !!! [DONE]
2899 And fix all the other 64 bit registers [DONE]
2902 if (cmd == 0x1401060C)
2904 printf("logBlit = %s, cmd = %08X\n", (logBlit ? "T" : "F"), cmd);
2909 a2addy = a1addy; // A2 channel Y add bit is tied to A1's
2911 //if (logBlit && (ocount > 20)) logBlit = false;
2912 #ifdef VERBOSE_BLITTER_LOGGING
2915 printf(" a1_base = %08X, a2_base = %08X\n", a1_base, a2_base);
2916 printf(" a1_x = %04X, a1_y = %04X, a1_frac_x = %04X, a1_frac_y = %04X, a2_x = %04X, a2_y = %04X\n", (uint16)a1_x, (uint16)a1_y, a1_frac_x, a1_frac_y, (uint16)a2_x, (uint16)a2_y);
2917 printf(" a1_step_x = %04X, a1_step_y = %04X, a1_stepf_x = %04X, a1_stepf_y = %04X, a2_step_x = %04X, a2_step_y = %04X\n", (uint16)a1_step_x, (uint16)a1_step_y, a1_stepf_x, a1_stepf_y, (uint16)a2_step_x, (uint16)a2_step_y);
2918 printf(" a1_inc_x = %04X, a1_inc_y = %04X, a1_incf_x = %04X, a1_incf_y = %04X\n", (uint16)a1_inc_x, (uint16)a1_inc_y, a1_incf_x, a1_incf_y);
2919 printf(" a1_win_x = %04X, a1_win_y = %04X, a2_mask_x = %04X, a2_mask_y = %04X\n", a1_win_x, a1_win_y, a2_mask_x, a2_mask_y);
2920 char x_add_str[4][4] = { "phr", "1", "0", "inc" };
2921 printf(" a2_mask=%s a1add=%s%s/%s%s a2add=%s%s/%s%s\n", (a2_mask ? "T" : "F"), (a1xsign ? "-" : "+"), x_add_str[a1addx],
2922 (a1ysign ? "-" : "+"), (a1addy ? "1" : "0"), (a2xsign ? "-" : "+"), x_add_str[a2addx],
2923 (a2ysign ? "-" : "+"), (a2addy ? "1" : "0"));
2924 printf(" a1_pixsize = %u, a2_pixsize = %u\n", a1_pixsize, a2_pixsize);
2925 printf(" srcd=%08X%08X dstd=%08X%08X patd=%08X%08X iinc=%08X\n",
2926 (uint32)(srcd1 >> 32), (uint32)(srcd1 & 0xFFFFFFFF),
2927 (uint32)(dstd >> 32), (uint32)(dstd & 0xFFFFFFFF),
2928 (uint32)(patd >> 32), (uint32)(patd & 0xFFFFFFFF), iinc);
2929 printf(" srcz1=%08X%08X srcz2=%08X%08X dstz=%08X%08X zinc=%08X, coll=%X\n",
2930 (uint32)(srcz1 >> 32), (uint32)(srcz1 & 0xFFFFFFFF),
2931 (uint32)(srcz2 >> 32), (uint32)(srcz2 & 0xFFFFFFFF),
2932 (uint32)(dstz >> 32), (uint32)(dstz & 0xFFFFFFFF), zinc, collision);
2936 // Various state lines set up by user
2938 bool phrase_mode = ((!dsta2 && a1addx == 0) || (dsta2 && a2addx == 0) ? true : false); // From ACONTROL
2939 #ifdef VERBOSE_BLITTER_LOGGING
2942 printf(" Phrase mode is %s\n", (phrase_mode ? "ON" : "off"));
2947 // Stopgap vars to simulate various lines
2949 uint16 a1FracCInX = 0, a1FracCInY = 0;
2955 if ((idle && !go) || (inner && outer0 && indone))
2957 #ifdef VERBOSE_BLITTER_LOGGING
2960 printf(" Entering IDLE state...\n");
2971 // INNER LOOP ACTIVE
2973 Entering DWRITE state... (icount=0000, inc=4)
2974 Entering IDLE_INNER state...
2975 Leaving INNER state... (ocount=00EF)
2976 [in=T a1f=F a1=T zf=F z=F a2=F iif=F iii=F izf=F izi=F]
2977 Entering INNER state...
2979 [in=F a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
2982 if ((idle && go && !datinit)
2983 || (inner && !indone)
2984 || (inner && indone && !outer0 && !upda1f && !upda1 && notgzandp && !upda2 && !datinit)
2985 || (a1update && !upda2 && notgzandp && !datinit)
2986 || (zupdate && !upda2 && !datinit)
2987 || (a2update && !datinit)
2988 || (init_ii && !gourz)
2996 // A1 FRACTION UPDATE
2998 if (inner && indone && !outer0 && upda1f)
3005 // A1 POINTER UPDATE
3008 || (inner && indone && !outer0 && !upda1f && upda1))
3015 // Z FRACTION UPDATE
3017 if ((a1update && gourz && polygon)
3018 || (inner && indone && !outer0 && !upda1f && !upda1 && gourz && polygon))
3034 // A2 POINTER UPDATE
3036 if ((a1update && upda2 && notgzandp)
3037 || (zupdate && upda2)
3038 || (inner && indone && !outer0 && !upda1f && notgzandp && !upda1 && upda2))
3045 // INITIALIZE INTENSITY FRACTION
3047 if ((zupdate && !upda2 && datinit)
3048 || (a1update && !upda2 && datinit && notgzandp)
3049 || (inner && indone && !outer0 && !upda1f && !upda1 && notgzandp && !upda2 && datinit)
3050 || (a2update && datinit)
3051 || (idle && go && datinit))
3058 // INITIALIZE INTENSITY INTEGER
3067 // INITIALIZE Z FRACTION
3069 if (init_ii && gourz)
3076 // INITIALIZE Z INTEGER
3085 // Here we move the fooi into their foo counterparts in order to simulate the moving
3086 // of data into the various FDSYNCs... Each time we loop we simulate one clock cycle...
3090 a1fupdate = a1fupdatei;
3091 a1update = a1updatei;
3092 zfupdate = zfupdatei; // *
3093 zupdate = zupdatei; // *
3094 a2update = a2updatei;
3095 init_if = init_ifi; // *
3096 init_ii = init_iii; // *
3097 init_zf = init_zfi; // *
3098 init_zi = init_zii; // *
3099 // * denotes states that will never assert for Jaguar I
3100 #ifdef VERBOSE_BLITTER_LOGGING
3103 printf(" [in=%c a1f=%c a1=%c zf=%c z=%c a2=%c iif=%c iii=%c izf=%c izi=%c]\n",
3104 (inner ? 'T' : 'F'), (a1fupdate ? 'T' : 'F'), (a1update ? 'T' : 'F'), (zfupdate ? 'T' : 'F'),
3105 (zupdate ? 'T' : 'F'), (a2update ? 'T' : 'F'), (init_if ? 'T' : 'F'), (init_ii ? 'T' : 'F'),
3106 (init_zf ? 'T' : 'F'), (init_zi ? 'T' : 'F'));
3111 // Now, depending on how we want to handle things, we could either put the implementation
3112 // of the various pieces up above, or handle them down below here.
3114 // Let's try postprocessing for now...
3119 #ifdef VERBOSE_BLITTER_LOGGING
3122 printf(" Entering INNER state...\n");
3126 uint16 icount = GET16(blitter_ram, PIXLINECOUNTER + 2);
3127 bool idle_inner = true, step = true, sreadx = false, szreadx = false, sread = false,
3128 szread = false, dread = false, dzread = false, dwrite = false, dzwrite = false;
3129 bool inner0 = false;
3130 bool idle_inneri, sreadxi, szreadxi, sreadi, szreadi, dreadi, dzreadi, dwritei, dzwritei;
3132 // State lines that will never assert in Jaguar I
3134 bool textext = false, txtread = false;
3138 bool sshftld = true; // D flipflop (D -> Q): instart -> sshftld
3139 //NOTE: sshftld probably is only asserted at the beginning of the inner loop. !!! FIX !!!
3141 Blit! (CMD = 01800005)
3142 Flags: SRCEN SRCENX LFUFUNC=C
3144 a1_base = 00037290, a2_base = 000095D0
3145 a1_x = 0000, a1_y = 0000, a2_x = 0002, a2_y = 0000
3146 a1_pixsize = 4, a2_pixsize = 4
3147 srcd=0000000000000000, dstd=0000000000000000, patd=0000000000000000
3149 [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
3150 Entering INNER state...
3151 Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20]
3152 Source extra read address/pix address: 000095D4/0 [0000001C00540038]
3153 Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3154 Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0]
3155 Source read address/pix address: 000095D8/0 [0054003800009814]
3156 Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3157 Entering DWRITE state...
3158 Dest write address/pix address: 00037290/0 [dstart=0 dend=20 pwidth=8 srcshift=0] (icount=026E, inc=4)
3159 Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3160 Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0]
3161 Source read address/pix address: 000095E0/0 [00009968000377C7]
3162 Entering A2_ADD state [a2_x=0008, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3163 Entering DWRITE state...
3164 Dest write address/pix address: 00037298/0 [dstart=0 dend=20 pwidth=8 srcshift=0] (icount=026A, inc=4)
3165 Entering A1_ADD state [a1_x=0004, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3168 // while (!idle_inner)
3173 if ((idle_inner && !step)
3174 || (dzwrite && step && inner0)
3175 || (dwrite && step && !dstwrz && inner0))
3177 #ifdef VERBOSE_BLITTER_LOGGING
3180 printf(" Entering IDLE_INNER state...\n");
3188 idle_inneri = false;
3190 // EXTRA SOURCE DATA READ
3192 if ((idle_inner && step && srcenx)
3193 || (sreadx && !step))
3200 // EXTRA SOURCE ZED READ
3202 if ((sreadx && step && srcenz)
3203 || (szreadx && !step))
3210 // TEXTURE DATA READ (not implemented because not in Jaguar I)
3214 if ((szreadx && step && !textext)
3215 || (sreadx && step && !srcenz && srcen)
3216 || (idle_inner && step && !srcenx && !textext && srcen)
3217 || (dzwrite && step && !inner0 && !textext && srcen)
3218 || (dwrite && step && !dstwrz && !inner0 && !textext && srcen)
3219 || (txtread && step && srcen)
3220 || (sread && !step))
3229 if ((sread && step && srcenz)
3230 || (szread && !step))
3237 // DESTINATION DATA READ
3239 if ((szread && step && dsten)
3240 || (sread && step && !srcenz && dsten)
3241 || (sreadx && step && !srcenz && !textext && !srcen && dsten)
3242 || (idle_inner && step && !srcenx && !textext && !srcen && dsten)
3243 || (dzwrite && step && !inner0 && !textext && !srcen && dsten)
3244 || (dwrite && step && !dstwrz && !inner0 && !textext && !srcen && dsten)
3245 || (txtread && step && !srcen && dsten)
3246 || (dread && !step))
3253 // DESTINATION ZED READ
3255 if ((dread && step && dstenz)
3256 || (szread && step && !dsten && dstenz)
3257 || (sread && step && !srcenz && !dsten && dstenz)
3258 || (sreadx && step && !srcenz && !textext && !srcen && !dsten && dstenz)
3259 || (idle_inner && step && !srcenx && !textext && !srcen && !dsten && dstenz)
3260 || (dzwrite && step && !inner0 && !textext && !srcen && !dsten && dstenz)
3261 || (dwrite && step && !dstwrz && !inner0 && !textext && !srcen && !dsten && dstenz)
3262 || (txtread && step && !srcen && !dsten && dstenz)
3263 || (dzread && !step))
3270 // DESTINATION DATA WRITE
3272 if ((dzread && step)
3273 || (dread && step && !dstenz)
3274 || (szread && step && !dsten && !dstenz)
3275 || (sread && step && !srcenz && !dsten && !dstenz)
3276 || (txtread && step && !srcen && !dsten && !dstenz)
3277 || (sreadx && step && !srcenz && !textext && !srcen && !dsten && !dstenz)
3278 || (idle_inner && step && !srcenx && !textext && !srcen && !dsten && !dstenz)
3279 || (dzwrite && step && !inner0 && !textext && !srcen && !dsten && !dstenz)
3280 || (dwrite && step && !dstwrz && !inner0 && !textext && !srcen && !dsten && !dstenz)
3281 || (dwrite && !step))
3288 // DESTINATION ZED WRITE
3290 if ((dzwrite && !step)
3291 || (dwrite && step && dstwrz))
3298 //Kludge: A QnD way to make sure that sshftld is asserted only for the first
3299 // cycle of the inner loop...
3300 sshftld = idle_inner;
3302 // Here we move the fooi into their foo counterparts in order to simulate the moving
3303 // of data into the various FDSYNCs... Each time we loop we simulate one clock cycle...
3305 idle_inner = idle_inneri;
3315 // Here's a few more decodes--not sure if they're supposed to go here or not...
3317 bool srca_addi = (sreadxi && !srcenz) || (sreadi && !srcenz) || szreadxi || szreadi;
3319 bool dsta_addi = (dwritei && !dstwrz) || dzwritei;
3321 bool gensrc = sreadxi || szreadxi || sreadi || szreadi;
3322 bool gendst = dreadi || szreadi || dwritei || dzwritei;
3323 bool gena2i = (gensrc && !dsta2) || (gendst && dsta2);
3325 bool zaddr = szreadx || szread || dzread || dzwrite;
3327 // Some stuff from MCONTROL.NET--not sure if this is the correct use of this decode or not...
3328 /*Fontread\ := OND1 (fontread\, sread[1], sreadx[1], bcompen);
3329 Fontread := INV1 (fontread, fontread\);
3330 Justt := NAN3 (justt, fontread\, phrase_mode, tactive\);
3331 Justify := TS (justify, justt, busen);*/
3332 bool fontread = (sread || sreadx) && bcompen;
3333 bool justify = !(!fontread && phrase_mode /*&& tactive*/);
3335 /* Generate inner loop update enables */
3337 A1_addi := MX2 (a1_addi, dsta_addi, srca_addi, dsta2);
3338 A2_addi := MX2 (a2_addi, srca_addi, dsta_addi, dsta2);
3339 A1_add := FD1 (a1_add, a1_add\, a1_addi, clk);
3340 A2_add := FD1 (a2_add, a2_add\, a2_addi, clk);
3341 A2_addb := BUF1 (a2_addb, a2_add);
3343 bool a1_add = (dsta2 ? srca_addi : dsta_addi);
3344 bool a2_add = (dsta2 ? dsta_addi : srca_addi);
3346 /* Address adder input A register selection
3347 000 A1 step integer part
3348 001 A1 step fraction part
3349 010 A1 increment integer part
3350 011 A1 increment fraction part
3354 bit 1 = /a2update . (a1_add . a1addx[0..1])
3355 bit 0 = /a2update . ( a1fupdate
3356 + a1_add . atick[0] . a1addx[0..1])
3357 The /a2update term on bits 0 and 1 is redundant.
3358 Now look-ahead based
3360 uint8 addasel = (a1fupdate || (a1_add && a1addx == 3) ? 0x01 : 0x00);
3361 addasel |= (a1_add && a1addx == 3 ? 0x02 : 0x00);
3362 addasel |= (a2update ? 0x04 : 0x00);
3363 /* Address adder input A X constant selection
3364 adda_xconst[0..2] generate a power of 2 in the range 1-64 or all
3365 zeroes when they are all 1
3366 Remember - these are pixels, so to add one phrase the pixel size
3367 has to be taken into account to get the appropriate value.
3369 if a1addx[0..1] are 00 set 6 - pixel size
3370 if a1addx[0..1] are 01 set the value 000
3371 if a1addx[0..1] are 10 set the value 111
3373 JLH: Also, 11 will likewise set the value to 111
3375 uint8 a1_xconst = 6 - a1_pixsize, a2_xconst = 6 - a2_pixsize;
3379 else if (a1addx & 0x02)
3384 else if (a2addx & 0x02)
3387 uint8 adda_xconst = (a2_add ? a2_xconst : a1_xconst);
3388 /* Address adder input A Y constant selection
3389 22 June 94 - This was erroneous, because only the a1addy bit was reflected here.
3390 Therefore, the selection has to be controlled by a bug fix bit.
3391 JLH: Bug fix bit in Jaguar II--not in Jaguar I!
3393 bool adda_yconst = a1addy;
3394 /* Address adder input A register versus constant selection
3395 given by a1_add . a1addx[0..1]
3398 + a2_add . a2addx[0..1]
3401 bool addareg = ((a1_add && a1addx == 3) || a1update || a1fupdate
3402 || (a2_add && a2addx == 3) || a2update ? true : false);
3403 /* The adders can be put into subtract mode in add pixel size
3404 mode when the corresponding flags are set */
3405 bool suba_x = ((a1_add && a1xsign && a1addx == 1) || (a2_add && a2xsign && a2addx == 1) ? true : false);
3406 bool suba_y = ((a1_add && a1addy && a1ysign) || (a2_add && a2addy && a2ysign) ? true : false);
3407 /* Address adder input B selection
3414 + (a1_add . atick[0] . a1addx[0..1])
3415 + a1fupdate . a1_stepld
3416 + a1update . a1_stepld
3417 + a2update . a2_stepld
3418 Bit 0 = a2update + a2_add
3419 + a1fupdate . a1_stepld
3420 + a1update . a1_stepld
3421 + a2update . a2_stepld
3423 uint8 addbsel = (a2update || a2_add || (a1fupdate && a1_stepld)
3424 || (a1update && a1_stepld) || (a2update && a2_stepld) ? 0x01 : 0x00);
3425 addbsel |= (a1fupdate || (a1_add && a1addx == 3) || (a1fupdate && a1_stepld)
3426 || (a1update && a1_stepld) || (a2update && a2_stepld) ? 0x02 : 0x00);
3428 /* The modulo bits are used to align X onto a phrase boundary when
3429 it is being updated by one phrase
3436 Masking is enabled for a1 when a1addx[0..1] is 00, and the value
3437 is 6 - the pixel size (again!)
3439 uint8 maska1 = (a1_add && a1addx == 0 ? 6 - a1_pixsize : 0);
3440 uint8 maska2 = (a2_add && a2addx == 0 ? 6 - a2_pixsize : 0);
3441 uint8 modx = (a2_add ? maska2 : maska1);
3442 /* Generate load strobes for the increment updates */
3444 /*A1pldt := NAN2 (a1pldt, atick[1], a1_add);
3445 A1ptrldi := NAN2 (a1ptrldi, a1update\, a1pldt);
3447 A1fldt := NAN4 (a1fldt, atick[0], a1_add, a1addx[0..1]);
3448 A1fracldi := NAN2 (a1fracldi, a1fupdate\, a1fldt);
3450 A2pldt := NAN2 (a2pldt, atick[1], a2_add);
3451 A2ptrldi := NAN2 (a2ptrldi, a2update\, a2pldt);*/
3452 bool a1fracldi = a1fupdate || (a1_add && a1addx == 3);
3454 // Some more from DCONTROL...
3455 // atick[] just MAY be important here! We're assuming it's true and dropping the term...
3456 // That will probably screw up some of the lower terms that seem to rely on the timing of it...
3457 #warning srcdreadd is not properly initialized!
3458 bool srcdreadd = false; // Set in INNER.NET
3459 //Shadeadd\ := NAN2H (shadeadd\, dwrite, srcshade);
3460 //Shadeadd := INV2 (shadeadd, shadeadd\);
3461 bool shadeadd = dwrite && srcshade;
3462 /* Data adder control, input A selection
3463 000 Destination data
3464 001 Initialiser pixel value
3465 100 Source data - computed intensity fraction
3466 101 Pattern data - computed intensity
3467 110 Source zed 1 - computed zed
3468 111 Source zed 2 - computed zed fraction
3470 Bit 0 = dwrite . gourd . atick[1]
3471 + dzwrite . gourz . atick[0]
3474 + init_if + init_ii + init_zf + init_zi
3475 Bit 1 = dzwrite . gourz . (atick[0] + atick[1])
3478 Bit 2 = (gourd + gourz) . /(init_if + init_ii + init_zf + init_zi)
3481 uint8 daddasel = ((dwrite && gourd) || (dzwrite && gourz) || istepadd || zstepfadd
3482 || init_if || init_ii || init_zf || init_zi ? 0x01 : 0x00);
3483 daddasel |= ((dzwrite && gourz) || zstepadd || zstepfadd ? 0x02 : 0x00);
3484 daddasel |= (((gourd || gourz) && !(init_if || init_ii || init_zf || init_zi))
3485 || (dwrite && srcshade) ? 0x04 : 0x00);
3486 /* Data adder control, input B selection
3488 0001 Data initialiser increment
3489 0100 Bottom 16 bits of I increment repeated four times
3490 0101 Top 16 bits of I increment repeated four times
3491 0110 Bottom 16 bits of Z increment repeated four times
3492 0111 Top 16 bits of Z increment repeated four times
3493 1100 Bottom 16 bits of I step repeated four times
3494 1101 Top 16 bits of I step repeated four times
3495 1110 Bottom 16 bits of Z step repeated four times
3496 1111 Top 16 bits of Z step repeated four times
3498 Bit 0 = dwrite . gourd . atick[1]
3499 + dzwrite . gourz . atick[1]
3503 + init_if + init_ii + init_zf + init_zi
3504 Bit 1 = dzwrite . gourz . (atick[0] + atick[1])
3507 Bit 2 = dwrite . gourd . (atick[0] + atick[1])
3508 + dzwrite . gourz . (atick[0] + atick[1])
3510 + istepadd + istepfadd + zstepadd + zstepfadd
3511 Bit 3 = istepadd + istepfadd + zstepadd + zstepfadd
3513 uint8 daddbsel = ((dwrite && gourd) || (dzwrite && gourz) || (dwrite && srcshade)
3514 || istepadd || zstepadd || init_if || init_ii || init_zf || init_zi ? 0x01 : 0x00);
3515 daddbsel |= ((dzwrite && gourz) || zstepadd || zstepfadd ? 0x02 : 0x00);
3516 daddbsel |= ((dwrite && gourd) || (dzwrite && gourz) || (dwrite && srcshade)
3517 || istepadd || istepfadd || zstepadd || zstepfadd ? 0x04 : 0x00);
3518 daddbsel |= (istepadd && istepfadd && zstepadd && zstepfadd ? 0x08 : 0x00);
3519 /* Data adder mode control
3520 000 16-bit normal add
3521 001 16-bit saturating add with carry
3522 010 8-bit saturating add with carry, carry into top byte is
3524 011 8-bit saturating add with carry, carry into top byte and
3525 between top nybbles is inhibited (CRY)
3526 100 16-bit normal add with carry
3527 101 16-bit saturating add
3528 110 8-bit saturating add, carry into top byte is inhibited
3529 111 8-bit saturating add, carry into top byte and between top
3530 nybbles is inhibited
3532 The first five are used for Gouraud calculations, the latter three
3533 for adding source and destination data
3535 Bit 0 = dzwrite . gourz . atick[1]
3536 + dwrite . gourd . atick[1] . /topnen . /topben . /ext_int
3537 + dwrite . gourd . atick[1] . topnen . topben . /ext_int
3539 + istepadd . /topnen . /topben . /ext_int
3540 + istepadd . topnen . topben . /ext_int
3541 + /gourd . /gourz . /topnen . /topben
3542 + /gourd . /gourz . topnen . topben
3543 + shadeadd . /topnen . /topben
3544 + shadeadd . topnen . topben
3545 + init_ii . /topnen . /topben . /ext_int
3546 + init_ii . topnen . topben . /ext_int
3549 Bit 1 = dwrite . gourd . atick[1] . /topben . /ext_int
3550 + istepadd . /topben . /ext_int
3551 + /gourd . /gourz . /topben
3552 + shadeadd . /topben
3553 + init_ii . /topben . /ext_int
3555 Bit 2 = /gourd . /gourz
3557 + dwrite . gourd . atick[1] . ext_int
3558 + istepadd . ext_int
3561 uint8 daddmode = ((dzwrite && gourz) || (dwrite && gourd && !topnen && !topben && !ext_int)
3562 || (dwrite && gourd && topnen && topben && !ext_int) || zstepadd
3563 || (istepadd && !topnen && !topben && !ext_int)
3564 || (istepadd && topnen && topben && !ext_int) || (!gourd && !gourz && !topnen && !topben)
3565 || (!gourd && !gourz && topnen && topben) || (shadeadd && !topnen && !topben)
3566 || (shadeadd && topnen && topben) || (init_ii && !topnen && !topben && !ext_int)
3567 || (init_ii && topnen && topben && !ext_int) || init_zi ? 0x01 : 0x00);
3568 daddmode |= ((dwrite && gourd && !topben && !ext_int) || (istepadd && !topben && !ext_int)
3569 || (!gourd && !gourz && !topben) || (shadeadd && !topben)
3570 || (init_ii && !topben && !ext_int) ? 0x02 : 0x00);
3571 daddmode |= ((!gourd && !gourz) || shadeadd || (dwrite && gourd && ext_int)
3572 || (istepadd && ext_int) || (init_ii && ext_int) ? 0x04 : 0x00);
3573 /* Data add load controls
3574 Pattern fraction (dest data) is loaded on
3575 dwrite . gourd . atick[0]
3576 + istepfadd . /datinit
3578 Pattern data is loaded on
3579 dwrite . gourd . atick[1]
3580 + istepadd . /datinit . /datinit
3582 Source z1 is loaded on
3583 dzwrite . gourz . atick[1]
3584 + zstepadd . /datinit . /datinit
3586 Source z2 is loaded on
3587 dzwrite . gourz . atick[0]
3590 Texture map shaded data is loaded on
3591 srcdreadd . srcshade
3593 bool patfadd = (dwrite && gourd) || (istepfadd && !datinit) || init_if;
3594 bool patdadd = (dwrite && gourd) || (istepadd && !datinit) || init_ii;
3595 bool srcz1add = (dzwrite && gourz) || (zstepadd && !datinit) || init_zi;
3596 bool srcz2add = (dzwrite && gourz) || zstepfadd || init_zf;
3597 bool srcshadd = srcdreadd && srcshade;
3598 bool daddq_sel = patfadd || patdadd || srcz1add || srcz2add || srcshadd;
3599 /* Select write data
3600 This has to be controlled from stage 1 of the pipe-line, delayed
3601 by one tick, as the write occurs in the cycle after the ack.
3608 Bit 0 = /patdsel . /adddsel
3613 uint8 data_sel = ((!patdsel && !adddsel) || dzwrite ? 0x01 : 0x00)
3614 | (adddsel || dzwrite ? 0x02 : 0x00);
3616 uint32 address, pixAddr;
3617 ADDRGEN(address, pixAddr, gena2i, zaddr,
3618 a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset,
3619 a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset);
3621 //Here's my guess as to how the addresses get truncated to phrase boundaries in phrase mode...
3623 address &= 0xFFFFF8;
3625 /* Generate source alignment shift
3626 -------------------------------
3627 The source alignment shift for data move is the difference between
3628 the source and destination X pointers, multiplied by the pixel
3629 size. Only the low six bits of the pointers are of interest, as
3630 pixel sizes are always a power of 2 and window rows are always
3633 When not in phrase mode, the top 3 bits of the shift value are
3636 Source shifting is also used to extract bits for bit-to-byte
3637 expansion in phrase mode. This involves only the bottom three
3638 bits of the shift value, and is based on the offset within the
3639 phrase of the destination X pointer, in pixels.
3641 Source shifting is disabled when srcen is not set.
3643 uint8 dstxp = (dsta2 ? a2_x : a1_x) & 0x3F;
3644 uint8 srcxp = (dsta2 ? a1_x : a2_x) & 0x3F;
3645 uint8 shftv = ((dstxp - srcxp) << pixsize) & 0x3F;
3646 /* The phrase mode alignment count is given by the phrase offset
3647 of the first pixel, for bit to byte expansion */
3651 pobb = dstxp & 0x07;
3653 pobb = dstxp & 0x03;
3655 pobb = dstxp & 0x01;
3657 bool pobbsel = phrase_mode && bcompen;
3658 uint8 loshd = (pobbsel ? pobb : shftv) & 0x07;
3659 uint8 shfti = (srcen || pobbsel ? (sshftld ? loshd : srcshift & 0x07) : 0);
3660 /* Enable for high bits is srcen . phrase_mode */
3661 shfti |= (srcen && phrase_mode ? (sshftld ? shftv & 0x38 : srcshift & 0x38) : 0);
3666 #ifdef VERBOSE_BLITTER_LOGGING
3669 printf(" Entering SREADX state...");
3670 //printf(" [dstart=%X dend=%X pwidth=%X srcshift=%X]\n", dstart, dend, pwidth, srcshift);
3674 //uint32 srcAddr, pixAddr;
3675 //ADDRGEN(srcAddr, pixAddr, gena2i, zaddr,
3676 // a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset,
3677 // a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset);
3679 srcd1 = ((uint64)JaguarReadLong(address, BLITTER) << 32) | (uint64)JaguarReadLong(address + 4, BLITTER);
3680 //Kludge to take pixel size into account...
3685 else if (pixsize == 4)
3690 #ifdef VERBOSE_BLITTER_LOGGING
3693 printf(" Source extra read address/pix address: %08X/%1X [%08X%08X]\n", address, pixAddr,
3694 (uint32)(srcd1 >> 32), (uint32)(srcd1 & 0xFFFFFFFF));
3702 #ifdef VERBOSE_BLITTER_LOGGING
3705 printf(" Entering SZREADX state...\n");
3713 #ifdef VERBOSE_BLITTER_LOGGING
3716 printf(" Entering SREAD state...");
3717 //printf(" [dstart=%X dend=%X pwidth=%X srcshift=%X]\n", dstart, dend, pwidth, srcshift);
3721 //uint32 srcAddr, pixAddr;
3722 //ADDRGEN(srcAddr, pixAddr, gena2i, zaddr,
3723 // a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset,
3724 // a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset);
3726 srcd1 = ((uint64)JaguarReadLong(address, BLITTER) << 32) | (uint64)JaguarReadLong(address + 4, BLITTER);
3727 //Kludge to take pixel size into account...
3732 else if (pixsize == 4)
3737 #ifdef VERBOSE_BLITTER_LOGGING
3740 printf(" Source read address/pix address: %08X/%1X [%08X%08X]\n", address, pixAddr,
3741 (uint32)(srcd1 >> 32), (uint32)(srcd1 & 0xFFFFFFFF));
3749 #ifdef VERBOSE_BLITTER_LOGGING
3752 printf(" Entering SZREADX state...\n");
3760 #ifdef VERBOSE_BLITTER_LOGGING
3763 printf(" Entering DREAD state...\n");
3767 //uint32 dstAddr, pixAddr;
3768 //ADDRGEN(dstAddr, pixAddr, gena2i, zaddr,
3769 // a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset,
3770 // a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset);
3771 dstd = ((uint64)JaguarReadLong(address, BLITTER) << 32) | (uint64)JaguarReadLong(address + 4, BLITTER);
3772 //Kludge to take pixel size into account...
3777 else if (pixsize == 4)
3782 #ifdef VERBOSE_BLITTER_LOGGING
3785 printf(" Dest read address/pix address: %08X/%1X [%08X%08X]\n", address, pixAddr,
3786 (uint32)(dstd >> 32), (uint32)(dstd & 0xFFFFFFFF));
3794 // Is Z always 64 bit read? Or sometimes 16 bit (dependent on phrase_mode)?
3795 #ifdef VERBOSE_BLITTER_LOGGING
3798 printf(" Entering DZREAD state...");
3802 dstz = ((uint64)JaguarReadLong(address, BLITTER) << 32) | (uint64)JaguarReadLong(address + 4, BLITTER);
3803 #ifdef VERBOSE_BLITTER_LOGGING
3806 printf(" Dest Z read address/pix address: %08X/%1X [%08X%08X]\n", address, pixAddr,
3807 (uint32)(dstz >> 32), (uint32)(dstz & 0xFFFFFFFF));
3813 //NOTE: SRCSHADE requires GOURZ to be set to work properly--another Jaguar I bug
3816 #ifdef VERBOSE_BLITTER_LOGGING
3819 printf(" Entering DWRITE state...\n");
3823 //Counter is done on the dwrite state...! (We'll do it first, since it affects dstart/dend calculations.)
3824 //Here's the voodoo for figuring the correct amount of pixels in phrase mode (or not):
3825 int8 inct = -((dsta2 ? a2_x : a1_x) & 0x07); // From INNER_CNT
3827 inc = (!phrase_mode || (phrase_mode && (inct & 0x01)) ? 0x01 : 0x00);
3828 inc |= (phrase_mode && (((pixsize == 3 || pixsize == 4) && (inct & 0x02)) || pixsize == 5 && !(inct & 0x01)) ? 0x02 : 0x00);
3829 inc |= (phrase_mode && ((pixsize == 3 && (inct & 0x04)) || (pixsize == 4 && !(inct & 0x03))) ? 0x04 : 0x00);
3830 inc |= (phrase_mode && pixsize == 3 && !(inct & 0x07) ? 0x08 : 0x00);
3832 uint16 oldicount = icount; // Save icount to detect underflow...
3835 if (icount == 0 || ((icount & 0x8000) && !(oldicount & 0x8000)))
3837 // X/Y stepping is also done here, I think...No. It's done when a1_add or a2_add is asserted...
3839 //*********************************************************************************
3840 //Start & end write mask computations...
3841 //*********************************************************************************
3846 dstart = (dstxp & 0x07) << 3;
3848 dstart = (dstxp & 0x03) << 4;
3850 dstart = (dstxp & 0x01) << 5;
3852 dstart = (phrase_mode ? dstart : pixAddr & 0x07);
3854 //This is the other Jaguar I bug... Normally, should ALWAYS select a1_x here.
3855 uint16 dstxwr = (dsta2 ? a2_x : a1_x) & 0x7FFE;
3856 uint16 pseq = dstxwr ^ (a1_win_x & 0x7FFE);
3857 pseq = (pixsize == 5 ? pseq : pseq & 0x7FFC);
3858 pseq = ((pixsize & 0x06) == 4 ? pseq : pseq & 0x7FF8);
3859 bool penden = clip_a1 && (pseq == 0);
3860 uint8 window_mask = 0;
3863 window_mask = (a1_win_x & 0x07) << 3;
3865 window_mask = (a1_win_x & 0x03) << 4;
3867 window_mask = (a1_win_x & 0x01) << 5;
3869 window_mask = (penden ? window_mask : 0);
3872 Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20]
3873 Source extra read address/pix address: 000095D0/0 [000004E40000001C]
3874 Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3875 Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=20]
3876 Source read address/pix address: 000095D8/0 [0054003800009814]
3877 Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3878 Entering DWRITE state...
3879 Dest write address/pix address: 00037290/0 [dstart=0 dend=20 pwidth=8 srcshift=20][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000001C00000000] (icount=026E, inc=4)
3880 Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
3882 (icount=026E, inc=4)
3883 icount & 0x03 = 0x02
3886 window_mask = 0x1000
3888 Therefore, it chooses the inner_mask over the window_mask every time! Argh!
3889 This is because we did this wrong:
3890 Innerm[3-5] := AN2 (inner_mask[3-5], imb[3-5], inner0);
3891 NOTE! This doesn't fix the problem because inner0 is asserted too late to help here. !!! FIX !!! [Should be DONE]
3894 /* The mask to be used if within one phrase of the end of the inner
3896 uint8 inner_mask = 0;
3899 inner_mask = (icount & 0x07) << 3;
3901 inner_mask = (icount & 0x03) << 4;
3903 inner_mask = (icount & 0x01) << 5;
3906 /* The actual mask used should be the lesser of the window masks and
3907 the inner mask, where is all cases 000 means 1000. */
3908 window_mask = (window_mask == 0 ? 0x40 : window_mask);
3909 inner_mask = (inner_mask == 0 ? 0x40 : inner_mask);
3910 uint8 emask = (window_mask > inner_mask ? inner_mask : window_mask);
3911 /* The mask to be used for the pixel size, to which must be added
3913 uint8 pma = pixAddr + (1 << pixsize);
3914 /* Select the mask */
3915 uint8 dend = (phrase_mode ? emask : pma);
3917 /* The cycle width in phrase mode is normally one phrase. However,
3918 at the start and end it may be narrower. The start and end masks
3919 are used to generate this. The width is given by:
3921 8 - start mask - (8 - end mask)
3922 = end mask - start mask
3924 This is only used for writes in phrase mode.
3925 Start and end from the address level of the pipeline are used.
3927 uint8 pwidth = (((dend | dstart) & 0x07) == 0 ? 0x08 : (dend - dstart) & 0x07);
3929 //uint32 dstAddr, pixAddr;
3930 //ADDRGEN(dstAddr, pixAddr, gena2i, zaddr,
3931 // a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset,
3932 // a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset);
3933 #ifdef VERBOSE_BLITTER_LOGGING
3936 printf(" Dest write address/pix address: %08X/%1X", address, pixAddr);
3937 printf(" [dstart=%X dend=%X pwidth=%X srcshift=%X]", dstart, dend, pwidth, srcshift);
3939 printf("[daas=%X dabs=%X dam=%X ds=%X daq=%s]", daddasel, daddbsel, daddmode, data_sel, (daddq_sel ? "T" : "F"));
3944 //Testing only... for now...
3945 //This is wrong because the write data is a combination of srcd and dstd--either run
3946 //thru the LFU or in PATDSEL or ADDDSEL mode.
3947 // Precedence is ADDDSEL > PATDSEL > LFU.
3948 //Also, doesn't take into account the start & end masks, or the phrase width...
3951 // srcd2 = xxxx xxxx 0123 4567, srcd = 8901 2345 xxxx xxxx, srcshift = $20 (32)
3952 uint64 srcd = (srcd2 << (64 - srcshift)) | (srcd1 >> srcshift);
3953 //bleh, ugly ugly ugly
3957 //Temporary kludge, to see if the fractional pattern does anything...
3962 uint8 initcin[4] = { 0, 0, 0, 0 };
3963 ADDARRAY(addq, 4/*daddasel*/, 4/*daddbsel*/, 0/*daddmode*/, dstd, iinc, initcin, 0, 0, 0, patd, srcd, 0, 0, 0, 0);
3964 srcd1 = ((uint64)addq[3] << 48) | ((uint64)addq[2] << 32) | ((uint64)addq[1] << 16) | (uint64)addq[0];
3967 //Note that we still don't take atick[0] & [1] into account here, so this will skip half of the data needed... !!! FIX !!!
3968 //Not yet enumerated: dbinh, srcdread, srczread
3970 //When in SRCSHADE mode, it adds the IINC to the read source (from LFU???)
3971 //According to following line, it gets LFU mode. But does it feed the source into the LFU
3973 //Dest write address/pix address: 0014E83E/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003F, inc=1)
3977 //NOTE: This is basically doubling the work done by DATA--since this is what
3978 // ADDARRAY is loaded with when srschshade is enabled... !!! FIX !!!
3979 // Also note that it doesn't work properly unless GOURZ is set--there's the clue!
3981 uint8 initcin[4] = { 0, 0, 0, 0 };
3982 ADDARRAY(addq, 4/*daddasel*/, 5/*daddbsel*/, 7/*daddmode*/, dstd, iinc, initcin, 0, 0, 0, patd, srcd, 0, 0, 0, 0);
3983 srcd = ((uint64)addq[3] << 48) | ((uint64)addq[2] << 32) | ((uint64)addq[1] << 16) | (uint64)addq[0];
3985 //Seems to work... Not 100% sure tho.
3988 bool winhibit;// = false;
3991 DATA(wdata, dcomp, zcomp, winhibit,
3992 true, cmpdst, daddasel, daddbsel, daddmode, daddq_sel, data_sel, 0/*dbinh*/,
3993 dend, dstart, dstd, iinc, lfufunc, patd, patdadd,
3994 phrase_mode, srcd, false/*srcdread*/, false/*srczread*/, srcz2add, zmode,
3995 bcompen, bkgwren, dcompen, icount & 0x07, pixsize);
3996 // bool bcompen, bool bkgwren, bool dcompen, uint8 icount, uint8 pixsize)
4006 a1_outside // A1 pointer is outside window bounds
4015 // The address is outside if negative, or if greater than or equal
4016 // to the window size
4018 A1_xcomp := MAG_15 (a1xgr, a1xeq, a1xlt, a1_x{0..14}, a1_win_x{0..14});
4019 A1_ycomp := MAG_15 (a1ygr, a1yeq, a1ylt, a1_y{0..14}, a1_win_y{0..14});
4020 A1_outside := OR6 (a1_outside, a1_x{15}, a1xgr, a1xeq, a1_y{15}, a1ygr, a1yeq);
4022 //NOTE: There seems to be an off-by-one bug here in the clip_a1 section... !!! FIX !!!
4023 if (clip_a1 && ((a1_x & 0x8000) || (a1_y & 0x8000) || (a1_x >= a1_win_x) || (a1_y >= a1_win_y)))
4028 //This is currently not correct for phrase mode. !!! FIX !!!
4029 if ((pixsize == 3 && (dcomp & 0x01))
4030 || (pixsize == 4 && (dcomp & 0x03)))
4038 JaguarWriteLong(address + 0, wdata >> 32, BLITTER);
4039 JaguarWriteLong(address + 4, wdata & 0xFFFFFFFF, BLITTER);
4044 JaguarWriteLong(address, wdata & 0xFFFFFFFF, BLITTER);
4045 else if (pixsize == 4)
4046 JaguarWriteWord(address, wdata & 0x0000FFFF, BLITTER);
4048 JaguarWriteByte(address, wdata & 0x000000FF, BLITTER);
4051 #ifdef VERBOSE_BLITTER_LOGGING
4054 printf(" [%08X%08X]", (uint32)(wdata >> 32), (uint32)(wdata & 0xFFFFFFFF));
4060 #ifdef VERBOSE_BLITTER_LOGGING
4063 printf(" (icount=%04X, inc=%u)\n", icount, (uint16)inc);
4071 #ifdef VERBOSE_BLITTER_LOGGING
4074 printf(" Entering DZWRITE state...\n");
4082 #ifdef VERBOSE_BLITTER_LOGGING
4085 //printf(" Entering A1_ADD state [addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0"));
4086 printf(" Entering A1_ADD state [a1_x=%04X, a1_y=%04X, addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", a1_x, a1_y, addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0"));
4090 int16 adda_x, adda_y, addb_x, addb_y, data_x, data_y, addq_x, addq_y;
4091 ADDAMUX(adda_x, adda_y, addasel, a1_step_x, a1_step_y, a1_stepf_x, a1_stepf_y, a2_step_x, a2_step_y,
4092 a1_inc_x, a1_inc_y, a1_incf_x, a1_incf_y, adda_xconst, adda_yconst, addareg, suba_x, suba_y);
4093 ADDBMUX(addb_x, addb_y, addbsel, a1_x, a1_y, a2_x, a2_y, a1_frac_x, a1_frac_y);
4094 ADDRADD(addq_x, addq_y, a1fracldi, adda_x, adda_y, addb_x, addb_y, modx, suba_x, suba_y);
4096 #if 0//def VERBOSE_BLITTER_LOGGING
4099 printf(" [adda_x=%d, adda_y=%d, addb_x=%d, addb_y=%d, addq_x=%d, addq_y=%d]\n", adda_x, adda_y, addb_x, addb_y, addq_x, addq_y);
4103 //Now, write to what???
4104 //a2ptrld comes from a2ptrldi...
4105 //I believe it's addbsel that determines the writeback...
4106 // This is where atick[0] & [1] come in, in determining which part (fractional, integer)
4107 // gets written to...
4110 //Kludge, to get A1 channel increment working...
4113 a1_frac_x = addq_x, a1_frac_y = addq_y;
4115 addasel = 2, addbsel = 0, a1fracldi = false;
4116 ADDAMUX(adda_x, adda_y, addasel, a1_step_x, a1_step_y, a1_stepf_x, a1_stepf_y, a2_step_x, a2_step_y,
4117 a1_inc_x, a1_inc_y, a1_incf_x, a1_incf_y, adda_xconst, adda_yconst, addareg, suba_x, suba_y);
4118 ADDBMUX(addb_x, addb_y, addbsel, a1_x, a1_y, a2_x, a2_y, a1_frac_x, a1_frac_y);
4119 ADDRADD(addq_x, addq_y, a1fracldi, adda_x, adda_y, addb_x, addb_y, modx, suba_x, suba_y);
4121 a1_x = addq_x, a1_y = addq_y;
4124 a1_x = addq_x, a1_y = addq_y;
4129 #ifdef VERBOSE_BLITTER_LOGGING
4132 //printf(" Entering A2_ADD state [addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0"));
4133 printf(" Entering A2_ADD state [a2_x=%04X, a2_y=%04X, addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", a2_x, a2_y, addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0"));
4137 //void ADDAMUX(int16 &adda_x, int16 &adda_y, uint8 addasel, int16 a1_step_x, int16 a1_step_y,
4138 // int16 a1_stepf_x, int16 a1_stepf_y, int16 a2_step_x, int16 a2_step_y,
4139 // int16 a1_inc_x, int16 a1_inc_y, int16 a1_incf_x, int16 a1_incf_y, uint8 adda_xconst,
4140 // bool adda_yconst, bool addareg, bool suba_x, bool suba_y)
4141 //void ADDBMUX(int16 &addb_x, int16 &addb_y, uint8 addbsel, int16 a1_x, int16 a1_y,
4142 // int16 a2_x, int16 a2_y, int16 a1_frac_x, int16 a1_frac_y)
4143 //void ADDRADD(int16 &addq_x, int16 &addq_y, bool a1fracldi,
4144 // int16 adda_x, int16 adda_y, int16 addb_x, int16 addb_y, uint8 modx, bool suba_x, bool suba_y)
4145 //void DATAMUX(int16 &data_x, int16 &data_y, uint32 gpu_din, int16 addq_x, int16 addq_y, bool addqsel)
4146 int16 adda_x, adda_y, addb_x, addb_y, data_x, data_y, addq_x, addq_y;
4147 ADDAMUX(adda_x, adda_y, addasel, a1_step_x, a1_step_y, a1_stepf_x, a1_stepf_y, a2_step_x, a2_step_y,
4148 a1_inc_x, a1_inc_y, a1_incf_x, a1_incf_y, adda_xconst, adda_yconst, addareg, suba_x, suba_y);
4149 ADDBMUX(addb_x, addb_y, addbsel, a1_x, a1_y, a2_x, a2_y, a1_frac_x, a1_frac_y);
4150 ADDRADD(addq_x, addq_y, a1fracldi, adda_x, adda_y, addb_x, addb_y, modx, suba_x, suba_y);
4152 #if 0//def VERBOSE_BLITTER_LOGGING
4155 printf(" [adda_x=%d, adda_y=%d, addb_x=%d, addb_y=%d, addq_x=%d, addq_y=%d]\n", adda_x, adda_y, addb_x, addb_y, addq_x, addq_y);
4159 //Now, write to what???
4160 //a2ptrld comes from a2ptrldi...
4161 //I believe it's addbsel that determines the writeback...
4167 Flags: SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 DSTA2 GOURZ ZMODE=0 LFUFUNC=C SRCSHADE
4169 a1_base = 0015B000, a2_base = 0014B000
4170 a1_x = 0000, a1_y = 0000, a1_frac_x = 8000, a1_frac_y = 8000, a2_x = 001F, a2_y = 0038
4171 a1_step_x = FFFFFFC0, a1_step_y = 0001, a1_stepf_x = 0000, a1_stepf_y = 2AAA, a2_step_x = FFFFFFC0, a2_step_y = 0001
4172 a1_inc_x = 0001, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000
4173 a1_win_x = 0040, a1_win_y = 0040, a2_mask_x = 0000, a2_mask_y = 0000
4174 a2_mask=F a1add=+inc/+0 a2add=+1/+0
4175 a1_pixsize = 4, a2_pixsize = 4
4176 srcd=FF00FF00FF00FF00 dstd=0000000000000000 patd=0000000000000000 iinc=00000000
4177 srcz1=0000000000000000 srcz2=0000000000000000 dstz=0000000000000000 zinc=00000000, col=0
4179 [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4180 Entering INNER state...
4181 Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505]
4182 Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4183 Entering DWRITE state...
4184 Dest write address/pix address: 0014E83E/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003F, inc=1)
4185 Entering A2_ADD state [a2_x=001F, a2_y=0038, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4186 Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505]
4187 Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4188 Entering DWRITE state...
4189 Dest write address/pix address: 0014E942/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003E, inc=1)
4190 Entering A2_ADD state [a2_x=0021, a2_y=0039, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4191 Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505]
4192 Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4193 Entering DWRITE state...
4194 Dest write address/pix address: 0014EA46/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003D, inc=1)
4195 Entering A2_ADD state [a2_x=0023, a2_y=003A, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4196 Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505]
4197 Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4198 Entering DWRITE state...
4199 Dest write address/pix address: 0014EB4A/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003C, inc=1)
4200 Entering A2_ADD state [a2_x=0025, a2_y=003B, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4202 Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505]
4203 Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4204 Entering DWRITE state...
4205 Dest write address/pix address: 0015283A/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=0000, inc=1)
4206 Entering A2_ADD state [a2_x=009D, a2_y=0077, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4207 Entering IDLE_INNER state...
4208 Leaving INNER state... (ocount=0036)
4209 [in=F a1f=T a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4210 Entering A1FUPDATE state...
4211 [in=F a1f=F a1=T zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4212 Entering A1UPDATE state... (-32768/-32768 -> 32704/-32767)
4213 [in=F a1f=F a1=F zf=F z=F a2=T iif=F iii=F izf=F izi=F]
4214 Entering A2UPDATE state... (159/120 -> 95/121)
4215 [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4216 Entering INNER state...
4219 #ifdef VERBOSE_BLITTER_LOGGING
4222 printf(" Leaving INNER state...");
4227 // The outer counter is updated here as well on the clock cycle...
4229 /* the inner loop is started whenever another state is about to
4230 cause the inner state to go active */
4231 //Instart := ND7 (instart, innert[0], innert[2..7]);
4233 //Actually, it's done only when inner gets asserted without the 2nd line of conditions
4234 //(inner AND !indone)
4236 //Since we don't get here until the inner loop is finished (indone = true) we can get
4237 //away with doing it here...!
4242 #ifdef VERBOSE_BLITTER_LOGGING
4245 printf(" (ocount=%04X)\n", ocount);
4253 #ifdef VERBOSE_BLITTER_LOGGING
4256 printf(" Entering A1FUPDATE state...\n");
4260 uint32 a1_frac_xt = (uint32)a1_frac_x + (uint32)a1_stepf_x;
4261 uint32 a1_frac_yt = (uint32)a1_frac_y + (uint32)a1_stepf_y;
4262 a1FracCInX = a1_frac_xt >> 16;
4263 a1FracCInY = a1_frac_yt >> 16;
4264 a1_frac_x = (uint16)(a1_frac_xt & 0xFFFF);
4265 a1_frac_y = (uint16)(a1_frac_yt & 0xFFFF);
4270 #ifdef VERBOSE_BLITTER_LOGGING
4273 printf(" Entering A1UPDATE state... (%d/%d -> ", a1_x, a1_y);
4277 a1_x += a1_step_x + a1FracCInX;
4278 a1_y += a1_step_y + a1FracCInY;
4279 #ifdef VERBOSE_BLITTER_LOGGING
4282 printf("%d/%d)\n", a1_x, a1_y);
4290 #ifdef VERBOSE_BLITTER_LOGGING
4293 printf(" Entering A2UPDATE state... (%d/%d -> ", a2_x, a2_y);
4299 #ifdef VERBOSE_BLITTER_LOGGING
4302 printf("%d/%d)\n", a2_x, a2_y);
4309 // Write values back to registers (in real blitter, these are continuously updated)
4310 SET16(blitter_ram, A1_PIXEL + 0, a1_y);
4311 SET16(blitter_ram, A1_PIXEL + 2, a1_x);
4312 SET16(blitter_ram, A1_FPIXEL + 0, a1_frac_y);
4313 SET16(blitter_ram, A1_FPIXEL + 2, a1_frac_x);
4314 SET16(blitter_ram, A2_PIXEL + 0, a2_y);
4315 SET16(blitter_ram, A2_PIXEL + 2, a2_x);
4320 The latest that doesn't work properly:
4322 Blit! (CMD = 09800741)
4323 Flags: SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 LFUFUNC=C DCOMPEN
4325 a1_base = 00050000, a2_base = 0083F400
4326 a1_x = 003D, a1_y = 00AD, a1_frac_x = 8000, a1_frac_y = 0000, a2_x = 0027, a2_y = 00A4
4327 a1_step_x = FFF1, a1_step_y = 0001, a1_stepf_x = 0000, a1_stepf_y = 0000, a2_step_x = FFF1, a2_step_y = 0001
4328 a1_inc_x = 0001, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000
4329 a1_win_x = 0180, a1_win_y = 0118, a2_mask_x = 0000, a2_mask_y = 0000
4330 a2_mask=F a1add=+inc/+0 a2add=+1/+0
4331 a1_pixsize = 4, a2_pixsize = 4
4332 srcd=0000000000000000 dstd=0000000000000000 patd=0000000000000000 iinc=00FFF000
4333 srcz1=0000000000000000 srcz2=0000000000000000 dstz=0000000000000000 zinc=00000000, col=2
4335 [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4336 Entering INNER state...
4337 Entering SREAD state... Source read address/pix address: 00858E4E/0 [0000000000000000]
4338 Entering A2_ADD state [a2_x=0027, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4339 Entering DWRITE state...
4340 Dest write address/pix address: 0007077A/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000000000000000] (icount=000E, inc=1)
4341 Entering A1_ADD state [a1_x=003D, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4342 Entering SREAD state... Source read address/pix address: 00858E50/0 [0000000000000000]
4343 Entering A2_ADD state [a2_x=0028, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4344 Entering DWRITE state...
4345 Dest write address/pix address: 0007077C/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000000000000000] (icount=000D, inc=1)
4346 Entering A1_ADD state [a1_x=003E, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4347 Entering SREAD state... Source read address/pix address: 00858E52/0 [0000000000000000]
4348 Entering A2_ADD state [a2_x=0029, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4349 Entering DWRITE state...
4350 Dest write address/pix address: 0007077E/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000000000000000] (icount=000C, inc=1)
4351 Entering A1_ADD state [a1_x=003F, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4352 Entering SREAD state... Source read address/pix address: 00858E54/0 [000000000000014A]
4353 Entering A2_ADD state [a2_x=002A, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4354 Entering DWRITE state...
4355 Dest write address/pix address: 00070780/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=000B, inc=1)
4356 Entering A1_ADD state [a1_x=0040, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4357 Entering SREAD state... Source read address/pix address: 00858E56/0 [000000000000014A]
4358 Entering A2_ADD state [a2_x=002B, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4359 Entering DWRITE state...
4360 Dest write address/pix address: 00070782/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=000A, inc=1)
4361 Entering A1_ADD state [a1_x=0041, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4362 Entering SREAD state... Source read address/pix address: 00858E58/0 [000000000000014A]
4363 Entering A2_ADD state [a2_x=002C, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4364 Entering DWRITE state...
4365 Dest write address/pix address: 00070784/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=0009, inc=1)
4366 Entering A1_ADD state [a1_x=0042, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4367 Entering SREAD state... Source read address/pix address: 00858E5A/0 [000000000000014A]
4368 Entering A2_ADD state [a2_x=002D, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4369 Entering DWRITE state...
4370 Dest write address/pix address: 00070786/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=0008, inc=1)
4371 Entering A1_ADD state [a1_x=0043, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4372 Entering SREAD state... Source read address/pix address: 00858E5C/0 [000000000000014A]
4373 Entering A2_ADD state [a2_x=002E, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4374 Entering DWRITE state...
4375 Dest write address/pix address: 00070788/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=0007, inc=1)
4376 Entering A1_ADD state [a1_x=0044, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4377 Entering SREAD state... Source read address/pix address: 00858E5E/0 [000000000000014A]
4378 Entering A2_ADD state [a2_x=002F, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4379 Entering DWRITE state...
4380 Dest write address/pix address: 0007078A/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=0006, inc=1)
4381 Entering A1_ADD state [a1_x=0045, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4382 Entering SREAD state... Source read address/pix address: 00858E60/0 [000000000000014A]
4383 Entering A2_ADD state [a2_x=0030, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4384 Entering DWRITE state...
4385 Dest write address/pix address: 0007078C/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=0005, inc=1)
4386 Entering A1_ADD state [a1_x=0046, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4387 Entering SREAD state... Source read address/pix address: 00858E62/0 [000000000000014A]
4388 Entering A2_ADD state [a2_x=0031, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4389 Entering DWRITE state...
4390 Dest write address/pix address: 0007078E/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=0004, inc=1)
4391 Entering A1_ADD state [a1_x=0047, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4392 Entering SREAD state... Source read address/pix address: 00858E64/0 [000000000000014A]
4393 Entering A2_ADD state [a2_x=0032, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4394 Entering DWRITE state...
4395 Dest write address/pix address: 00070790/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [000000000000014A] (icount=0003, inc=1)
4396 Entering A1_ADD state [a1_x=0048, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4397 Entering SREAD state... Source read address/pix address: 00858E66/0 [0000000000000000]
4398 Entering A2_ADD state [a2_x=0033, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4399 Entering DWRITE state...
4400 Dest write address/pix address: 00070792/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000000000000000] (icount=0002, inc=1)
4401 Entering A1_ADD state [a1_x=0049, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4402 Entering SREAD state... Source read address/pix address: 00858E68/0 [0000000000000000]
4403 Entering A2_ADD state [a2_x=0034, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4404 Entering DWRITE state...
4405 Dest write address/pix address: 00070794/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000000000000000] (icount=0001, inc=1)
4406 Entering A1_ADD state [a1_x=004A, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4407 Entering SREAD state... Source read address/pix address: 00858E6A/0 [0000000000000000]
4408 Entering A2_ADD state [a2_x=0035, a2_y=00A4, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]...
4409 Entering DWRITE state...
4410 Dest write address/pix address: 00070796/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000000000000000] (icount=0000, inc=1)
4411 Entering A1_ADD state [a1_x=004B, a1_y=00AD, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]...
4412 Entering IDLE_INNER state...
4413 Leaving INNER state... (ocount=0011)
4414 [in=F a1f=T a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4415 Entering A1FUPDATE state...
4416 [in=F a1f=F a1=T zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4417 Entering A1UPDATE state... (76/173 -> 61/174)
4418 [in=F a1f=F a1=F zf=F z=F a2=T iif=F iii=F izf=F izi=F]
4419 Entering A2UPDATE state... (54/164 -> 39/165)
4420 [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F]
4421 Entering INNER state...
4425 // Various pieces of the blitter puzzle are teased out here...
4431 INT24/ address // byte address
4432 pixa[0..2] // bit part of address, un-pipe-lined
4448 apipe // load address pipe-line latch
4449 clk // co-processor clock
4450 gena2 // generate A2 as opposed to A1
4451 zaddr // generate Z address
4455 void ADDRGEN(uint32 &address, uint32 &pixa, bool gena2, bool zaddr,
4456 uint16 a1_x, uint16 a1_y, uint32 a1_base, uint8 a1_pitch, uint8 a1_pixsize, uint8 a1_width, uint8 a1_zoffset,
4457 uint16 a2_x, uint16 a2_y, uint32 a2_base, uint8 a2_pitch, uint8 a2_pixsize, uint8 a2_width, uint8 a2_zoffset)
4459 uint16 x = (gena2 ? a2_x : a1_x) & 0x7FFF;
4460 uint16 y = (gena2 ? a2_y : a1_y) & 0x0FFF;
4461 uint8 width = (gena2 ? a2_width : a1_width);
4462 uint8 pixsize = (gena2 ? a2_pixsize : a1_pixsize);
4463 uint8 pitch = (gena2 ? a2_pitch : a1_pitch);
4464 uint32 base = (gena2 ? a2_base : a1_base) >> 3;//Only upper 21 bits are passed around the bus? Seems like it...
4465 uint8 zoffset = (gena2 ? a2_zoffset : a1_zoffset);
4467 uint32 ytm = ((uint32)y << 2) + (width & 0x02 ? (uint32)y << 1 : 0) + (width & 0x01 ? (uint32)y : 0);
4469 uint32 ya = (ytm << (width >> 2)) >> 2;
4473 /*uint32*/ pixa = pa << pixsize;
4475 uint8 pt = ((pitch & 0x01) && !(pitch & 0x02) ? 0x01 : 0x00)
4476 | (!(pitch & 0x01) && (pitch & 0x02) ? 0x02 : 0x00);
4477 // uint32 phradr = pixa << pt;
4478 uint32 phradr = (pixa >> 6) << pt;
4479 uint32 shup = (pitch == 0x03 ? (pixa >> 6) : 0);
4481 uint8 za = (zaddr ? zoffset : 0) & 0x03;
4482 // uint32 addr = za + (phradr & 0x07) + (shup << 1) + base;
4483 uint32 addr = za + phradr + (shup << 1) + base;
4484 /*uint32*/ address = ((pixa & 0x38) >> 3) | ((addr & 0x1FFFFF) << 3);
4485 #if 0//def VERBOSE_BLITTER_LOGGING
4488 printf(" [gena2=%s, x=%04X, y=%04X, w=%1X, pxsz=%1X, ptch=%1X, b=%08X, zoff=%1X]\n", (gena2 ? "T" : "F"), x, y, width, pixsize, pitch, base, zoffset);
4489 printf(" [ytm=%X, ya=%X, pa=%X, pixa=%X, pt=%X, phradr=%X, shup=%X, za=%X, addr=%X, address=%X]\n", ytm, ya, pa, pixa, pt, phradr, shup, za, addr, address);
4495 Entering INNER state...
4496 [gena2=T, x=0002, y=0000, w=20, pxsz=4, ptch=0, b=000012BA, zoff=0]
4497 [ytm=0, ya=0, pa=2, pixa=20, pt=0, phradr=0, shup=0, za=0, addr=12BA, address=95D4]
4498 Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20]
4499 Source extra read address/pix address: 000095D4/0 [0000001C00540038]
4500 Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
4501 [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000012BA, zoff=0]
4502 [ytm=0, ya=0, pa=4, pixa=40, pt=0, phradr=1, shup=0, za=0, addr=12BB, address=95D8]
4503 Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0]
4504 Source read address/pix address: 000095D8/0 [0054003800009814]
4505 Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
4506 [gena2=F, x=0000, y=0000, w=20, pxsz=4, ptch=0, b=00006E52, zoff=0]
4507 [ytm=0, ya=0, pa=0, pixa=0, pt=0, phradr=0, shup=0, za=0, addr=6E52, address=37290]
4508 Entering DWRITE state...
4509 Dest write address/pix address: 00037290/0 [dstart=0 dend=20 pwidth=8 srcshift=0] (icount=026E, inc=4)
4510 Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
4511 [gena2=T, x=0008, y=0000, w=20, pxsz=4, ptch=0, b=000012BA, zoff=0]
4512 [ytm=0, ya=0, pa=8, pixa=80, pt=0, phradr=2, shup=0, za=0, addr=12BC, address=95E0]
4516 Entering SREAD state...
4517 [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000010AC, zoff=0]
4518 [ytm=0, ya=0, pa=4, pixa=0, pt=0, phradr=40, shup=0, za=0, addr=10AC, address=8560]
4519 Source read address/pix address: 00008560/0 [8C27981B327E00F0]
4521 2nd pass (still wrong):
4522 Entering SREAD state...
4523 [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000010AC, zoff=0]
4524 [ytm=0, ya=0, pa=4, pixa=0, pt=0, phradr=40, shup=0, za=0, addr=10EC, address=8760]
4525 Source read address/pix address: 00008760/0 [00E06DC04581880C]
4528 Entering SREAD state...
4529 [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000010AC, zoff=0]
4530 [ytm=0, ya=0, pa=4, pixa=0, pt=0, phradr=1, shup=0, za=0, addr=10AD, address=8568]
4531 Source read address/pix address: 00008568/0 [6267981A327C00F0]
4533 OK, now we're back into incorrect (or is it?):
4534 Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20]
4535 Source extra read address/pix address: 000095D4/0 [0000 001C 0054 0038]
4536 Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
4537 Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0]
4538 Source read address/pix address: 000095D8/0 [0054 0038 0000 9814]
4539 Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]...
4540 I think this may be correct...!
4545 // source and destination address update conditions
4547 Sraat0 := AN2 (sraat[0], sreadxi, srcenz\);
4548 Sraat1 := AN2 (sraat[1], sreadi, srcenz\);
4549 Srca_addi := OR4 (srca_addi, szreadxi, szreadi, sraat[0..1]);
4550 Srca_add := FD1Q (srca_add, srca_addi, clk);
4552 Dstaat := AN2 (dstaat, dwritei, dstwrz\);
4553 Dsta_addi := OR2 (dsta_addi, dzwritei, dstaat);
4554 // Dsta_add := FD1Q (dsta_add, dsta_addi, clk);
4556 // source and destination address generate conditions
4558 Gensrc := OR4 (gensrc, sreadxi, szreadxi, sreadi, szreadi);
4559 Gendst := OR4 (gendst, dreadi, dzreadi, dwritei, dzwritei);
4560 Dsta2\ := INV1 (dsta2\, dsta2);
4561 Gena2t0 := NAN2 (gena2t[0], gensrc, dsta2\);
4562 Gena2t1 := NAN2 (gena2t[1], gendst, dsta2);
4563 Gena2i := NAN2 (gena2i, gena2t[0..1]);
4564 Gena2 := FD1QU (gena2, gena2i, clk);
4566 Zaddr := OR4 (zaddr, szreadx, szread, dzread, dzwrite);
4571 // Basically, the above translates to:
4572 bool srca_addi = (sreadxi && !srcenz) || (sreadi && !srcenz) || szreadxi || szreadi;
4574 bool dsta_addi = (dwritei && !dstwrz) || dzwritei;
4576 bool gensrc = sreadxi || szreadxi || sreadi || szreadi;
4577 bool gendst = dreadi || szreadi || dwritei || dzwritei;
4578 bool gena2i = (gensrc && !dsta2) || (gendst && dsta2);
4580 bool zaddr = szreadx || szread || dzread || dzwrite;
4584 // source data reads
4586 Srcdpset\ := NAN2 (srcdpset\, readreq, sread);
4587 Srcdpt1 := NAN2 (srcdpt[1], srcdpend, srcdack\);
4588 Srcdpt2 := NAN2 (srcdpt[2], srcdpset\, srcdpt[1]);
4589 Srcdpend := FD2Q (srcdpend, srcdpt[2], clk, reset\);
4591 Srcdxpset\ := NAN2 (srcdxpset\, readreq, sreadx);
4592 Srcdxpt1 := NAN2 (srcdxpt[1], srcdxpend, srcdxack\);
4593 Srcdxpt2 := NAN2 (srcdxpt[2], srcdxpset\, srcdxpt[1]);
4594 Srcdxpend := FD2Q (srcdxpend, srcdxpt[2], clk, reset\);
4596 Sdpend := OR2 (sdpend, srcdxpend, srcdpend);
4597 Srcdreadt := AN2 (srcdreadt, sdpend, read_ack);
4599 //2/9/92 - enhancement?
4600 //Load srcdread on the next tick as well to modify it in srcshade
4602 Srcdreadd := FD1Q (srcdreadd, srcdreadt, clk);
4603 Srcdread := AOR1 (srcdread, srcshade, srcdreadd, srcdreadt);
4607 Srczpset\ := NAN2 (srczpset\, readreq, szread);
4608 Srczpt1 := NAN2 (srczpt[1], srczpend, srczack\);
4609 Srczpt2 := NAN2 (srczpt[2], srczpset\, srczpt[1]);
4610 Srczpend := FD2Q (srczpend, srczpt[2], clk, reset\);
4612 Srczxpset\ := NAN2 (srczxpset\, readreq, szreadx);
4613 Srczxpt1 := NAN2 (srczxpt[1], srczxpend, srczxack\);
4614 Srczxpt2 := NAN2 (srczxpt[2], srczxpset\, srczxpt[1]);
4615 Srczxpend := FD2Q (srczxpend, srczxpt[2], clk, reset\);
4617 Szpend := OR2 (szpend, srczpend, srczxpend);
4618 Srczread := AN2 (srczread, szpend, read_ack);
4620 // destination data reads
4622 Dstdpset\ := NAN2 (dstdpset\, readreq, dread);
4623 Dstdpt0 := NAN2 (dstdpt[0], dstdpend, dstdack\);
4624 Dstdpt1 := NAN2 (dstdpt[1], dstdpset\, dstdpt[0]);
4625 Dstdpend := FD2Q (dstdpend, dstdpt[1], clk, reset\);
4626 Dstdread := AN2 (dstdread, dstdpend, read_ack);
4628 // destination zed reads
4630 Dstzpset\ := NAN2 (dstzpset\, readreq, dzread);
4631 Dstzpt0 := NAN2 (dstzpt[0], dstzpend, dstzack\);
4632 Dstzpt1 := NAN2 (dstzpt[1], dstzpset\, dstzpt[0]);
4633 Dstzpend := FD2Q (dstzpend, dstzpt[1], clk, reset\);
4634 Dstzread := AN2 (dstzread, dstzpend, read_ack);
4639 // Basically, the above translates to:
4640 bool srcdpend = (readreq && sread) || (srcdpend && !srcdack);
4641 bool srcdxpend = (readreq && sreadx) || (srcdxpend && !srcdxack);
4642 bool sdpend = srcxpend || srcdpend;
4643 bool srcdread = ((sdpend && read_ack) && srcshade) || (sdpend && read_ack);//the latter term is lookahead
4647 ////////////////////////////////////////////////////////////////////////////////////////////
4648 ////////////////////////////////////////////////////////////////////////////////////////////
4649 // Here's an important bit: The source data adder logic. Need to track down the inputs!!! //
4650 ////////////////////////////////////////////////////////////////////////////////////////////
4651 ////////////////////////////////////////////////////////////////////////////////////////////
4658 daddasel[0..2] // data adder input A selection
4663 initcin[0..3] // carry into the adders from the initializers
4664 initinc[0..63] // the initialisation increment
4665 initpix[0..15] // Data initialiser pixel value
4677 void ADDARRAY(uint16 * addq, uint8 daddasel, uint8 daddbsel, uint8 daddmode,
4678 uint64 dstd, uint32 iinc, uint8 initcin[], uint64 initinc, uint16 initpix,
4679 uint32 istep, uint64 patd, uint64 srcd, uint64 srcz1, uint64 srcz2,
4680 uint32 zinc, uint32 zstep)
4682 uint32 initpix2 = ((uint32)initpix << 16) | initpix;
4683 uint32 addalo[8], addahi[8];
4684 addalo[0] = dstd & 0xFFFFFFFF;
4685 addalo[1] = initpix2;
4688 addalo[4] = srcd & 0xFFFFFFFF;
4689 addalo[5] = patd & 0xFFFFFFFF;
4690 addalo[6] = srcz1 & 0xFFFFFFFF;
4691 addalo[7] = srcz2 & 0xFFFFFFFF;
4692 addahi[0] = dstd >> 32;
4693 addahi[1] = initpix2;
4696 addahi[4] = srcd >> 32;
4697 addahi[5] = patd >> 32;
4698 addahi[6] = srcz1 >> 32;
4699 addahi[7] = srcz2 >> 32;
4701 adda[0] = addalo[daddasel] & 0xFFFF;
4702 adda[1] = addalo[daddasel] >> 16;
4703 adda[2] = addahi[daddasel] & 0xFFFF;
4704 adda[3] = addahi[daddasel] >> 16;
4707 wordmux[0] = iinc & 0xFFFF;
4708 wordmux[1] = iinc >> 16;
4709 wordmux[2] = zinc & 0xFFFF;
4710 wordmux[3] = zinc >> 16;;
4711 wordmux[4] = istep & 0xFFFF;
4712 wordmux[5] = istep >> 16;;
4713 wordmux[6] = zstep & 0xFFFF;
4714 wordmux[7] = zstep >> 16;;
4715 uint16 word = wordmux[((daddbsel & 0x08) >> 1) | (daddbsel & 0x03)];
4717 bool dbsel2 = daddbsel & 0x04;
4718 bool iincsel = (daddbsel & 0x01) && !(daddbsel & 0x04);
4720 if (!dbsel2 && !iincsel)
4721 addb[0] = srcd & 0xFFFF,
4722 addb[1] = (srcd >> 16) & 0xFFFF,
4723 addb[2] = (srcd >> 32) & 0xFFFF,
4724 addb[3] = (srcd >> 48) & 0xFFFF;
4725 else if (dbsel2 && !iincsel)
4726 addb[0] = addb[1] = addb[2] = addb[3] = word;
4727 else if (!dbsel2 && iincsel)
4728 addb[0] = initinc & 0xFFFF,
4729 addb[1] = (initinc >> 16) & 0xFFFF,
4730 addb[2] = (initinc >> 32) & 0xFFFF,
4731 addb[3] = (initinc >> 48) & 0xFFFF;
4733 addb[0] = addb[1] = addb[2] = addb[3] = 0;
4735 uint8 cinsel = (daddmode >= 1 && daddmode <= 4 ? 1 : 0);
4737 static uint8 co[4];//These are preserved between calls...
4740 for(int i=0; i<4; i++)
4741 cin[i] = initcin[i] | (co[i] & cinsel);
4743 bool eightbit = daddmode & 0x02;
4744 bool sat = daddmode & 0x03;
4745 bool hicinh = ((daddmode & 0x03) == 0x03);
4747 //Note that the carry out is saved between calls to this function...
4748 for(int i=0; i<4; i++)
4749 ADD16SAT(addq[i], co[i], adda[i], addb[i], cin[i], sat, eightbit, hicinh);
4765 void ADD16SAT(uint16 &r, uint8 &co, uint16 a, uint16 b, uint8 cin, bool sat, bool eightbit, bool hicinh)
4768 uint32 qt = (a & 0xFF) + (b & 0xFF) + cin;
4769 carry[0] = (qt & 0x0100 ? 1 : 0);
4770 uint16 q = qt & 0x00FF;
4771 carry[1] = (carry[0] && !eightbit ? carry[0] : 0);
4772 qt = (a & 0x0F00) + (b & 0x0F00) + (carry[1] << 8);
4773 carry[2] = (qt & 0x1000 ? 1 : 0);
4775 carry[3] = (carry[2] && !hicinh ? carry[2] : 0);
4776 qt = (a & 0xF000) + (b & 0xF000) + (carry[3] << 12);
4777 co = (qt & 0x10000 ? 1 : 0);
4780 uint8 btop = (eightbit ? (b & 0x0080) >> 7 : (b & 0x8000) >> 15);
4781 uint8 ctop = (eightbit ? carry[0] : co);
4783 bool saturate = sat && (btop ^ ctop);
4784 bool hisaturate = saturate && !eightbit;
4786 r = (saturate ? (ctop ? 0x00FF : 0x0000) : q & 0x00FF);
4787 r |= (hisaturate ? (ctop ? 0xFF00 : 0x0000) : q & 0xFF00);
4790 /** ADDAMUX - Address adder input A selection *******************
4792 This module generates the data loaded into the address adder input A. This is
4793 the update value, and can be one of four registers : A1 step, A2 step, A1
4794 increment and A1 fraction. It can complement these values to perform
4795 subtraction, and it can generate constants to increment / decrement the window
4798 addasel[0..2] select the register to add
4800 000 A1 step integer part
4801 001 A1 step fraction part
4802 010 A1 increment integer part
4803 011 A1 increment fraction part
4806 adda_xconst[0..2] generate a power of 2 in the range 1-64 or all zeroes when
4809 addareg selects register value to be added as opposed to constant
4812 suba_x, suba_y complement the X and Y values
4838 void ADDAMUX(int16 &adda_x, int16 &adda_y, uint8 addasel, int16 a1_step_x, int16 a1_step_y,
4839 int16 a1_stepf_x, int16 a1_stepf_y, int16 a2_step_x, int16 a2_step_y,
4840 int16 a1_inc_x, int16 a1_inc_y, int16 a1_incf_x, int16 a1_incf_y, uint8 adda_xconst,
4841 bool adda_yconst, bool addareg, bool suba_x, bool suba_y)
4844 /*INT16/ addac_x, addac_y, addar_x, addar_y, addart_x, addart_y,
4845 INT16/ addas_x, addas_y, suba_x16, suba_y16
4849 Zero := TIE0 (zero);*/
4851 /* Multiplex the register terms */
4853 /*Addaselb[0-2] := BUF8 (addaselb[0-2], addasel[0-2]);
4854 Addart_x := MX4 (addart_x, a1_step_x, a1_stepf_x, a1_inc_x, a1_incf_x, addaselb[0..1]);
4855 Addar_x := MX2 (addar_x, addart_x, a2_step_x, addaselb[2]);
4856 Addart_y := MX4 (addart_y, a1_step_y, a1_stepf_y, a1_inc_y, a1_incf_y, addaselb[0..1]);
4857 Addar_y := MX2 (addar_y, addart_y, a2_step_y, addaselb[2]);*/
4859 ////////////////////////////////////// C++ CODE //////////////////////////////////////
4860 int16 xterm[4], yterm[4];
4861 xterm[0] = a1_step_x, xterm[1] = a1_stepf_x, xterm[2] = a1_inc_x, xterm[3] = a1_incf_x;
4862 yterm[0] = a1_step_y, yterm[1] = a1_stepf_y, yterm[2] = a1_inc_y, yterm[3] = a1_incf_y;
4863 int16 addar_x = (addasel & 0x04 ? a2_step_x : xterm[addasel & 0x03]);
4864 int16 addar_y = (addasel & 0x04 ? a2_step_y : yterm[addasel & 0x03]);
4865 //////////////////////////////////////////////////////////////////////////////////////
4867 /* Generate a constant value - this is a power of 2 in the range
4868 0-64, or zero. The control bits are adda_xconst[0..2], when they
4869 are all 1 the result is 0.
4870 Constants for Y can only be 0 or 1 */
4872 /*Addac_xlo := D38H (addac_x[0..6], unused[0], adda_xconst[0..2]);
4873 Unused[0] := DUMMY (unused[0]);
4875 Addac_x := JOIN (addac_x, addac_x[0..6], zero, zero, zero, zero, zero, zero, zero, zero, zero);
4876 Addac_y := JOIN (addac_y, adda_yconst, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero,
4877 zero, zero, zero, zero, zero);*/
4878 ////////////////////////////////////// C++ CODE //////////////////////////////////////
4879 int16 addac_x = (adda_xconst == 0x07 ? 0 : 1 << adda_xconst);
4880 int16 addac_y = (adda_yconst ? 0x01 : 0);
4881 //////////////////////////////////////////////////////////////////////////////////////
4883 /* Select between constant value and register value */
4885 /*Addas_x := MX2 (addas_x, addac_x, addar_x, addareg);
4886 Addas_y := MX2 (addas_y, addac_y, addar_y, addareg);*/
4887 ////////////////////////////////////// C++ CODE //////////////////////////////////////
4888 int16 addas_x = (addareg ? addar_x : addac_x);
4889 int16 addas_y = (addareg ? addar_y : addac_y);
4890 //////////////////////////////////////////////////////////////////////////////////////
4892 /* Complement these values (complement flag gives adder carry in)*/
4894 /*Suba_x16 := JOIN (suba_x16, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x,
4895 suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x);
4896 Suba_y16 := JOIN (suba_y16, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y,
4897 suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y);
4898 Adda_x := EO (adda_x, suba_x16, addas_x);
4899 Adda_y := EO (adda_y, suba_y16, addas_y);*/
4900 ////////////////////////////////////// C++ CODE //////////////////////////////////////
4901 adda_x = addas_x ^ (suba_x ? 0xFFFF : 0x0000);
4902 adda_y = addas_y ^ (suba_y ? 0xFFFF : 0x0000);
4903 //////////////////////////////////////////////////////////////////////////////////////
4908 /** ADDBMUX - Address adder input B selection *******************
4910 This module selects the register to be updated by the address
4911 adder. This can be one of three registers, the A1 and A2
4912 pointers, or the A1 fractional part. It can also be zero, so that the step
4913 registers load directly into the pointers.
4928 INT16/ zero16 :LOCAL;
4930 void ADDBMUX(int16 &addb_x, int16 &addb_y, uint8 addbsel, int16 a1_x, int16 a1_y,
4931 int16 a2_x, int16 a2_y, int16 a1_frac_x, int16 a1_frac_y)
4934 /*Zero := TIE0 (zero);
4935 Zero16 := JOIN (zero16, zero, zero, zero, zero, zero, zero, zero,
4936 zero, zero, zero, zero, zero, zero, zero, zero, zero);
4937 Addbselb[0-1] := BUF8 (addbselb[0-1], addbsel[0-1]);
4938 Addb_x := MX4 (addb_x, a1_x, a2_x, a1_frac_x, zero16, addbselb[0..1]);
4939 Addb_y := MX4 (addb_y, a1_y, a2_y, a1_frac_y, zero16, addbselb[0..1]);*/
4940 ////////////////////////////////////// C++ CODE //////////////////////////////////////
4941 int16 xterm[4], yterm[4];
4942 xterm[0] = a1_x, xterm[1] = a2_x, xterm[2] = a1_frac_x, xterm[3] = 0;
4943 yterm[0] = a1_y, yterm[1] = a2_y, yterm[2] = a1_frac_y, yterm[3] = 0;
4944 addb_x = xterm[addbsel & 0x03];
4945 addb_y = yterm[addbsel & 0x03];
4946 //////////////////////////////////////////////////////////////////////////////////////
4951 /** DATAMUX - Address local data bus selection ******************
4953 Select between the adder output and the input data bus
4966 INT16/ gpu_lo, gpu_hi
4969 void DATAMUX(int16 &data_x, int16 &data_y, uint32 gpu_din, int16 addq_x, int16 addq_y, bool addqsel)
4971 /*Gpu_lo := JOIN (gpu_lo, gpu_din{0..15});
4972 Gpu_hi := JOIN (gpu_hi, gpu_din{16..31});
4974 Addqselb := BUF8 (addqselb, addqsel);
4975 Data_x := MX2 (data_x, gpu_lo, addq_x, addqselb);
4976 Data_y := MX2 (data_y, gpu_hi, addq_y, addqselb);*/
4977 ////////////////////////////////////// C++ CODE //////////////////////////////////////
4978 data_x = (addqsel ? addq_x : (int16)(gpu_din & 0xFFFF));
4979 data_y = (addqsel ? addq_y : (int16)(gpu_din >> 16));
4980 //////////////////////////////////////////////////////////////////////////////////////
4985 /******************************************************************
4989 Blitter Address Adder
4990 ---------------------
4991 The blitter address adder is a pair of sixteen bit adders, one
4992 each for X and Y. The multiplexing of the input terms is
4993 performed elsewhere, but this adder can also perform modulo
4994 arithmetic to align X-addresses onto phrase boundaries.
4996 modx[0..2] take values
5003 ******************************************************************/
5005 /*IMPORT duplo, tosh;
5011 a1fracldi // propagate address adder carry
5016 clk[0] // co-processor clock
5024 Zero := TIE0 (zero);*/
5025 void ADDRADD(int16 &addq_x, int16 &addq_y, bool a1fracldi,
5026 uint16 adda_x, uint16 adda_y, uint16 addb_x, uint16 addb_y, uint8 modx, bool suba_x, bool suba_y)
5029 /* Perform the addition */
5031 /*Adder_x := ADD16 (addqt_x[0..15], co_x, adda_x{0..15}, addb_x{0..15}, ci_x);
5032 Adder_y := ADD16 (addq_y[0..15], co_y, adda_y{0..15}, addb_y{0..15}, ci_y);*/
5034 /* latch carry and propagate if required */
5036 /*Cxt0 := AN2 (cxt[0], co_x, a1fracldi);
5037 Cxt1 := FD1Q (cxt[1], cxt[0], clk[0]);
5038 Ci_x := EO (ci_x, cxt[1], suba_x);
5040 yt0 := AN2 (cyt[0], co_y, a1fracldi);
5041 Cyt1 := FD1Q (cyt[1], cyt[0], clk[0]);
5042 Ci_y := EO (ci_y, cyt[1], suba_y);*/
5044 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5045 //I'm sure the following will generate a bunch of warnings, but will have to do for now.
5046 static uint16 co_x = 0, co_y = 0; // Carry out has to propogate between function calls...
5047 uint16 ci_x = co_x ^ (suba_x ? 1 : 0);
5048 uint16 ci_y = co_y ^ (suba_y ? 1 : 0);
5049 uint32 addqt_x = adda_x + addb_x + ci_x;
5050 uint32 addqt_y = adda_y + addb_y + ci_y;
5051 co_x = ((addqt_x & 0x10000) && a1fracldi ? 1 : 0);
5052 co_y = ((addqt_y & 0x10000) && a1fracldi ? 1 : 0);
5053 //////////////////////////////////////////////////////////////////////////////////////
5055 /* Mask low bits of X to 0 if required */
5057 /*Masksel := D38H (unused[0], masksel[0..4], maskbit[5], unused[1], modx[0..2]);
5059 Maskbit[0-4] := OR2 (maskbit[0-4], masksel[0-4], maskbit[1-5]);
5061 Mask[0-5] := MX2 (addq_x[0-5], addqt_x[0-5], zero, maskbit[0-5]);
5063 Addq_x := JOIN (addq_x, addq_x[0..5], addqt_x[6..15]);
5064 Addq_y := JOIN (addq_y, addq_y[0..15]);*/
5066 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5067 int16 mask[8] = { 0xFFFF, 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, 0xFFE0, 0xFFC0, 0x0000 };
5068 addq_x = addqt_x & mask[modx];
5069 addq_y = addqt_y & 0xFFFF;
5070 //////////////////////////////////////////////////////////////////////////////////////
5072 //Unused[0-1] := DUMMY (unused[0-1]);
5079 wdata[0..63] // co-processor write data bus
5081 dcomp[0..7] // data byte equal flags
5082 srcd[0..7] // bits to use for bit to byte expansion
5083 zcomp[0..3] // output from Z comparators
5085 a1_x[0..1] // low two bits of A1 X pointer
5086 big_pix // pixel organisation is big-endian
5087 blitter_active // blitter is active
5088 clk // co-processor clock
5089 cmpdst // compare dest rather than source
5090 colorld // load the pattern color fields
5091 daddasel[0..2] // data adder input A selection
5092 daddbsel[0..3] // data adder input B selection
5093 daddmode[0..2] // data adder mode
5094 daddq_sel // select adder output vs. GPU data
5095 data[0..63] // co-processor read data bus
5096 data_ena // enable write data
5097 data_sel[0..1] // select data to write
5098 dbinh\[0..7] // byte oriented changed data inhibits
5099 dend[0..5] // end of changed write data zone
5100 dpipe[0..1] // load computed data pipe-line latch
5101 dstart[0..5] // start of changed write data zone
5102 dstdld[0..1] // dest data load (two halves)
5103 dstzld[0..1] // dest zed load (two halves)
5104 ext_int // enable extended precision intensity calculations
5105 INT32/ gpu_din // GPU data bus
5106 iincld // I increment load
5107 iincldx // alternate I increment load
5108 init_if // initialise I fraction phase
5109 init_ii // initialise I integer phase
5110 init_zf // initialise Z fraction phase
5111 intld[0..3] // computed intensities load
5112 istepadd // intensity step integer add
5113 istepfadd // intensity step fraction add
5114 istepld // I step load
5115 istepdld // I step delta load
5116 lfu_func[0..3] // LFU function code
5117 patdadd // pattern data gouraud add
5118 patdld[0..1] // pattern data load (two halves)
5119 pdsel[0..1] // select pattern data type
5120 phrase_mode // phrase write mode
5121 reload // transfer contents of double buffers
5122 reset\ // system reset
5123 srcd1ld[0..1] // source register 1 load (two halves)
5124 srcdread // source data read load enable
5125 srczread // source zed read load enable
5126 srcshift[0..5] // source alignment shift
5127 srcz1ld[0..1] // source zed 1 load (two halves)
5128 srcz2add // zed fraction gouraud add
5129 srcz2ld[0..1] // source zed 2 load (two halves)
5130 textrgb // texture mapping in RGB mode
5131 txtd[0..63] // data from the texture unit
5132 zedld[0..3] // computed zeds load
5133 zincld // Z increment load
5134 zmode[0..2] // Z comparator mode
5135 zpipe[0..1] // load computed zed pipe-line latch
5136 zstepadd // zed step integer add
5137 zstepfadd // zed step fraction add
5138 zstepld // Z step load
5139 zstepdld // Z step delta load
5143 void DATA (uint64 &wdata, uint8 &dcomp, uint8 &zcomp, bool &nowrite,
5144 bool big_pix, bool cmpdst, uint8 daddasel, uint8 daddbsel, uint8 daddmode, bool daddq_sel, uint8 data_sel,
5145 uint8 dbinh, uint8 dend, uint8 dstart, uint64 dstd, uint32 iinc, uint8 lfu_func, uint64 patd, bool patdadd,
5146 bool phrase_mode, uint64 srcd, bool srcdread, bool srczread, bool srcz2add, uint8 zmode,
5147 bool bcompen, bool bkgwren, bool dcompen, uint8 icount, uint8 pixsize)
5150 Stuff we absolutely *need* to have passed in/out:
5152 patdadd, dstd, srcd, patd, daddasel, daddbsel, daddmode, iinc, srcz1, srcz2, big_pix, phrase_mode, cmpdst
5154 changed patd (wdata I guess...)
5157 // Source data registers
5159 /*Data_src := DATA_SRC (srcdlo, srcdhi, srcz[0..1], srczo[0..1], srczp[0..1], srcz1[0..1], srcz2[0..1], big_pix,
5160 clk, gpu_din, intld[0..3], local_data0, local_data1, srcd1ld[0..1], srcdread, srczread, srcshift[0..5],
5161 srcz1ld[0..1], srcz2add, srcz2ld[0..1], zedld[0..3], zpipe[0..1]);
5162 Srcd[0-7] := JOIN (srcd[0-7], srcdlo{0-7});
5163 Srcd[8-31] := JOIN (srcd[8-31], srcdlo{8-31});
5164 Srcd[32-63] := JOIN (srcd[32-63], srcdhi{0-31});*/
5166 // Destination data registers
5168 /*Data_dst := DATA_DST (dstd[0..63], dstz[0..1], clk, dstdld[0..1], dstzld[0..1], load_data[0..1]);
5169 Dstdlo := JOIN (dstdlo, dstd[0..31]);
5170 Dstdhi := JOIN (dstdhi, dstd[32..63]);*/
5172 // Pattern and Color data registers
5174 // Looks like this is simply another register file for the pattern data registers. No adding or anything funky
5175 // going on. Note that patd & patdv will output the same info.
5176 // Patdldl/h (patdld[0..1]) can select the local_data bus to overwrite the current pattern data...
5177 // Actually, it can be either patdld OR patdadd...!
5178 /*Data_pat := DATA_PAT (colord[0..15], int0dp[8..10], int1dp[8..10], int2dp[8..10], int3dp[8..10], mixsel[0..2],
5179 patd[0..63], patdv[0..1], clk, colorld, dpipe[0], ext_int, gpu_din, intld[0..3], local_data0, local_data1,
5180 patdadd, patdld[0..1], reload, reset\);
5181 Patdlo := JOIN (patdlo, patd[0..31]);
5182 Patdhi := JOIN (patdhi, patd[32..63]);*/
5184 // Multiplying data Mixer (NOT IN JAGUAR I)
5186 /*Datamix := DATAMIX (patdo[0..1], clk, colord[0..15], dpipe[1], dstd[0..63], int0dp[8..10], int1dp[8..10],
5187 int2dp[8..10], int3dp[8..10], mixsel[0..2], patd[0..63], pdsel[0..1], srcd[0..63], textrgb, txtd[0..63]);*/
5189 // Logic function unit
5191 /*Lfu := LFU (lfu[0..1], srcdlo, srcdhi, dstdlo, dstdhi, lfu_func[0..3]);*/
5192 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5193 uint64 funcmask[2] = { 0, 0xFFFFFFFFFFFFFFFFLL };
5194 uint64 func0 = funcmask[lfu_func & 0x01];
5195 uint64 func1 = funcmask[(lfu_func >> 1) & 0x01];
5196 uint64 func2 = funcmask[(lfu_func >> 2) & 0x01];
5197 uint64 func3 = funcmask[(lfu_func >> 3) & 0x01];
5198 uint64 lfu = (~srcd & ~dstd & func0) | (~srcd & dstd & func1) | (srcd & ~dstd & func2) | (srcd & dstd & func3);
5199 //////////////////////////////////////////////////////////////////////////////////////
5201 // Increment and Step Registers
5203 // Does it do anything without the step add lines? Check it!
5204 // No. This is pretty much just a register file without the Jaguar II lines...
5205 /*Inc_step := INC_STEP (iinc, istep[0..31], zinc, zstep[0..31], clk, ext_int, gpu_din, iincld, iincldx, istepadd,
5206 istepfadd, istepld, istepdld, reload, reset\, zincld, zstepadd, zstepfadd, zstepld, zstepdld);
5207 Istep := JOIN (istep, istep[0..31]);
5208 Zstep := JOIN (zstep, zstep[0..31]);*/
5210 // Pixel data comparator
5212 /*Datacomp := DATACOMP (dcomp[0..7], cmpdst, dstdlo, dstdhi, patdlo, patdhi, srcdlo, srcdhi);*/
5213 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5215 uint64 cmpd = patd ^ (cmpdst ? dstd : srcd);
5217 if ((cmpd & 0x00000000000000FFLL) == 0)
5219 if ((cmpd & 0x000000000000FF00LL) == 0)
5221 if ((cmpd & 0x0000000000FF0000LL) == 0)
5223 if ((cmpd & 0x00000000FF000000LL) == 0)
5225 if ((cmpd & 0x000000FF00000000LL) == 0)
5227 if ((cmpd & 0x0000FF0000000000LL) == 0)
5229 if ((cmpd & 0x00FF000000000000LL) == 0)
5231 if ((cmpd & 0xFF00000000000000LL) == 0)
5233 // We'll do the comparison/bit/byte inhibits here, since that's they way it happens
5234 // in the real thing (dcomp goes out to COMP_CTRL and back into DATA through dbinh)...
5238 COMP_CTRL(dbinht, nowrite,
5239 bcompen, true/*big_pix*/, bkgwren, dcomp, dcompen, icount, pixsize, phrase_mode, srcd & 0xFF, 0);//zcomp);
5243 //////////////////////////////////////////////////////////////////////////////////////
5245 // Zed comparator for Z-buffer operations
5247 /*Zedcomp := ZEDCOMP (zcomp[0..3], srczp[0..1], dstz[0..1], zmode[0..2]);*/
5248 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5250 //////////////////////////////////////////////////////////////////////////////////////
5253 // The data initializer - allows all four initial values to be computed from one (NOT IN JAGUAR I)
5255 /*Datinit := DATINIT (initcin[0..3], initinc[0..63], initpix[0..15], a1_x[0..1], big_pix, clk, iinc, init_if, init_ii,
5256 init_zf, istep[0..31], zinc, zstep[0..31]);*/
5258 // Adder array for Z and intensity increments
5260 /*Addarray := ADDARRAY (addq[0..3], clk, daddasel[0..2], daddbsel[0..3], daddmode[0..2], dstdlo, dstdhi, iinc,
5261 initcin[0..3], initinc[0..63], initpix[0..15], istep, patdv[0..1], srcdlo, srcdhi, srcz1[0..1],
5262 srcz2[0..1], reset\, zinc, zstep);*/
5263 /*void ADDARRAY(uint16 * addq, uint8 daddasel, uint8 daddbsel, uint8 daddmode,
5264 uint64 dstd, uint32 iinc, uint8 initcin[], uint64 initinc, uint16 initpix,
5265 uint32 istep, uint64 patd, uint64 srcd, uint64 srcz1, uint64 srcz2,
5266 uint32 zinc, uint32 zstep)*/
5267 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5269 uint8 initcin[4] = { 0, 0, 0, 0 };
5270 ADDARRAY(addq, daddasel, daddbsel, daddmode, dstd, iinc, initcin, 0, 0, 0, patd, srcd, 0, 0, 0, 0);
5272 //This is normally done asynchronously above (thru local_data) when in patdadd mode...
5274 patd = ((uint64)addq[3] << 48) | ((uint64)addq[2] << 32) | ((uint64)addq[1] << 16) | (uint64)addq[0];
5275 //////////////////////////////////////////////////////////////////////////////////////
5277 // Local data bus multiplexer
5279 /*Local_mux := LOCAL_MUX (local_data[0..1], load_data[0..1],
5280 addq[0..3], gpu_din, data[0..63], blitter_active, daddq_sel);
5281 Local_data0 := JOIN (local_data0, local_data[0]);
5282 Local_data1 := JOIN (local_data1, local_data[1]);*/
5283 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5284 //////////////////////////////////////////////////////////////////////////////////////
5286 // Data output multiplexer and tri-state drive
5288 /*Data_mux := DATA_MUX (wdata[0..63], addq[0..3], big_pix, dstdlo, dstdhi, dstz[0..1], data_sel[0..1], data_ena,
5289 dstart[0..5], dend[0..5], dbinh\[0..7], lfu[0..1], patdo[0..1], phrase_mode, srczo[0..1]);*/
5290 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5291 // NOTE: patdo comes from DATAMIX and can be considered the same as patd for Jaguar I
5293 //////////////////////////////////////////////////////////////////////////////////////
5297 wdata[0..63] // co-processor rwrite data bus
5300 big_pix // Pixel organisation is big-endian
5305 data_sel[0..1] // source of write data
5306 data_ena // enable write data onto read/write bus
5307 dstart[0..5] // start of changed write data
5308 dend[0..5] // end of changed write data
5309 dbinh\[0..7] // byte oriented changed data inhibits
5312 phrase_mode // phrase write mode
5317 /*INT32/ addql[0..1], ddatlo, ddathi zero32
5321 Phrase_mode\ := INV1 (phrase_mode\, phrase_mode);
5322 Zero := TIE0 (zero);
5323 Zero32 := JOIN (zero32, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero);*/
5325 /* Generate a changed data mask */
5327 /*Edis := OR6 (edis\, dend[0..5]);
5328 Ecoarse := DECL38E (e_coarse\[0..7], dend[3..5], edis\);
5329 E_coarse[0] := INV1 (e_coarse[0], e_coarse\[0]);
5330 Efine := DECL38E (unused[0], e_fine\[1..7], dend[0..2], e_coarse[0]);*/
5331 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5332 uint8 decl38e[2][8] = { { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
5333 { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } };
5334 uint8 dech38[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
5335 uint8 dech38el[2][8] = { { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
5336 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } };
5338 int en = (dend & 0x3F ? 1 : 0);
5339 uint8 e_coarse = decl38e[en][(dend & 0x38) >> 3]; // Actually, this is e_coarse inverted...
5340 uint8 e_fine = decl38e[(e_coarse & 0x01) ^ 0x01][dend & 0x07];
5342 //////////////////////////////////////////////////////////////////////////////////////
5344 /*Scoarse := DECH38 (s_coarse[0..7], dstart[3..5]);
5345 Sfen\ := INV1 (sfen\, s_coarse[0]);
5346 Sfine := DECH38EL (s_fine[0..7], dstart[0..2], sfen\);*/
5347 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5348 uint8 s_coarse = dech38[(dstart & 0x38) >> 3];
5349 uint8 s_fine = dech38el[(s_coarse & 0x01) ^ 0x01][dstart & 0x07];
5350 //////////////////////////////////////////////////////////////////////////////////////
5352 /*Maskt[0] := BUF1 (maskt[0], s_fine[0]);
5353 Maskt[1-7] := OAN1P (maskt[1-7], maskt[0-6], s_fine[1-7], e_fine\[1-7]);*/
5354 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5355 uint16 maskt = s_fine & 0x0001;
5356 maskt |= (((maskt & 0x0001) || (s_fine & 0x02)) && (e_fine & 0x02) ? 0x0002 : 0x0000);
5357 maskt |= (((maskt & 0x0002) || (s_fine & 0x04)) && (e_fine & 0x04) ? 0x0004 : 0x0000);
5358 maskt |= (((maskt & 0x0004) || (s_fine & 0x08)) && (e_fine & 0x08) ? 0x0008 : 0x0000);
5359 maskt |= (((maskt & 0x0008) || (s_fine & 0x10)) && (e_fine & 0x10) ? 0x0010 : 0x0000);
5360 maskt |= (((maskt & 0x0010) || (s_fine & 0x20)) && (e_fine & 0x20) ? 0x0020 : 0x0000);
5361 maskt |= (((maskt & 0x0020) || (s_fine & 0x40)) && (e_fine & 0x40) ? 0x0040 : 0x0000);
5362 maskt |= (((maskt & 0x0040) || (s_fine & 0x80)) && (e_fine & 0x80) ? 0x0080 : 0x0000);
5363 //////////////////////////////////////////////////////////////////////////////////////
5365 /* Produce a look-ahead on the ripple carry:
5366 masktla = s_coarse[0] . /e_coarse[0] */
5367 /*Masktla := AN2 (masktla, s_coarse[0], e_coarse\[0]);
5368 Maskt[8] := OAN1P (maskt[8], masktla, s_coarse[1], e_coarse\[1]);
5369 Maskt[9-14] := OAN1P (maskt[9-14], maskt[8-13], s_coarse[2-7], e_coarse\[2-7]);*/
5370 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5371 maskt |= (((s_coarse & e_coarse & 0x01) || (s_coarse & 0x02)) && (e_coarse & 0x02) ? 0x0100 : 0x0000);
5372 maskt |= (((maskt & 0x0100) || (s_coarse & 0x04)) && (e_coarse & 0x04) ? 0x0200 : 0x0000);
5373 maskt |= (((maskt & 0x0200) || (s_coarse & 0x08)) && (e_coarse & 0x08) ? 0x0400 : 0x0000);
5374 maskt |= (((maskt & 0x0400) || (s_coarse & 0x10)) && (e_coarse & 0x10) ? 0x0800 : 0x0000);
5375 maskt |= (((maskt & 0x0800) || (s_coarse & 0x20)) && (e_coarse & 0x20) ? 0x1000 : 0x0000);
5376 maskt |= (((maskt & 0x1000) || (s_coarse & 0x40)) && (e_coarse & 0x40) ? 0x2000 : 0x0000);
5377 maskt |= (((maskt & 0x2000) || (s_coarse & 0x80)) && (e_coarse & 0x80) ? 0x4000 : 0x0000);
5378 //////////////////////////////////////////////////////////////////////////////////////
5380 /* The bit terms are mirrored for big-endian pixels outside phrase
5381 mode. The byte terms are mirrored for big-endian pixels in phrase
5384 /*Mirror_bit := AN2M (mir_bit, phrase_mode\, big_pix);
5385 Mirror_byte := AN2H (mir_byte, phrase_mode, big_pix);
5387 Masktb[14] := BUF1 (masktb[14], maskt[14]);
5388 Masku[0] := MX4 (masku[0], maskt[0], maskt[7], maskt[14], zero, mir_bit, mir_byte);
5389 Masku[1] := MX4 (masku[1], maskt[1], maskt[6], maskt[14], zero, mir_bit, mir_byte);
5390 Masku[2] := MX4 (masku[2], maskt[2], maskt[5], maskt[14], zero, mir_bit, mir_byte);
5391 Masku[3] := MX4 (masku[3], maskt[3], maskt[4], masktb[14], zero, mir_bit, mir_byte);
5392 Masku[4] := MX4 (masku[4], maskt[4], maskt[3], masktb[14], zero, mir_bit, mir_byte);
5393 Masku[5] := MX4 (masku[5], maskt[5], maskt[2], masktb[14], zero, mir_bit, mir_byte);
5394 Masku[6] := MX4 (masku[6], maskt[6], maskt[1], masktb[14], zero, mir_bit, mir_byte);
5395 Masku[7] := MX4 (masku[7], maskt[7], maskt[0], masktb[14], zero, mir_bit, mir_byte);
5396 Masku[8] := MX2 (masku[8], maskt[8], maskt[13], mir_byte);
5397 Masku[9] := MX2 (masku[9], maskt[9], maskt[12], mir_byte);
5398 Masku[10] := MX2 (masku[10], maskt[10], maskt[11], mir_byte);
5399 Masku[11] := MX2 (masku[11], maskt[11], maskt[10], mir_byte);
5400 Masku[12] := MX2 (masku[12], maskt[12], maskt[9], mir_byte);
5401 Masku[13] := MX2 (masku[13], maskt[13], maskt[8], mir_byte);
5402 Masku[14] := MX2 (masku[14], maskt[14], maskt[0], mir_byte);*/
5403 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5404 bool mir_bit = true/*big_pix*/ && !phrase_mode;
5405 bool mir_byte = true/*big_pix*/ && phrase_mode;
5406 uint16 masku = maskt;
5411 masku |= (maskt >> 7) & 0x0001;
5412 masku |= (maskt >> 5) & 0x0002;
5413 masku |= (maskt >> 3) & 0x0004;
5414 masku |= (maskt >> 1) & 0x0008;
5415 masku |= (maskt << 1) & 0x0010;
5416 masku |= (maskt << 3) & 0x0020;
5417 masku |= (maskt << 5) & 0x0040;
5418 masku |= (maskt << 7) & 0x0080;
5424 masku |= (maskt >> 14) & 0x0001;
5425 masku |= (maskt >> 13) & 0x0002;
5426 masku |= (maskt >> 12) & 0x0004;
5427 masku |= (maskt >> 11) & 0x0008;
5428 masku |= (maskt >> 10) & 0x0010;
5429 masku |= (maskt >> 9) & 0x0020;
5430 masku |= (maskt >> 8) & 0x0040;
5431 masku |= (maskt >> 7) & 0x0080;
5433 masku |= (maskt >> 5) & 0x0100;
5434 masku |= (maskt >> 3) & 0x0200;
5435 masku |= (maskt >> 1) & 0x0400;
5436 masku |= (maskt << 1) & 0x0800;
5437 masku |= (maskt << 3) & 0x1000;
5438 masku |= (maskt << 5) & 0x2000;
5439 masku |= (maskt << 7) & 0x4000;
5441 //////////////////////////////////////////////////////////////////////////////////////
5443 /* The maskt terms define the area for changed data, but the byte
5444 inhibit terms can override these */
5446 /*Mask[0-7] := AN2 (mask[0-7], masku[0-7], dbinh\[0]);
5447 Mask[8-14] := AN2H (mask[8-14], masku[8-14], dbinh\[1-7]);*/
5448 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5449 uint16 mask = masku & (!(dbinh & 0x01) ? 0xFFFF : 0xFF00);
5450 mask &= ~(((uint16)dbinh & 0x00FE) << 7);
5451 //////////////////////////////////////////////////////////////////////////////////////
5453 /*Addql[0] := JOIN (addql[0], addq[0..1]);
5454 Addql[1] := JOIN (addql[1], addq[2..3]);
5456 Dsel0b[0-1] := BUF8 (dsel0b[0-1], data_sel[0]);
5457 Dsel1b[0-1] := BUF8 (dsel1b[0-1], data_sel[1]);
5458 Ddatlo := MX4 (ddatlo, patd[0], lfu[0], addql[0], zero32, dsel0b[0], dsel1b[0]);
5459 Ddathi := MX4 (ddathi, patd[1], lfu[1], addql[1], zero32, dsel0b[1], dsel1b[1]);*/
5460 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5464 dmux[2] = ((uint64)addq[3] << 48) | ((uint64)addq[2] << 32) | ((uint64)addq[1] << 16) | (uint64)addq[0];
5466 uint64 ddat = dmux[data_sel];
5467 //////////////////////////////////////////////////////////////////////////////////////
5469 /*Zed_sel := AN2 (zed_sel, data_sel[0..1]);
5470 Zed_selb[0-1] := BUF8 (zed_selb[0-1], zed_sel);
5472 Dat[0-7] := MX4 (dat[0-7], dstdlo{0-7}, ddatlo{0-7}, dstzlo{0-7}, srczlo{0-7}, mask[0-7], zed_selb[0]);
5473 Dat[8-15] := MX4 (dat[8-15], dstdlo{8-15}, ddatlo{8-15}, dstzlo{8-15}, srczlo{8-15}, mask[8], zed_selb[0]);
5474 Dat[16-23] := MX4 (dat[16-23], dstdlo{16-23}, ddatlo{16-23}, dstzlo{16-23}, srczlo{16-23}, mask[9], zed_selb[0]);
5475 Dat[24-31] := MX4 (dat[24-31], dstdlo{24-31}, ddatlo{24-31}, dstzlo{24-31}, srczlo{24-31}, mask[10], zed_selb[0]);
5476 Dat[32-39] := MX4 (dat[32-39], dstdhi{0-7}, ddathi{0-7}, dstzhi{0-7}, srczhi{0-7}, mask[11], zed_selb[1]);
5477 Dat[40-47] := MX4 (dat[40-47], dstdhi{8-15}, ddathi{8-15}, dstzhi{8-15}, srczhi{8-15}, mask[12], zed_selb[1]);
5478 Dat[48-55] := MX4 (dat[48-55], dstdhi{16-23}, ddathi{16-23}, dstzhi{16-23}, srczhi{16-23}, mask[13], zed_selb[1]);
5479 Dat[56-63] := MX4 (dat[56-63], dstdhi{24-31}, ddathi{24-31}, dstzhi{24-31}, srczhi{24-31}, mask[14], zed_selb[1]);*/
5480 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5481 wdata = ((ddat & mask) | (dstd & ~mask)) & 0x00000000000000FFLL;
5482 wdata |= (mask & 0x0100 ? ddat : dstd) & 0x000000000000FF00LL;
5483 wdata |= (mask & 0x0200 ? ddat : dstd) & 0x0000000000FF0000LL;
5484 wdata |= (mask & 0x0400 ? ddat : dstd) & 0x00000000FF000000LL;
5485 wdata |= (mask & 0x0800 ? ddat : dstd) & 0x000000FF00000000LL;
5486 wdata |= (mask & 0x1000 ? ddat : dstd) & 0x0000FF0000000000LL;
5487 wdata |= (mask & 0x2000 ? ddat : dstd) & 0x00FF000000000000LL;
5488 wdata |= (mask & 0x4000 ? ddat : dstd) & 0xFF00000000000000LL;
5489 //////////////////////////////////////////////////////////////////////////////////////
5491 /*Data_enab[0-1] := BUF8 (data_enab[0-1], data_ena);
5492 Datadrv[0-31] := TS (wdata[0-31], dat[0-31], data_enab[0]);
5493 Datadrv[32-63] := TS (wdata[32-63], dat[32-63], data_enab[1]);
5495 Unused[0] := DUMMY (unused[0]);
5500 /** COMP_CTRL - Comparator output control logic *****************
5502 This block is responsible for taking the comparator outputs and
5503 using them as appropriate to inhibit writes. Two methods are
5504 supported for inhibiting write data:
5506 - suppression of the inner loop controlled write operation
5507 - a set of eight byte inhibit lines to write back dest data
5509 The first technique is used in pixel oriented modes, the second in
5510 phrase mode, but the phrase mode form is only applicable to eight
5511 and sixteen bit pixel modes.
5513 Writes can be suppressed by data being equal, by the Z comparator
5514 conditions being met, or by the bit to pixel expansion scheme.
5516 Pipe-lining issues: the data derived comparator outputs are stable
5517 until the next data read, well after the affected write from this
5518 operation. However, the inner counter bits can count immediately
5519 before the ack for the last write. Therefore, it is necessary to
5520 delay bcompbit select terms by one inner loop pipe-line stage,
5521 when generating the select for the data control - the output is
5522 delayed one further tick to give it write data timing (2/34).
5524 There is also a problem with computed data - the new values are
5525 calculated before the write associated with the old value has been
5526 performed. The is taken care of within the zed comparator by
5527 pipe-lining the comparator inputs where appropriate.
5530 //#define LOG_COMP_CTRL
5532 dbinh\[0..7] // destination byte inhibit lines
5533 nowrite // suppress inner loop write operation
5535 bcompen // bit selector inhibit enable
5536 big_pix // pixels are big-endian
5537 bkgwren // enable dest data write in pix inhibit
5538 clk // co-processor clock
5539 dcomp[0..7] // output of data byte comparators
5540 dcompen // data comparator inhibit enable
5541 icount[0..2] // low bits of inner count
5542 pixsize[0..2] // destination pixel size
5543 phrase_mode // phrase write mode
5544 srcd[0..7] // bits to use for bit to byte expansion
5545 step_inner // inner loop advance
5546 zcomp[0..3] // output of word zed comparators
5548 void COMP_CTRL(uint8 &dbinh, bool &nowrite,
5549 bool bcompen, bool big_pix, bool bkgwren, uint8 dcomp, bool dcompen, uint8 icount,
5550 uint8 pixsize, bool phrase_mode, uint8 srcd, uint8 zcomp)
5554 /*Bkgwren\ := INV1 (bkgwren\, bkgwren);
5555 Phrase_mode\ := INV1 (phrase_mode\, phrase_mode);
5556 Pixsize\[0-2] := INV2 (pixsize\[0-2], pixsize[0-2]);*/
5558 /* The bit comparator bits are derived from the source data, which
5559 will have been suitably aligned for phrase mode. The contents of
5560 the inner counter are used to select which bit to use.
5562 When not in phrase mode the inner count value is used to select
5563 one bit. It is assumed that the count has already occurred, so,
5564 7 selects bit 0, etc. In big-endian pixel mode, this turns round,
5565 so that a count of 7 selects bit 7.
5567 In phrase mode, the eight bits are used directly, and this mode is
5568 only applicable to 8-bit pixel mode (2/34) */
5570 /*Bcompselt[0-2] := EO (bcompselt[0-2], icount[0-2], big_pix);
5571 Bcompbit := MX8 (bcompbit, srcd[7], srcd[6], srcd[5],
5572 srcd[4], srcd[3], srcd[2], srcd[1], srcd[0], bcompselt[0..2]);
5573 Bcompbit\ := INV1 (bcompbit\, bcompbit);*/
5574 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5575 #ifdef LOG_COMP_CTRL
5578 printf("\n [bcompen=%s dcompen=%s phrase_mode=%s bkgwren=%s dcomp=%02X zcomp=%02X]", (bcompen ? "T" : "F"), (dcompen ? "T" : "F"), (phrase_mode ? "T" : "F"), (bkgwren ? "T" : "F"), dcomp, zcomp);
5583 uint8 bcompselt = (big_pix ? ~icount : icount) & 0x07;
5584 uint8 bitmask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 };
5585 bool bcompbit = srcd & bitmask[bcompselt];
5586 //////////////////////////////////////////////////////////////////////////////////////
5588 /* pipe-line the count */
5589 /*Bcompsel[0-2] := FDSYNC (bcompsel[0-2], bcompselt[0-2], step_inner, clk);
5590 Bcompbt := MX8 (bcompbitpt, srcd[7], srcd[6], srcd[5],
5591 srcd[4], srcd[3], srcd[2], srcd[1], srcd[0], bcompsel[0..2]);
5592 Bcompbitp := FD1Q (bcompbitp, bcompbitpt, clk);
5593 Bcompbitp\ := INV1 (bcompbitp\, bcompbitp);*/
5595 /* For pixel mode, generate the write inhibit signal for all modes
5596 on bit inhibit, for 8 and 16 bit modes on comparator inhibit, and
5597 for 16 bit mode on Z inhibit
5599 Nowrite = bcompen . /bcompbit . /phrase_mode
5600 + dcompen . dcomp[0] . /phrase_mode . pixsize = 011
5601 + dcompen . dcomp[0..1] . /phrase_mode . pixsize = 100
5602 + zcomp[0] . /phrase_mode . pixsize = 100
5605 /*Nowt0 := NAN3 (nowt[0], bcompen, bcompbit\, phrase_mode\);
5606 Nowt1 := ND6 (nowt[1], dcompen, dcomp[0], phrase_mode\, pixsize\[2], pixsize[0..1]);
5607 Nowt2 := ND7 (nowt[2], dcompen, dcomp[0..1], phrase_mode\, pixsize[2], pixsize\[0..1]);
5608 Nowt3 := NAN5 (nowt[3], zcomp[0], phrase_mode\, pixsize[2], pixsize\[0..1]);
5609 Nowt4 := NAN4 (nowt[4], nowt[0..3]);
5610 Nowrite := AN2 (nowrite, nowt[4], bkgwren\);*/
5611 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5612 nowrite = ((bcompen && !bcompbit && !phrase_mode)
5613 || (dcompen && (dcomp & 0x01) && !phrase_mode && (pixsize == 3))
5614 || (dcompen && ((dcomp & 0x03) == 0x03) && !phrase_mode && (pixsize == 4))
5615 || ((zcomp & 0x01) && !phrase_mode && (pixsize == 4)))
5617 //////////////////////////////////////////////////////////////////////////////////////
5619 /*Winht := NAN3 (winht, bcompen, bcompbitp\, phrase_mode\);
5620 Winhibit := NAN4 (winhibit, winht, nowt[1..3]);*/
5621 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5622 //This is the same as above, but with bcompbit delayed one tick and called 'winhibit'
5623 //Small difference: Besides the pipeline effect, it's also not using !bkgwren...
5624 // bool winhibit = (bcompen && !
5625 bool winhibit = (bcompen && !bcompbit && !phrase_mode)
5626 || (dcompen && (dcomp & 0x01) && !phrase_mode && (pixsize == 3))
5627 || (dcompen && ((dcomp & 0x03) == 0x03) && !phrase_mode && (pixsize == 4))
5628 || ((zcomp & 0x01) && !phrase_mode && (pixsize == 4));
5629 #ifdef LOG_COMP_CTRL
5632 printf("[nw=%s wi=%s]", (nowrite ? "T" : "F"), (winhibit ? "T" : "F"));
5636 //////////////////////////////////////////////////////////////////////////////////////
5638 /* For phrase mode, generate the byte inhibit signals for eight bit
5639 mode 011, or sixteen bit mode 100
5640 dbinh\[0] = pixsize[2] . zcomp[0]
5641 + pixsize[2] . dcomp[0] . dcomp[1] . dcompen
5642 + /pixsize[2] . dcomp[0] . dcompen
5643 + /srcd[0] . bcompen
5645 Inhibits 0-3 are also used when not in phrase mode to write back
5649 /*Srcd\[0-7] := INV1 (srcd\[0-7], srcd[0-7]);
5651 Di0t0 := NAN2H (di0t[0], pixsize[2], zcomp[0]);
5652 Di0t1 := NAN4H (di0t[1], pixsize[2], dcomp[0..1], dcompen);
5653 Di0t2 := NAN2 (di0t[2], srcd\[0], bcompen);
5654 Di0t3 := NAN3 (di0t[3], pixsize\[2], dcomp[0], dcompen);
5655 Di0t4 := NAN4 (di0t[4], di0t[0..3]);
5656 Dbinh[0] := ANR1P (dbinh\[0], di0t[4], phrase_mode, winhibit);*/
5657 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5659 bool di0t0_1 = ((pixsize & 0x04) && (zcomp & 0x01))
5660 || ((pixsize & 0x04) && (dcomp & 0x01) && (dcomp & 0x02) && dcompen);
5661 bool di0t4 = di0t0_1
5662 || (!(srcd & 0x01) && bcompen)
5663 || (!(pixsize & 0x04) && (dcomp & 0x01) && dcompen);
5664 dbinh |= (!((di0t4 && phrase_mode) || winhibit) ? 0x01 : 0x00);
5665 #ifdef LOG_COMP_CTRL
5668 printf("[di0t0_1=%s di0t4=%s]", (di0t0_1 ? "T" : "F"), (di0t4 ? "T" : "F"));
5672 //////////////////////////////////////////////////////////////////////////////////////
5674 /*Di1t0 := NAN3 (di1t[0], pixsize\[2], dcomp[1], dcompen);
5675 Di1t1 := NAN2 (di1t[1], srcd\[1], bcompen);
5676 Di1t2 := NAN4 (di1t[2], di0t[0..1], di1t[0..1]);
5677 Dbinh[1] := ANR1 (dbinh\[1], di1t[2], phrase_mode, winhibit);*/
5678 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5679 bool di1t2 = di0t0_1
5680 || (!(srcd & 0x02) && bcompen)
5681 || (!(pixsize & 0x04) && (dcomp & 0x02) && dcompen);
5682 dbinh |= (!((di1t2 && phrase_mode) || winhibit) ? 0x02 : 0x00);
5683 #ifdef LOG_COMP_CTRL
5686 printf("[di1t2=%s]", (di1t2 ? "T" : "F"));
5690 //////////////////////////////////////////////////////////////////////////////////////
5692 /*Di2t0 := NAN2H (di2t[0], pixsize[2], zcomp[1]);
5693 Di2t1 := NAN4H (di2t[1], pixsize[2], dcomp[2..3], dcompen);
5694 Di2t2 := NAN2 (di2t[2], srcd\[2], bcompen);
5695 Di2t3 := NAN3 (di2t[3], pixsize\[2], dcomp[2], dcompen);
5696 Di2t4 := NAN4 (di2t[4], di2t[0..3]);
5697 Dbinh[2] := ANR1 (dbinh\[2], di2t[4], phrase_mode, winhibit);*/
5698 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5699 //[bcompen=F dcompen=T phrase_mode=T bkgwren=F][nw=F wi=F]
5700 //[di0t0_1=F di0t4=F][di1t2=F][di2t0_1=T di2t4=T][di3t2=T][di4t0_1=F di2t4=F][di5t2=F][di6t0_1=F di6t4=F][di7t2=F]
5701 //[dcomp=$00 dbinh=$0C][7804780400007804] (icount=0005, inc=4)
5702 bool di2t0_1 = ((pixsize & 0x04) && (zcomp & 0x02))
5703 || ((pixsize & 0x04) && (dcomp & 0x04) && (dcomp & 0x08) && dcompen);
5704 bool di2t4 = di2t0_1
5705 || (!(srcd & 0x04) && bcompen)
5706 || (!(pixsize & 0x04) && (dcomp & 0x04) && dcompen);
5707 dbinh |= (!((di2t4 && phrase_mode) || winhibit) ? 0x04 : 0x00);
5708 #ifdef LOG_COMP_CTRL
5711 printf("[di2t0_1=%s di2t4=%s]", (di2t0_1 ? "T" : "F"), (di2t4 ? "T" : "F"));
5715 //////////////////////////////////////////////////////////////////////////////////////
5717 /*Di3t0 := NAN3 (di3t[0], pixsize\[2], dcomp[3], dcompen);
5718 Di3t1 := NAN2 (di3t[1], srcd\[3], bcompen);
5719 Di3t2 := NAN4 (di3t[2], di2t[0..1], di3t[0..1]);
5720 Dbinh[3] := ANR1 (dbinh\[3], di3t[2], phrase_mode, winhibit);*/
5721 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5722 bool di3t2 = di2t0_1
5723 || (!(srcd & 0x08) && bcompen)
5724 || (!(pixsize & 0x04) && (dcomp & 0x08) && dcompen);
5725 dbinh |= (!((di3t2 && phrase_mode) || winhibit) ? 0x08 : 0x00);
5726 #ifdef LOG_COMP_CTRL
5729 printf("[di3t2=%s]", (di3t2 ? "T" : "F"));
5733 //////////////////////////////////////////////////////////////////////////////////////
5735 /*Di4t0 := NAN2H (di4t[0], pixsize[2], zcomp[2]);
5736 Di4t1 := NAN4H (di4t[1], pixsize[2], dcomp[4..5], dcompen);
5737 Di4t2 := NAN2 (di4t[2], srcd\[4], bcompen);
5738 Di4t3 := NAN3 (di4t[3], pixsize\[2], dcomp[4], dcompen);
5739 Di4t4 := NAN4 (di4t[4], di4t[0..3]);
5740 Dbinh[4] := NAN2 (dbinh\[4], di4t[4], phrase_mode);*/
5741 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5742 bool di4t0_1 = ((pixsize & 0x04) && (zcomp & 0x04))
5743 || ((pixsize & 0x04) && (dcomp & 0x10) && (dcomp & 0x20) && dcompen);
5744 bool di4t4 = di4t0_1
5745 || (!(srcd & 0x10) && bcompen)
5746 || (!(pixsize & 0x04) && (dcomp & 0x10) && dcompen);
5747 dbinh |= (!(di4t4 && phrase_mode) ? 0x10 : 0x00);
5748 #ifdef LOG_COMP_CTRL
5751 printf("[di4t0_1=%s di2t4=%s]", (di4t0_1 ? "T" : "F"), (di4t4 ? "T" : "F"));
5755 //////////////////////////////////////////////////////////////////////////////////////
5757 /*Di5t0 := NAN3 (di5t[0], pixsize\[2], dcomp[5], dcompen);
5758 Di5t1 := NAN2 (di5t[1], srcd\[5], bcompen);
5759 Di5t2 := NAN4 (di5t[2], di4t[0..1], di5t[0..1]);
5760 Dbinh[5] := NAN2 (dbinh\[5], di5t[2], phrase_mode);*/
5761 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5762 bool di5t2 = di4t0_1
5763 || (!(srcd & 0x20) && bcompen)
5764 || (!(pixsize & 0x04) && (dcomp & 0x20) && dcompen);
5765 dbinh |= (!(di5t2 && phrase_mode) ? 0x20 : 0x00);
5766 #ifdef LOG_COMP_CTRL
5769 printf("[di5t2=%s]", (di5t2 ? "T" : "F"));
5773 //////////////////////////////////////////////////////////////////////////////////////
5775 /*Di6t0 := NAN2H (di6t[0], pixsize[2], zcomp[3]);
5776 Di6t1 := NAN4H (di6t[1], pixsize[2], dcomp[6..7], dcompen);
5777 Di6t2 := NAN2 (di6t[2], srcd\[6], bcompen);
5778 Di6t3 := NAN3 (di6t[3], pixsize\[2], dcomp[6], dcompen);
5779 Di6t4 := NAN4 (di6t[4], di6t[0..3]);
5780 Dbinh[6] := NAN2 (dbinh\[6], di6t[4], phrase_mode);*/
5781 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5782 bool di6t0_1 = ((pixsize & 0x04) && (zcomp & 0x08))
5783 || ((pixsize & 0x04) && (dcomp & 0x40) && (dcomp & 0x80) && dcompen);
5784 bool di6t4 = di6t0_1
5785 || (!(srcd & 0x40) && bcompen)
5786 || (!(pixsize & 0x04) && (dcomp & 0x40) && dcompen);
5787 dbinh |= (!(di6t4 && phrase_mode) ? 0x40 : 0x00);
5788 #ifdef LOG_COMP_CTRL
5791 printf("[di6t0_1=%s di6t4=%s]", (di6t0_1 ? "T" : "F"), (di6t4 ? "T" : "F"));
5795 //////////////////////////////////////////////////////////////////////////////////////
5797 /*Di7t0 := NAN3 (di7t[0], pixsize\[2], dcomp[7], dcompen);
5798 Di7t1 := NAN2 (di7t[1], srcd\[7], bcompen);
5799 Di7t2 := NAN4 (di7t[2], di6t[0..1], di7t[0..1]);
5800 Dbinh[7] := NAN2 (dbinh\[7], di7t[2], phrase_mode);*/
5801 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5802 bool di7t2 = di6t0_1
5803 || (!(srcd & 0x80) && bcompen)
5804 || (!(pixsize & 0x04) && (dcomp & 0x80) && dcompen);
5805 dbinh |= (!(di7t2 && phrase_mode) ? 0x80 : 0x00);
5806 #ifdef LOG_COMP_CTRL
5809 printf("[di7t2=%s]", (di7t2 ? "T" : "F"));
5813 //////////////////////////////////////////////////////////////////////////////////////
5818 #ifdef LOG_COMP_CTRL
5821 printf("[dcomp=$%02X dbinh=$%02X]\n ", dcomp, dbinh);
5828 ////////////////////////////////////// C++ CODE //////////////////////////////////////
5829 //////////////////////////////////////////////////////////////////////////////////////