2 // RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
18 #define DEF_MR // Declare keyword values
19 #include "risckw.h" // Incl. generated risc keywords
21 #define DEF_KW // Declare keyword values
22 #include "kwtab.h" // Incl. generated keyword tables & defs
25 unsigned altbankok = 0; // Ok to use alternate register bank
26 unsigned orgactive = 0; // RISC org directive active
27 unsigned orgaddr = 0; // Org'd address
28 unsigned orgwarning = 0; // Has an ORG warning been issued
29 int lastOpcode = -1; // Last RISC opcode assembled
30 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
32 const char reg_err[] = "missing register R0...R31";
34 // Jaguar jump condition names
35 const char condname[MAXINTERNCC][5] = {
36 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
37 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
41 // Jaguar jump condition numbers
42 const char condnumber[] = {
43 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
44 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
47 const struct opcoderecord roptbl[] = {
48 { MR_ADD, RI_TWO, 0 },
49 { MR_ADDC, RI_TWO, 1 },
50 { MR_ADDQ, RI_NUM_32, 2 },
51 { MR_ADDQT, RI_NUM_32, 3 },
52 { MR_SUB, RI_TWO, 4 },
53 { MR_SUBC, RI_TWO, 5 },
54 { MR_SUBQ, RI_NUM_32, 6 },
55 { MR_SUBQT, RI_NUM_32, 7 },
56 { MR_NEG, RI_ONE, 8 },
57 { MR_AND, RI_TWO, 9 },
58 { MR_OR, RI_TWO, 10 },
59 { MR_XOR, RI_TWO, 11 },
60 { MR_NOT, RI_ONE, 12 },
61 { MR_BTST, RI_NUM_31, 13 },
62 { MR_BSET, RI_NUM_31, 14 },
63 { MR_BCLR, RI_NUM_31, 15 },
64 { MR_MULT, RI_TWO, 16 },
65 { MR_IMULT, RI_TWO, 17 },
66 { MR_IMULTN, RI_TWO, 18 },
67 { MR_RESMAC, RI_ONE, 19 },
68 { MR_IMACN, RI_TWO, 20 },
69 { MR_DIV, RI_TWO, 21 },
70 { MR_ABS, RI_ONE, 22 },
71 { MR_SH, RI_TWO, 23 },
72 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
73 { MR_SHRQ, RI_NUM_32, 25 },
74 { MR_SHA, RI_TWO, 26 },
75 { MR_SHARQ, RI_NUM_32, 27 },
76 { MR_ROR, RI_TWO, 28 },
77 { MR_RORQ, RI_NUM_32, 29 },
78 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
79 { MR_CMP, RI_TWO, 30 },
80 { MR_CMPQ, RI_NUM_15, 31 },
81 { MR_SAT8, RI_ONE, 32 + GPUONLY },
82 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
83 { MR_SAT16, RI_ONE, 33 + GPUONLY },
84 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
85 { MR_MOVEQ, RI_NUM_31, 35 },
86 { MR_MOVETA, RI_TWO, 36 },
87 { MR_MOVEFA, RI_TWO, 37 },
88 { MR_MOVEI, RI_MOVEI, 38 },
89 { MR_LOADB, RI_LOADN, 39 },
90 { MR_LOADW, RI_LOADN, 40 },
91 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
92 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
93 { MR_STOREB, RI_STOREN, 45 },
94 { MR_STOREW, RI_STOREN, 46 },
95 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
96 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
97 { MR_JUMP, RI_JUMP, 52 },
99 { MR_MMULT, RI_TWO, 54 },
100 { MR_MTOI, RI_TWO, 55 },
101 { MR_NORMI, RI_TWO, 56 },
102 { MR_NOP, RI_NONE, 57 },
103 { MR_SAT24, RI_ONE, 62 },
104 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
105 { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
106 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
107 { MR_MOVE, RI_MOVE, 0 },
108 { MR_LOAD, RI_LOAD, 0 },
109 { MR_STORE, RI_STORE, 0 }
114 // Convert a string to uppercase
116 void strtoupper(char * s)
124 // Function to return "malformed expression" error
125 // This is done mainly to remove a bunch of GOTO statements in the parser
127 static inline int MalformedOpcode(int signal)
130 sprintf(buf, "%02X", signal);
131 return errors("Malformed opcode [internal $%s]", buf);
136 // Build RISC instruction word
138 void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
140 // Check for absolute address setting
141 if (!orgwarning && !orgactive)
143 warn("RISC code generated with no origin defined");
147 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
149 //printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
154 // Get a RISC register
156 int GetRegister(WORD rattr)
158 VALUE eval; // Expression value
159 WORD eattr; // Expression attributes
160 SYM * esym; // External symbol involved in expr.
161 TOKEN r_expr[EXPRSIZE]; // Expression token list
163 // Evaluate what's in the global "tok" buffer
164 if (expr(r_expr, &eval, &eattr, &esym) != OK)
167 if ((challoc - ch_size) < 4)
170 if (!(eattr & DEFINED))
172 AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr);
176 // If we got a register in range (0-31), return it
177 if ((eval >= 0) && (eval <= 31))
180 // Otherwise, it's out of range & we flag an error
181 return error(reg_err);
186 // Do RISC code generation
188 int GenerateRISCCode(int state)
190 int reg1; // Register 1
191 int reg2; // Register 2
192 int val = 0; // Constructed value
199 int indexed; // Indexed register flag
201 VALUE eval; // Expression value
202 WORD eattr; // Expression attributes
203 SYM * esym; // External symbol involved in expr.
204 TOKEN r_expr[EXPRSIZE]; // Expression token list
206 // Get opcode parameter and type
207 unsigned short parm = (WORD)(roptbl[state - 3000].parm);
208 unsigned type = roptbl[state - 3000].typ;
209 riscImmTokenSeen = 0; // Set to "token not seen yet"
211 // Detect whether the opcode parmeter passed determines that the opcode is
212 // specific to only one of the RISC processors and ensure it is legal in
213 // the current code section. If not then show error and return.
214 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
215 return error("Opcode is not valid in this code section");
217 // Process RISC opcode
220 // No operand instructions
223 BuildRISCIntructionWord(parm, 0, 0);
226 // Single operand instructions (Rd)
227 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
230 reg2 = GetRegister(FU_REGTWO);
232 BuildRISCIntructionWord(parm, parm >> 6, reg2);
235 // Two operand instructions (Rs,Rd)
236 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
237 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
240 altbankok = 1; // MOVEFA
242 reg1 = GetRegister(FU_REGONE);
246 altbankok = 1; // MOVETA
248 reg2 = GetRegister(FU_REGTWO);
250 BuildRISCIntructionWord(parm, reg1, reg2);
253 // Numeric operand (n,Rd) where n = -16..+15
257 // Numeric operand (n,Rd) where n = 0..31
258 // BCLR, BSET, BTST, MOVEQ
261 // Numeric operand (n,Rd) where n = 1..32
262 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
268 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
272 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
275 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
283 return MalformedOpcode(0x01);
286 riscImmTokenSeen = 1;
288 if (expr(r_expr, &eval, &eattr, &esym) != OK)
289 return MalformedOpcode(0x02);
291 if ((challoc - ch_size) < 4)
294 if (!(eattr & DEFINED))
296 AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
301 if ((int)eval < reg1 || (int)eval > reg2)
302 return error("constant out of range");
306 else if (type == RI_NUM_32)
307 reg1 = (reg1 == 32 ? 0 : eval);
313 reg2 = GetRegister(FU_REGTWO);
315 BuildRISCIntructionWord(parm, reg1, reg2);
318 // Move Immediate--n,Rn--n in Second Word
321 return MalformedOpcode(0x03);
324 riscImmTokenSeen = 1;
326 // Check for equated register after # and return error if so
329 sy = lookup(string[tok[1]], LABEL, 0);
331 if (sy && (sy->sattre & EQUATEDREG))
332 return error("equated register in 1st operand of MOVEI instruction");
335 if (expr(r_expr, &eval, &eattr, &esym) != OK)
336 return MalformedOpcode(0x04);
338 if (lastOpcode == RI_JUMP || lastOpcode == RI_JR)
342 // User doesn't care, emit a NOP to fix
343 BuildRISCIntructionWord(57, 0, 0);
344 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
347 warn("MOVEI immediately follows JUMP");
350 if ((challoc - ch_size) < 4)
353 if (!(eattr & DEFINED))
355 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
362 //printf("RISCASM: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
363 rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
367 val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000);
369 reg2 = GetRegister(FU_REGTWO);
371 D_word((((parm & 0x3F) << 10) + reg2));
386 reg1 = GetRegister(FU_REGONE);
390 reg2 = GetRegister(FU_REGTWO);
392 BuildRISCIntructionWord(parm, reg1, reg2);
395 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
401 return MalformedOpcode(0x05);
405 if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')'))
406 indexed = (*tok - KW_R0);
410 // sy = lookup((char *)tok[1], LABEL, 0);
411 sy = lookup(string[tok[1]], LABEL, 0);
419 if (sy->sattre & EQUATEDREG)
421 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
422 && (*(tok + 2) != ')'))
424 indexed = (sy->svalue & 0x1F);
432 reg1 = GetRegister(FU_REGONE);
442 parm = (WORD)(reg1 - 14 + 58);
445 if (*tok >= KW_R0 && *tok <= KW_R31)
450 // sy = lookup((char *)tok[1], LABEL, 0);
451 sy = lookup(string[tok[1]], LABEL, 0);
459 if (sy->sattre & EQUATEDREG)
465 reg1 = GetRegister(FU_REGONE);
469 if (expr(r_expr, &eval, &eattr, &esym) != OK)
470 return MalformedOpcode(0x06);
472 if ((challoc - ch_size) < 4)
475 if (!(eattr & DEFINED))
476 return error("constant expected after '+'");
482 reg1 = 14 + (parm - 58);
484 warn("NULL offset in LOAD ignored");
488 if (reg1 < 1 || reg1 > 32)
489 return error("constant in LOAD out of range");
494 parm = (WORD)(parm - 58 + 43);
500 reg1 = GetRegister(FU_REGONE);
505 return MalformedOpcode(0x07);
509 reg2 = GetRegister(FU_REGTWO);
511 BuildRISCIntructionWord(parm, reg1, reg2);
514 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
517 reg1 = GetRegister(FU_REGONE);
521 return MalformedOpcode(0x08);
526 if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')'))
527 indexed = (*tok - KW_R0);
531 sy = lookup(string[tok[1]], LABEL, 0);
539 if (sy->sattre & EQUATEDREG)
541 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
542 && (*(tok + 2) != ')'))
544 indexed = (sy->svalue & 0x1F);
552 reg2 = GetRegister(FU_REGTWO);
562 parm = (WORD)(reg2 - 14 + 60);
565 if (*tok >= KW_R0 && *tok <= KW_R31)
570 sy = lookup(string[tok[1]], LABEL, 0);
578 if (sy->sattre & EQUATEDREG)
584 reg2 = GetRegister(FU_REGTWO);
588 if (expr(r_expr, &eval, &eattr, &esym) != OK)
589 return MalformedOpcode(0x09);
591 if ((challoc - ch_size) < 4)
594 if (!(eattr & DEFINED))
596 AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
605 reg2 = 14 + (parm - 60);
607 warn("NULL offset in STORE ignored");
611 if (reg2 < 1 || reg2 > 32)
612 return error("constant in STORE out of range");
617 parm = (WORD)(parm - 60 + 49);
624 reg2 = GetRegister(FU_REGTWO);
629 return MalformedOpcode(0x0A);
633 BuildRISCIntructionWord(parm, reg2, reg1);
636 // LOADB/LOADP/LOADW (Rn),Rn
639 return MalformedOpcode(0x0B);
642 reg1 = GetRegister(FU_REGONE);
645 return MalformedOpcode(0x0C);
649 reg2 = GetRegister(FU_REGTWO);
651 BuildRISCIntructionWord(parm, reg1, reg2);
654 // STOREB/STOREP/STOREW Rn,(Rn)
656 reg1 = GetRegister(FU_REGONE);
660 return MalformedOpcode(0x0D);
663 reg2 = GetRegister(FU_REGTWO);
666 return MalformedOpcode(0x0E);
670 BuildRISCIntructionWord(parm, reg2, reg1);
673 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
676 // Jump Absolute - cc,(Rs) - reg2=cc
678 // Check to see if there is a comma in the token string. If not then
679 // the JR or JUMP should default to 0, Jump Always
682 for(t=tok; *t!=EOL; t++)
695 // CC using a constant number
701 else if (*tok == SYMBOL)
704 // strcpy(scratch, (char *)tok[1]);
705 strcpy(scratch, string[tok[1]]);
708 for(i=0; i<MAXINTERNCC; i++)
710 // Look for the condition code & break if found
711 if (strcmp(condname[i], scratch) == 0)
718 // Standard CC was not found, look for an equated one
721 // ccsym = lookup((char *)tok[1], LABEL, 0);
722 ccsym = lookup(string[tok[1]], LABEL, 0);
724 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
729 return error("unknown condition code");
735 else if (*tok == '(')
737 // Set CC to "Jump Always"
743 // Set CC to "Jump Always"
747 if (val < 0 || val > 31)
748 return error("condition constant out of range");
750 // Store condition code
756 if (expr(r_expr, &eval, &eattr, &esym) != OK)
757 return MalformedOpcode(0x0F);
759 if ((challoc - ch_size) < 4)
762 if (!(eattr & DEFINED))
764 AddFixup(FU_WORD | FU_JR, sloc, r_expr);
769 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
771 if ((reg2 < -16) || (reg2 > 15))
772 error("PC relative overflow");
775 BuildRISCIntructionWord(parm, reg2, reg1);
781 return MalformedOpcode(0x10);
784 reg2 = GetRegister(FU_REGTWO);
787 return MalformedOpcode(0x11);
791 BuildRISCIntructionWord(parm, reg2, reg1);
796 // Should never get here :-D
798 return error("Unknown RISC opcode type");