2 // RMAC - Reboot's Macro Assembler for all Atari computers
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
19 #define DEF_MR // Declare keyword values
20 #include "risckw.h" // Incl. generated risc keywords
22 #define DEF_KW // Declare keyword values
23 #include "kwtab.h" // Incl. generated keyword tables & defs
26 unsigned altbankok = 0; // Ok to use alternate register bank
27 unsigned orgactive = 0; // RISC/6502 org directive active
28 unsigned orgaddr = 0; // Org'd address
29 unsigned orgwarning = 0; // Has an ORG warning been issued
30 int lastOpcode = -1; // Last RISC opcode assembled
31 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
33 const char reg_err[] = "missing register R0...R31";
35 // Jaguar jump condition names
36 const char condname[MAXINTERNCC][5] = {
37 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
38 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
42 // Jaguar jump condition numbers
43 const char condnumber[] = {
44 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
45 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
48 const struct opcoderecord roptbl[] = {
49 { MR_ADD, RI_TWO, 0 },
50 { MR_ADDC, RI_TWO, 1 },
51 { MR_ADDQ, RI_NUM_32, 2 },
52 { MR_ADDQT, RI_NUM_32, 3 },
53 { MR_SUB, RI_TWO, 4 },
54 { MR_SUBC, RI_TWO, 5 },
55 { MR_SUBQ, RI_NUM_32, 6 },
56 { MR_SUBQT, RI_NUM_32, 7 },
57 { MR_NEG, RI_ONE, 8 },
58 { MR_AND, RI_TWO, 9 },
59 { MR_OR, RI_TWO, 10 },
60 { MR_XOR, RI_TWO, 11 },
61 { MR_NOT, RI_ONE, 12 },
62 { MR_BTST, RI_NUM_31, 13 },
63 { MR_BSET, RI_NUM_31, 14 },
64 { MR_BCLR, RI_NUM_31, 15 },
65 { MR_MULT, RI_TWO, 16 },
66 { MR_IMULT, RI_TWO, 17 },
67 { MR_IMULTN, RI_TWO, 18 },
68 { MR_RESMAC, RI_ONE, 19 },
69 { MR_IMACN, RI_TWO, 20 },
70 { MR_DIV, RI_TWO, 21 },
71 { MR_ABS, RI_ONE, 22 },
72 { MR_SH, RI_TWO, 23 },
73 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
74 { MR_SHRQ, RI_NUM_32, 25 },
75 { MR_SHA, RI_TWO, 26 },
76 { MR_SHARQ, RI_NUM_32, 27 },
77 { MR_ROR, RI_TWO, 28 },
78 { MR_RORQ, RI_NUM_32, 29 },
79 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
80 { MR_CMP, RI_TWO, 30 },
81 { MR_CMPQ, RI_NUM_15, 31 },
82 { MR_SAT8, RI_ONE, 32 + GPUONLY },
83 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
84 { MR_SAT16, RI_ONE, 33 + GPUONLY },
85 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
86 { MR_MOVEQ, RI_NUM_31, 35 },
87 { MR_MOVETA, RI_TWO, 36 },
88 { MR_MOVEFA, RI_TWO, 37 },
89 { MR_MOVEI, RI_MOVEI, 38 },
90 { MR_LOADB, RI_LOADN, 39 },
91 { MR_LOADW, RI_LOADN, 40 },
92 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
93 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
94 { MR_STOREB, RI_STOREN, 45 },
95 { MR_STOREW, RI_STOREN, 46 },
96 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
97 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
98 { MR_JUMP, RI_JUMP, 52 },
100 { MR_MMULT, RI_TWO, 54 },
101 { MR_MTOI, RI_TWO, 55 },
102 { MR_NORMI, RI_TWO, 56 },
103 { MR_NOP, RI_NONE, 57 },
104 { MR_SAT24, RI_ONE, 62 },
105 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
106 { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
107 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
108 { MR_MOVE, RI_MOVE, 0 },
109 { MR_LOAD, RI_LOAD, 0 },
110 { MR_STORE, RI_STORE, 0 }
115 // Convert a string to uppercase
117 void strtoupper(char * s)
125 // Function to return "malformed expression" error
126 // This is done mainly to remove a bunch of GOTO statements in the parser
128 static inline int MalformedOpcode(int signal)
131 sprintf(buf, "%02X", signal);
132 return errors("Malformed opcode [internal $%s]", buf);
136 // Function to return "Illegal Indexed Register" error
137 // Anyone trying to index something other than R14 or R15
139 static inline int IllegalIndexedRegister(int reg)
142 sprintf(buf, "%d", reg - KW_R0);
143 return errors("Attempted index reference with non-indexable register (r%s)", buf);
147 // Function to return "Illegal Indexed Register" error for EQUR scenarios
148 // Trying to use register value within EQUR that isn't 14 or 15
150 static inline int IllegalIndexedRegisterEqur(SYM *sy)
154 buf = (char *)malloc((strlen(sy->sname) + 7) * sizeof(char));
156 sprintf(buf, "%s = r%d",sy->sname, sy->svalue);
157 return errors("Attempted index reference with non-indexable register within EQUR (%s)", buf);
159 return errors("Unable to allocate memory! (IllegalIndexRegisterEqur)", "OOPS");
163 // Build RISC instruction word
165 void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
167 // Check for absolute address setting
168 if (!orgwarning && !orgactive)
170 warn("RISC code generated with no origin defined");
174 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
176 //printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
181 // Get a RISC register
183 int GetRegister(WORD rattr)
185 VALUE eval; // Expression value
186 WORD eattr; // Expression attributes
187 SYM * esym; // External symbol involved in expr.
188 TOKEN r_expr[EXPRSIZE]; // Expression token list
190 // Evaluate what's in the global "tok" buffer
191 if (expr(r_expr, &eval, &eattr, &esym) != OK)
194 if ((challoc - ch_size) < 4)
197 if (!(eattr & DEFINED))
199 AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr);
203 // If we got a register in range (0-31), return it
204 if ((eval >= 0) && (eval <= 31))
207 // Otherwise, it's out of range & we flag an error
208 return error(reg_err);
213 // Do RISC code generation
215 int GenerateRISCCode(int state)
217 int reg1; // Register 1
218 int reg2; // Register 2
219 int val = 0; // Constructed value
226 int indexed; // Indexed register flag
228 VALUE eval; // Expression value
229 WORD eattr; // Expression attributes
230 SYM * esym; // External symbol involved in expr.
231 TOKEN r_expr[EXPRSIZE]; // Expression token list
233 // Get opcode parameter and type
234 unsigned short parm = (WORD)(roptbl[state - 3000].parm);
235 unsigned type = roptbl[state - 3000].typ;
236 riscImmTokenSeen = 0; // Set to "token not seen yet"
238 // Detect whether the opcode parmeter passed determines that the opcode is
239 // specific to only one of the RISC processors and ensure it is legal in
240 // the current code section. If not then show error and return.
241 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
242 return error("Opcode is not valid in this code section");
244 // Process RISC opcode
247 // No operand instructions
250 BuildRISCIntructionWord(parm, 0, 0);
253 // Single operand instructions (Rd)
254 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
257 reg2 = GetRegister(FU_REGTWO);
259 BuildRISCIntructionWord(parm, parm >> 6, reg2);
262 // Two operand instructions (Rs,Rd)
263 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
264 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
267 altbankok = 1; // MOVEFA
269 reg1 = GetRegister(FU_REGONE);
273 altbankok = 1; // MOVETA
275 reg2 = GetRegister(FU_REGTWO);
277 BuildRISCIntructionWord(parm, reg1, reg2);
280 // Numeric operand (n,Rd) where n = -16..+15
284 // Numeric operand (n,Rd) where n = 0..31
285 // BCLR, BSET, BTST, MOVEQ
288 // Numeric operand (n,Rd) where n = 1..32
289 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
295 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
299 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
302 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
310 return MalformedOpcode(0x01);
313 riscImmTokenSeen = 1;
315 if (expr(r_expr, &eval, &eattr, &esym) != OK)
316 return MalformedOpcode(0x02);
318 if ((challoc - ch_size) < 4)
321 if (!(eattr & DEFINED))
323 AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
328 if ((int)eval < reg1 || (int)eval > reg2)
329 return error("constant out of range");
333 else if (type == RI_NUM_32)
334 reg1 = (reg1 == 32 ? 0 : eval);
340 reg2 = GetRegister(FU_REGTWO);
342 BuildRISCIntructionWord(parm, reg1, reg2);
345 // Move Immediate--n,Rn--n in Second Word
348 return MalformedOpcode(0x03);
351 riscImmTokenSeen = 1;
353 // Check for equated register after # and return error if so
356 sy = lookup(string[tok[1]], LABEL, 0);
358 if (sy && (sy->sattre & EQUATEDREG))
359 return error("equated register in 1st operand of MOVEI instruction");
362 if (expr(r_expr, &eval, &eattr, &esym) != OK)
363 return MalformedOpcode(0x04);
365 if (lastOpcode == RI_JUMP || lastOpcode == RI_JR)
369 // User doesn't care, emit a NOP to fix
370 BuildRISCIntructionWord(57, 0, 0);
371 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
374 warn("MOVEI immediately follows JUMP");
377 if ((challoc - ch_size) < 4)
380 if (!(eattr & DEFINED))
382 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
389 //printf("RISCASM: Doing MarkRelocatable for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
390 MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
394 // val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000);
395 val = WORDSWAP32(eval);
397 reg2 = GetRegister(FU_REGTWO);
399 D_word((((parm & 0x3F) << 10) + reg2));
414 reg1 = GetRegister(FU_REGONE);
418 reg2 = GetRegister(FU_REGTWO);
420 BuildRISCIntructionWord(parm, reg1, reg2);
423 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
429 return MalformedOpcode(0x05);
433 if ((*(tok + 1) == '+') || (*(tok + 1) == '-')) {
434 // Trying to make indexed call
435 if ((*tok == KW_R14 || *tok == KW_R15)) {
436 indexed = (*tok - KW_R0);
438 return IllegalIndexedRegister(*tok);
444 // sy = lookup((char *)tok[1], LABEL, 0);
445 sy = lookup(string[tok[1]], LABEL, 0);
453 if (sy->sattre & EQUATEDREG)
455 if ((*(tok + 2) == '+') || (*(tok + 2) == '-')) {
456 if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) {
457 indexed = (sy->svalue & 0x1F);
460 return IllegalIndexedRegisterEqur(sy);
468 reg1 = GetRegister(FU_REGONE);
478 parm = (WORD)(reg1 - 14 + 58);
481 if (*tok >= KW_R0 && *tok <= KW_R31)
486 // sy = lookup((char *)tok[1], LABEL, 0);
487 sy = lookup(string[tok[1]], LABEL, 0);
495 if (sy->sattre & EQUATEDREG)
501 reg1 = GetRegister(FU_REGONE);
505 if (expr(r_expr, &eval, &eattr, &esym) != OK)
506 return MalformedOpcode(0x06);
508 if ((challoc - ch_size) < 4)
511 if (!(eattr & DEFINED))
512 return error("constant expected after '+'");
518 reg1 = 14 + (parm - 58);
520 warn("NULL offset in LOAD ignored");
524 if (reg1 < 1 || reg1 > 32)
525 return error("constant in LOAD out of range");
530 parm = (WORD)(parm - 58 + 43);
536 reg1 = GetRegister(FU_REGONE);
541 return MalformedOpcode(0x07);
545 reg2 = GetRegister(FU_REGTWO);
547 BuildRISCIntructionWord(parm, reg1, reg2);
550 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
553 reg1 = GetRegister(FU_REGONE);
557 return MalformedOpcode(0x08);
562 if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')'))
563 indexed = (*tok - KW_R0);
567 sy = lookup(string[tok[1]], LABEL, 0);
575 if (sy->sattre & EQUATEDREG)
577 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
578 && (*(tok + 2) != ')'))
580 indexed = (sy->svalue & 0x1F);
588 reg2 = GetRegister(FU_REGTWO);
598 parm = (WORD)(reg2 - 14 + 60);
601 if (*tok >= KW_R0 && *tok <= KW_R31)
606 sy = lookup(string[tok[1]], LABEL, 0);
614 if (sy->sattre & EQUATEDREG)
620 reg2 = GetRegister(FU_REGTWO);
624 if (expr(r_expr, &eval, &eattr, &esym) != OK)
625 return MalformedOpcode(0x09);
627 if ((challoc - ch_size) < 4)
630 if (!(eattr & DEFINED))
632 AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
641 reg2 = 14 + (parm - 60);
643 warn("NULL offset in STORE ignored");
647 if (reg2 < 1 || reg2 > 32)
648 return error("constant in STORE out of range");
653 parm = (WORD)(parm - 60 + 49);
660 reg2 = GetRegister(FU_REGTWO);
665 return MalformedOpcode(0x0A);
669 BuildRISCIntructionWord(parm, reg2, reg1);
672 // LOADB/LOADP/LOADW (Rn),Rn
675 return MalformedOpcode(0x0B);
678 reg1 = GetRegister(FU_REGONE);
681 return MalformedOpcode(0x0C);
685 reg2 = GetRegister(FU_REGTWO);
687 BuildRISCIntructionWord(parm, reg1, reg2);
690 // STOREB/STOREP/STOREW Rn,(Rn)
692 reg1 = GetRegister(FU_REGONE);
696 return MalformedOpcode(0x0D);
699 reg2 = GetRegister(FU_REGTWO);
702 return MalformedOpcode(0x0E);
706 BuildRISCIntructionWord(parm, reg2, reg1);
709 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
712 // Jump Absolute - cc,(Rs) - reg2=cc
714 // Check to see if there is a comma in the token string. If not then
715 // the JR or JUMP should default to 0, Jump Always
718 for(t=tok; *t!=EOL; t++)
731 // CC using a constant number
737 else if (*tok == SYMBOL)
740 // strcpy(scratch, (char *)tok[1]);
741 strcpy(scratch, string[tok[1]]);
744 for(i=0; i<MAXINTERNCC; i++)
746 // Look for the condition code & break if found
747 if (strcmp(condname[i], scratch) == 0)
754 // Standard CC was not found, look for an equated one
757 // ccsym = lookup((char *)tok[1], LABEL, 0);
758 ccsym = lookup(string[tok[1]], LABEL, 0);
760 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
765 return error("unknown condition code");
771 else if (*tok == '(')
773 // Set CC to "Jump Always"
779 // Set CC to "Jump Always"
783 if (val < 0 || val > 31)
784 return error("condition constant out of range");
786 // Store condition code
792 if (expr(r_expr, &eval, &eattr, &esym) != OK)
793 return MalformedOpcode(0x0F);
795 if ((challoc - ch_size) < 4)
798 if (!(eattr & DEFINED))
800 AddFixup(FU_WORD | FU_JR, sloc, r_expr);
805 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
807 if ((reg2 < -16) || (reg2 > 15))
808 error("PC relative overflow");
811 BuildRISCIntructionWord(parm, reg2, reg1);
817 return MalformedOpcode(0x10);
820 reg2 = GetRegister(FU_REGTWO);
823 return MalformedOpcode(0x11);
827 BuildRISCIntructionWord(parm, reg2, reg1);
832 // Should never get here :-D
834 return error("Unknown RISC opcode type");