2 // RMAC - Renamed Macro Assembler for all Atari computers
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011-2021 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
20 #define DEF_MR // Declare keyword values
21 #include "risckw.h" // Incl. generated risc keywords
23 #define DEF_KW // Declare keyword values
24 #include "kwtab.h" // Incl. generated keyword tables & defs
26 #define MAXINTERNCC 26 // Maximum internal condition codes
29 #define EVAL_REG_RETURN_IF_ERROR(x, y) \
30 x = EvaluateRegisterFromTokenStream(y); \
35 #define EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(x, y) \
36 x = EvaluateRegisterFromTokenStream(y); \
38 if ((x == ERROR) || (ErrorIfNotAtEOL() == ERROR)) \
42 if (ErrorIfNotAtEOL() == ERROR) \
45 unsigned altbankok = 0; // Ok to use alternate register bank
46 unsigned orgactive = 0; // RISC/6502 org directive active
47 unsigned orgaddr = 0; // Org'd address
48 unsigned orgwarning = 0; // Has an ORG warning been issued
49 int lastOpcode = -1; // Last RISC opcode assembled
50 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
52 static const char reg_err[] = "missing register R0...R31";
54 // Jaguar jump condition names
55 static const char condname[MAXINTERNCC][5] = {
56 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
57 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
61 // Jaguar jump condition numbers
62 static const char condnumber[] = {
63 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
64 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
67 // Opcode Specific Data
69 uint16_t state; // Opcode Name (unused)
70 uint16_t type; // Opcode Type
71 uint16_t param; // Opcode Parameter
74 static const struct opcoderecord roptbl[] = {
75 { MR_ADD, RI_TWO, 0 },
76 { MR_ADDC, RI_TWO, 1 },
77 { MR_ADDQ, RI_NUM_32, 2 },
78 { MR_ADDQT, RI_NUM_32, 3 },
79 { MR_SUB, RI_TWO, 4 },
80 { MR_SUBC, RI_TWO, 5 },
81 { MR_SUBQ, RI_NUM_32, 6 },
82 { MR_SUBQT, RI_NUM_32, 7 },
83 { MR_NEG, RI_ONE, 8 },
84 { MR_AND, RI_TWO, 9 },
85 { MR_OR, RI_TWO, 10 },
86 { MR_XOR, RI_TWO, 11 },
87 { MR_NOT, RI_ONE, 12 },
88 { MR_BTST, RI_NUM_31, 13 },
89 { MR_BSET, RI_NUM_31, 14 },
90 { MR_BCLR, RI_NUM_31, 15 },
91 { MR_MULT, RI_TWO, 16 },
92 { MR_IMULT, RI_TWO, 17 },
93 { MR_IMULTN, RI_TWO, 18 },
94 { MR_RESMAC, RI_ONE, 19 },
95 { MR_IMACN, RI_TWO, 20 },
96 { MR_DIV, RI_TWO, 21 },
97 { MR_ABS, RI_ONE, 22 },
98 { MR_SH, RI_TWO, 23 },
99 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
100 { MR_SHRQ, RI_NUM_32, 25 },
101 { MR_SHA, RI_TWO, 26 },
102 { MR_SHARQ, RI_NUM_32, 27 },
103 { MR_ROR, RI_TWO, 28 },
104 { MR_RORQ, RI_NUM_32, 29 },
105 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
106 { MR_CMP, RI_TWO, 30 },
107 { MR_CMPQ, RI_NUM_15, 31 },
108 { MR_SAT8, RI_ONE, 32 + GPUONLY },
109 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
110 { MR_SAT16, RI_ONE, 33 + GPUONLY },
111 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
112 { MR_MOVEQ, RI_NUM_31, 35 },
113 { MR_MOVETA, RI_TWO, 36 },
114 { MR_MOVEFA, RI_TWO, 37 },
115 { MR_MOVEI, RI_MOVEI, 38 },
116 { MR_LOADB, RI_LOADN, 39 },
117 { MR_LOADW, RI_LOADN, 40 },
118 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
119 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
120 { MR_STOREB, RI_STOREN, 45 },
121 { MR_STOREW, RI_STOREN, 46 },
122 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
123 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
124 { MR_JUMP, RI_JUMP, 52 },
125 { MR_JR, RI_JR, 53 },
126 { MR_MMULT, RI_TWO, 54 },
127 { MR_MTOI, RI_TWO, 55 },
128 { MR_NORMI, RI_TWO, 56 },
129 { MR_NOP, RI_NONE, 57 },
130 { MR_SAT24, RI_ONE, 62 },
131 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
132 { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
133 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
134 { MR_MOVE, RI_MOVE, 0 },
135 { MR_LOAD, RI_LOAD, 0 },
136 { MR_STORE, RI_STORE, 0 }
141 #define MALF_LPAREN 2
142 #define MALF_RPAREN 3
144 static const char malform1[] = "missing '#'";
145 static const char malform2[] = "bad expression";
146 static const char malform3[] = "missing ')'";
147 static const char malform4[] = "missing '('";
149 static const char * malformErr[] = {
150 malform1, malform2, malform3, malform4
154 // Function to return "malformed expression" error
155 // This is done mainly to remove a bunch of GOTO statements in the parser
157 static inline int MalformedOpcode(int signal)
159 return error("Malformed opcode, %s", malformErr[signal]);
163 // Function to return "Illegal Indexed Register" error
164 // Anyone trying to index something other than R14 or R15
166 static inline int IllegalIndexedRegister(int reg)
168 return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0);
172 // Function to return "Illegal Indexed Register" error for EQUR scenarios
173 // Trying to use register value within EQUR that isn't 14 or 15
175 static inline int IllegalIndexedRegisterEqur(SYM * sy)
177 return error("Attempted index reference with non-indexable register within EQUR (%s = r%d)", sy->sname, sy->svalue);
181 // Build up & deposit RISC instruction word
183 static void DepositRISCInstructionWord(uint16_t opcode, int reg1, int reg2)
185 // Check for absolute address setting
186 if (!orgwarning && !orgactive)
188 warn("RISC code generated with no origin defined");
192 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
197 // Evaluate the RISC register from the token stream. Passed in value is the
198 // FIXUP attribute to use if the expression comes back as undefined.
200 static int EvaluateRegisterFromTokenStream(uint32_t fixup)
202 // Firstly, check to see if it's a register token and return that. No
203 // need to invoke expr() for easy cases like this.
204 if (*tok >= KW_R0 && *tok <= KW_R31)
206 int reg = *tok - KW_R0;
213 // If at this point we don't have a symbol then it's garbage. Punt.
214 return error("Expected register number or EQUREG");
217 uint64_t eval; // Expression value
218 WORD eattr; // Expression attributes
219 SYM * esym; // External symbol involved in expr.
220 TOKEN r_expr[EXPRSIZE]; // Expression token list
222 // Evaluate what's in the global "tok" buffer
223 // N.B.: We should either get a fixup or a register name from EQUR
224 if (expr(r_expr, &eval, &eattr, &esym) != OK)
227 if (!(eattr & DEFINED))
229 AddFixup(FU_WORD | fixup, sloc, r_expr);
233 // If we got a register in range (0-31), return it
237 // Otherwise, it's out of range & we flag an error
238 return error(reg_err);
242 // Do RISC code generation
244 int GenerateRISCCode(int state)
246 int reg1; // Register 1
247 int reg2; // Register 2
248 int val = 0; // Constructed value
255 int indexed; // Indexed register flag
257 uint64_t eval; // Expression value
258 uint16_t eattr; // Expression attributes
259 SYM * esym = NULL; // External symbol involved in expr.
260 TOKEN r_expr[EXPRSIZE]; // Expression token list
262 // Get opcode parameter and type
263 uint16_t parm = roptbl[state - 3000].param;
264 uint16_t type = roptbl[state - 3000].type;
265 riscImmTokenSeen = 0; // Set to "token not seen yet"
267 // Detect whether the opcode parmeter passed determines that the opcode is
268 // specific to only one of the RISC processors and ensure it is legal in
269 // the current code section. If not then show error and return.
270 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
271 return error("Opcode is not valid in this code section");
273 // Process RISC opcode
276 // No operand instructions
279 DepositRISCInstructionWord(parm, 0, 0);
282 // Single operand instructions (Rd)
283 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
286 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
287 DepositRISCInstructionWord(parm, parm >> 6, reg2);
290 // Two operand instructions (Rs,Rd)
291 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
292 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
295 altbankok = 1; // MOVEFA
297 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
301 altbankok = 1; // MOVETA
303 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
304 DepositRISCInstructionWord(parm, reg1, reg2);
307 // Numeric operand (n,Rd) where n = -16..+15
311 // Numeric operand (n,Rd) where n = 0..31
312 // BCLR, BSET, BTST, MOVEQ
315 // Numeric operand (n,Rd) where n = 1..32
316 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
322 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
326 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
329 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
337 return MalformedOpcode(MALF_NUM);
340 riscImmTokenSeen = 1;
342 if (expr(r_expr, &eval, &eattr, &esym) != OK)
343 return MalformedOpcode(MALF_EXPR);
345 if (!(eattr & DEFINED))
347 AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
352 if (esym && (esym->sattre & EQUATEDREG))
353 return error("equated register seen for immediate value");
356 return error("register seen for immediate value");
358 if (((int)eval < reg1) || ((int)eval > reg2))
359 return error("constant out of range (%d to %d)", reg1, reg2);
362 reg1 = 32 - (int)eval;
363 else if (type == RI_NUM_32)
364 reg1 = (reg1 == 32 ? 0 : (int)eval);
370 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
371 DepositRISCInstructionWord(parm, reg1, reg2);
374 // Move Immediate--n,Rn--n in Second Word
377 return MalformedOpcode(MALF_NUM);
380 riscImmTokenSeen = 1;
382 // Check for equated register after # and return error if so
385 sy = lookup(string[tok[1]], LABEL, 0);
387 if (sy && (sy->sattre & EQUATEDREG))
388 return error("equated register in 1st operand of MOVEI instruction");
391 if (expr(r_expr, &eval, &eattr, &esym) != OK)
392 return MalformedOpcode(MALF_EXPR);
394 if ((lastOpcode == RI_JUMP) || (lastOpcode == RI_JR))
398 // User doesn't care, emit a NOP to fix
399 DepositRISCInstructionWord(57, 0, 0);
400 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
403 warn("MOVEI immediately follows JUMP");
406 if (!(eattr & DEFINED))
408 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
414 MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
418 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
420 DepositRISCInstructionWord(parm, 0, reg2);
421 val = WORDSWAP32(eval);
436 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
440 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
441 DepositRISCInstructionWord(parm, reg1, reg2);
444 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
450 return MalformedOpcode(MALF_LPAREN);
454 if ((tok[1] == '+') || (tok[1] == '-'))
456 // Trying to make indexed call
457 if ((*tok == KW_R14) || (*tok == KW_R15))
458 indexed = (*tok - KW_R0);
460 return IllegalIndexedRegister(*tok);
465 sy = lookup(string[tok[1]], LABEL, 0);
473 if (sy->sattre & EQUATEDREG)
475 if ((tok[2] == '+') || (tok[2] == '-'))
477 if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) {
478 indexed = (sy->svalue & 0x1F);
482 return IllegalIndexedRegisterEqur(sy);
489 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
499 parm = (WORD)(reg1 - 14 + 58);
502 if ((*tok >= KW_R0) && (*tok <= KW_R31))
507 sy = lookup(string[tok[1]], LABEL, 0);
515 if (sy->sattre & EQUATEDREG)
521 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
525 if (expr(r_expr, &eval, &eattr, &esym) != OK)
526 return MalformedOpcode(MALF_EXPR);
528 if (!(eattr & DEFINED))
529 return error("constant expected after '+'");
535 reg1 = 14 + (parm - 58);
537 warn("NULL offset in LOAD ignored");
541 if ((reg1 < 1) || (reg1 > 32))
542 return error("constant in LOAD out of range (1-32)");
547 parm = (WORD)(parm - 58 + 43);
553 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
558 return MalformedOpcode(MALF_RPAREN);
562 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
563 DepositRISCInstructionWord(parm, reg1, reg2);
566 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
569 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
573 return MalformedOpcode(MALF_LPAREN);
578 if (((*tok == KW_R14) || (*tok == KW_R15)) && (tok[1] != ')'))
579 indexed = *tok - KW_R0;
583 sy = lookup(string[tok[1]], LABEL, 0);
591 if (sy->sattre & EQUATEDREG)
593 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
596 indexed = (sy->svalue & 0x1F);
604 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
614 parm = (WORD)(reg2 - 14 + 60);
617 if ((*tok >= KW_R0) && (*tok <= KW_R31))
622 sy = lookup(string[tok[1]], LABEL, 0);
630 if (sy->sattre & EQUATEDREG)
636 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
640 if (expr(r_expr, &eval, &eattr, &esym) != OK)
641 return MalformedOpcode(MALF_EXPR);
643 if (!(eattr & DEFINED))
645 AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
654 reg2 = 14 + (parm - 60);
656 warn("NULL offset in STORE ignored");
660 if ((reg2 < 1) || (reg2 > 32))
661 return error("constant in STORE out of range (1-32)");
666 parm = (WORD)(parm - 60 + 49);
673 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
678 return MalformedOpcode(MALF_RPAREN);
682 DepositRISCInstructionWord(parm, reg2, reg1);
685 // LOADB/LOADP/LOADW (Rn),Rn
688 return MalformedOpcode(MALF_LPAREN);
691 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
694 return MalformedOpcode(MALF_RPAREN);
698 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
699 DepositRISCInstructionWord(parm, reg1, reg2);
702 // STOREB/STOREP/STOREW Rn,(Rn)
704 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
708 return MalformedOpcode(MALF_LPAREN);
711 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
714 return MalformedOpcode(MALF_RPAREN);
718 DepositRISCInstructionWord(parm, reg2, reg1);
721 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
724 // Jump Absolute - cc,(Rs) - reg2=cc
726 // Check to see if there is a comma in the token string. If not then
727 // the JR or JUMP should default to 0, Jump Always
730 for(t=tok; *t!=EOL; t++)
743 // CC using a constant number (O_o)
750 else if (*tok == SYMBOL)
753 strcpy(scratch, string[tok[1]]);
756 for(i=0; i<MAXINTERNCC; i++)
758 // Look for the condition code & break if found
759 if (strcmp(condname[i], scratch) == 0)
766 // Standard CC was not found, look for an equated one
769 ccsym = lookup(string[tok[1]], LABEL, 0);
771 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
772 val = (int)ccsym->svalue;
774 return error("unknown condition code");
780 else if (*tok == '(')
782 // Set CC to "Jump Always"
788 // Set CC to "Jump Always"
792 if ((val < 0) || (val > 31))
793 return error("condition constant out of range");
795 // Store condition code
801 if (expr(r_expr, &eval, &eattr, &esym) != OK)
802 return MalformedOpcode(MALF_EXPR);
804 if (!(eattr & DEFINED))
806 AddFixup(FU_WORD | FU_JR, sloc, r_expr);
811 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
813 if ((reg2 < -16) || (reg2 > 15))
814 error("PC relative overflow in JR (outside of -16 to 15)");
821 return MalformedOpcode(MALF_LPAREN);
824 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
827 return MalformedOpcode(MALF_RPAREN);
833 DepositRISCInstructionWord(parm, reg2, reg1);
836 // We should never get here. If we do, somebody done fucked up. :-D
838 return error("Unknown RISC opcode type");