2 // RMAC - Renamed Macro Assembler for all Atari computers
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011-2021 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
20 #define DEF_MR // Declare keyword values
21 #include "risckw.h" // Incl. generated risc keywords
24 #include "riscregs.h" // Incl. generated keyword tables & defs
26 #define MAXINTERNCC 26 // Maximum internal condition codes
29 #define EVAL_REG_RETURN_IF_ERROR(x, y) \
30 x = EvaluateRegisterFromTokenStream(y); \
35 #define EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(x, y) \
36 x = EvaluateRegisterFromTokenStream(y); \
38 if ((x == ERROR) || (ErrorIfNotAtEOL() == ERROR)) \
42 if (ErrorIfNotAtEOL() == ERROR) \
45 unsigned altbankok = 0; // Ok to use alternate register bank
46 unsigned orgactive = 0; // RISC/6502 org directive active
47 unsigned orgaddr = 0; // Org'd address
48 unsigned orgwarning = 0; // Has an ORG warning been issued
49 int lastOpcode = -1; // Last RISC opcode assembled
50 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
52 static const char reg_err[] = "missing register R0...R31";
54 // Jaguar jump condition names
55 static const char condname[MAXINTERNCC][5] = {
56 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
57 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
61 // Jaguar jump condition numbers
62 static const char condnumber[] = {
63 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
64 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
67 // Opcode Specific Data
69 uint16_t state; // Opcode Name (unused)
70 uint16_t type; // Opcode Type
71 uint16_t param; // Opcode Parameter
74 static const struct opcoderecord roptbl[] = {
75 { MR_ADD, RI_TWO, 0 },
76 { MR_ADDC, RI_TWO, 1 },
77 { MR_ADDQ, RI_NUM_32, 2 },
78 { MR_ADDQT, RI_NUM_32, 3 },
79 { MR_SUB, RI_TWO, 4 },
80 { MR_SUBC, RI_TWO, 5 },
81 { MR_SUBQ, RI_NUM_32, 6 },
82 { MR_SUBQT, RI_NUM_32, 7 },
83 { MR_NEG, RI_ONE, 8 },
84 { MR_AND, RI_TWO, 9 },
85 { MR_OR, RI_TWO, 10 },
86 { MR_XOR, RI_TWO, 11 },
87 { MR_NOT, RI_ONE, 12 },
88 { MR_BTST, RI_NUM_31, 13 },
89 { MR_BSET, RI_NUM_31, 14 },
90 { MR_BCLR, RI_NUM_31, 15 },
91 { MR_MULT, RI_TWO, 16 },
92 { MR_IMULT, RI_TWO, 17 },
93 { MR_IMULTN, RI_TWO, 18 },
94 { MR_RESMAC, RI_ONE, 19 },
95 { MR_IMACN, RI_TWO, 20 },
96 { MR_DIV, RI_TWO, 21 },
97 { MR_ABS, RI_ONE, 22 },
98 { MR_SH, RI_TWO, 23 },
99 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
100 { MR_SHRQ, RI_NUM_32, 25 },
101 { MR_SHA, RI_TWO, 26 },
102 { MR_SHARQ, RI_NUM_32, 27 },
103 { MR_ROR, RI_TWO, 28 },
104 { MR_RORQ, RI_NUM_32, 29 },
105 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
106 { MR_CMP, RI_TWO, 30 },
107 { MR_CMPQ, RI_NUM_15, 31 },
108 { MR_SAT8, RI_ONE, 32 + GPUONLY },
109 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
110 { MR_SAT16, RI_ONE, 33 + GPUONLY },
111 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
112 { MR_MOVEQ, RI_NUM_31, 35 },
113 { MR_MOVETA, RI_TWO, 36 },
114 { MR_MOVEFA, RI_TWO, 37 },
115 { MR_MOVEI, RI_MOVEI, 38 },
116 { MR_LOADB, RI_LOADN, 39 },
117 { MR_LOADW, RI_LOADN, 40 },
118 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
119 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
120 { MR_STOREB, RI_STOREN, 45 },
121 { MR_STOREW, RI_STOREN, 46 },
122 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
123 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
124 { MR_JUMP, RI_JUMP, 52 },
125 { MR_JR, RI_JR, 53 },
126 { MR_MMULT, RI_TWO, 54 },
127 { MR_MTOI, RI_TWO, 55 },
128 { MR_NORMI, RI_TWO, 56 },
129 { MR_NOP, RI_NONE, 57 },
130 { MR_SAT24, RI_ONE, 62 },
131 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
132 { MR_PACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
133 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
134 { MR_MOVE, RI_MOVE, 0 },
135 { MR_LOAD, RI_LOAD, 0 },
136 { MR_STORE, RI_STORE, 0 }
141 #define MALF_LPAREN 2
142 #define MALF_RPAREN 3
144 static const char malform1[] = "missing '#'";
145 static const char malform2[] = "bad expression";
146 static const char malform3[] = "missing ')'";
147 static const char malform4[] = "missing '('";
149 static const char * malformErr[] = {
150 malform1, malform2, malform3, malform4
154 // Function to return "malformed expression" error
155 // This is done mainly to remove a bunch of GOTO statements in the parser
157 static inline int MalformedOpcode(int signal)
159 return error("Malformed opcode, %s", malformErr[signal]);
163 // Function to return "Illegal Indexed Register" error
164 // Anyone trying to index something other than R14 or R15
166 static inline int IllegalIndexedRegister(int reg)
168 return error("Attempted index reference with non-indexable register (r%d)", reg - REGRISC_R0);
172 // Function to return "Illegal Indexed Register" error for EQUR scenarios
173 // Trying to use register value within EQUR that isn't 14 or 15
175 static inline int IllegalIndexedRegisterEqur(SYM * sy)
177 return error("Attempted index reference with non-indexable register within EQUR (%s = r%d)", sy->sname, sy->svalue);
181 // Build up & deposit RISC instruction word
183 static void DepositRISCInstructionWord(uint16_t opcode, int reg1, int reg2)
185 // Check for absolute address setting
186 if (!orgwarning && !orgactive)
188 warn("RISC code generated with no origin defined");
192 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
198 // Evaluate the RISC register from the token stream. Passed in value is the
199 // FIXUP attribute to use if the expression comes back as undefined.
201 static int EvaluateRegisterFromTokenStream(uint32_t fixup)
203 // Firstly, check to see if it's a register token and return that. No
204 // need to invoke expr() for easy cases like this.
205 int reg = *tok & 255;
206 if (reg >= REGRISC_R0 && reg <= REGRISC_R31)
215 // If at this point we don't have a symbol then it's garbage. Punt.
216 return error("Expected register number or EQUREG");
219 uint64_t eval; // Expression value
220 WORD eattr; // Expression attributes
221 SYM * esym; // External symbol involved in expr.
222 TOKEN r_expr[EXPRSIZE]; // Expression token list
224 // Evaluate what's in the global "tok" buffer
225 // N.B.: We should either get a fixup or a register name from EQUR
226 if (expr(r_expr, &eval, &eattr, &esym) != OK)
229 if (!(eattr & DEFINED))
231 AddFixup(FU_WORD | fixup, sloc, r_expr);
235 // We shouldn't get here, that should not be legal
237 return 0; // Not that this will ever execute, but let's be nice and pacify gcc warnings
241 // Do RISC code generation
243 int GenerateRISCCode(int state)
245 int reg1; // Register 1
246 int reg2; // Register 2
247 int val = 0; // Constructed value
254 int indexed; // Indexed register flag
256 uint64_t eval; // Expression value
257 uint16_t eattr; // Expression attributes
258 SYM * esym = NULL; // External symbol involved in expr.
259 TOKEN r_expr[EXPRSIZE]; // Expression token list
261 // Get opcode parameter and type
262 uint16_t parm = roptbl[state - 3000].param;
263 uint16_t type = roptbl[state - 3000].type;
264 riscImmTokenSeen = 0; // Set to "token not seen yet"
266 // Detect whether the opcode parmeter passed determines that the opcode is
267 // specific to only one of the RISC processors and ensure it is legal in
268 // the current code section. If not then show error and return.
269 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
270 return error("Opcode is not valid in this code section");
272 // Process RISC opcode
275 // No operand instructions
278 DepositRISCInstructionWord(parm, 0, 0);
281 // Single operand instructions (Rd)
282 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
285 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
286 DepositRISCInstructionWord(parm, parm >> 6, reg2);
289 // Two operand instructions (Rs,Rd)
290 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
291 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
294 altbankok = 1; // MOVEFA
296 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
300 altbankok = 1; // MOVETA
302 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
303 DepositRISCInstructionWord(parm, reg1, reg2);
306 // Numeric operand (n,Rd) where n = -16..+15
310 // Numeric operand (n,Rd) where n = 0..31
311 // BCLR, BSET, BTST, MOVEQ
314 // Numeric operand (n,Rd) where n = 1..32
315 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
321 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
325 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
328 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
336 return MalformedOpcode(MALF_NUM);
339 riscImmTokenSeen = 1;
341 if (expr(r_expr, &eval, &eattr, &esym) != OK)
342 return MalformedOpcode(MALF_EXPR);
344 if (!(eattr & DEFINED))
346 AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
351 if (esym && (esym->sattre & EQUATEDREG))
352 return error("equated register seen for immediate value");
355 return error("register seen for immediate value");
357 if (((int)eval < reg1) || ((int)eval > reg2))
358 return error("constant out of range (%d to %d)", reg1, reg2);
361 reg1 = 32 - (int)eval;
362 else if (type == RI_NUM_32)
363 reg1 = (reg1 == 32 ? 0 : (int)eval);
369 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
370 DepositRISCInstructionWord(parm, reg1, reg2);
373 // Move Immediate--n,Rn--n in Second Word
376 return MalformedOpcode(MALF_NUM);
379 riscImmTokenSeen = 1;
381 // Check for equated register after # and return error if so
384 sy = lookup(string[tok[1]], LABEL, 0);
386 if (sy && (sy->sattre & EQUATEDREG))
387 return error("equated register in 1st operand of MOVEI instruction");
390 if (expr(r_expr, &eval, &eattr, &esym) != OK)
391 return MalformedOpcode(MALF_EXPR);
393 if ((lastOpcode == RI_JUMP) || (lastOpcode == RI_JR))
397 // User doesn't care, emit a NOP to fix
398 DepositRISCInstructionWord(57, 0, 0);
399 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
402 warn("MOVEI immediately follows JUMP");
405 if (!(eattr & DEFINED))
407 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
413 MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
417 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
419 DepositRISCInstructionWord(parm, 0, reg2);
420 val = WORDSWAP32(eval);
426 if (*tok == REGRISC_PC)
435 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
439 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
440 DepositRISCInstructionWord(parm, reg1, reg2);
443 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
449 return MalformedOpcode(MALF_LPAREN);
453 if ((tok[1] == '+') || (tok[1] == '-'))
455 // Trying to make indexed call
456 if ((*tok == REGRISC_R14) || (*tok == REGRISC_R15))
457 indexed = (*tok - REGRISC_R0);
459 return IllegalIndexedRegister(*tok);
464 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
474 parm = (WORD)(reg1 - 14 + 58);
477 if ((*tok >= REGRISC_R0) && (*tok <= REGRISC_R31))
482 sy = lookup(string[tok[1]], LABEL, 0);
490 if (sy->sattre & EQUATEDREG)
496 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
500 if (expr(r_expr, &eval, &eattr, &esym) != OK)
501 return MalformedOpcode(MALF_EXPR);
503 if (!(eattr & DEFINED))
504 return error("constant expected after '+'");
510 reg1 = 14 + (parm - 58);
512 warn("NULL offset in LOAD ignored");
516 if ((reg1 < 1) || (reg1 > 32))
517 return error("constant in LOAD out of range (1-32)");
522 parm = (WORD)(parm - 58 + 43);
528 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
533 return MalformedOpcode(MALF_RPAREN);
537 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
538 DepositRISCInstructionWord(parm, reg1, reg2);
541 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
544 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
548 return MalformedOpcode(MALF_LPAREN);
553 if (((*tok == REGRISC_R14) || (*tok == REGRISC_R15)) && (tok[1] != ')'))
554 indexed = *tok - REGRISC_R0;
558 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
568 parm = (WORD)(reg2 - 14 + 60);
571 if ((*tok >= REGRISC_R0) && (*tok <= REGRISC_R31))
576 sy = lookup(string[tok[1]], LABEL, 0);
584 if (sy->sattre & EQUATEDREG)
590 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
594 if (expr(r_expr, &eval, &eattr, &esym) != OK)
595 return MalformedOpcode(MALF_EXPR);
597 if (!(eattr & DEFINED))
599 AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
608 reg2 = 14 + (parm - 60);
610 warn("NULL offset in STORE ignored");
614 if ((reg2 < 1) || (reg2 > 32))
615 return error("constant in STORE out of range (1-32)");
620 parm = (WORD)(parm - 60 + 49);
627 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
632 return MalformedOpcode(MALF_RPAREN);
636 DepositRISCInstructionWord(parm, reg2, reg1);
639 // LOADB/LOADP/LOADW (Rn),Rn
642 return MalformedOpcode(MALF_LPAREN);
645 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
648 return MalformedOpcode(MALF_RPAREN);
652 EVAL_REG_RETURN_IF_ERROR_OR_NO_EOL(reg2, FU_REGTWO);
653 DepositRISCInstructionWord(parm, reg1, reg2);
656 // STOREB/STOREP/STOREW Rn,(Rn)
658 EVAL_REG_RETURN_IF_ERROR(reg1, FU_REGONE);
662 return MalformedOpcode(MALF_LPAREN);
665 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
668 return MalformedOpcode(MALF_RPAREN);
672 DepositRISCInstructionWord(parm, reg2, reg1);
675 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
678 // Jump Absolute - cc,(Rs) - reg2=cc
680 // Check to see if there is a comma in the token string. If not then
681 // the JR or JUMP should default to 0, Jump Always
684 for(t=tok; *t!=EOL; t++)
697 // CC using a constant number (O_o)
704 else if (*tok == SYMBOL)
707 strcpy(scratch, string[tok[1]]);
710 for(i=0; i<MAXINTERNCC; i++)
712 // Look for the condition code & break if found
713 if (strcmp(condname[i], scratch) == 0)
720 // Standard CC was not found, look for an equated one
723 ccsym = lookup(string[tok[1]], LABEL, 0);
725 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
726 val = (int)ccsym->svalue;
728 return error("unknown condition code");
734 else if (*tok == '(')
736 // Set CC to "Jump Always"
742 // Set CC to "Jump Always"
746 if ((val < 0) || (val > 31))
747 return error("condition constant out of range");
749 // Store condition code
755 if (expr(r_expr, &eval, &eattr, &esym) != OK)
756 return MalformedOpcode(MALF_EXPR);
758 if (!(eattr & DEFINED))
760 AddFixup(FU_WORD | FU_JR, sloc, r_expr);
765 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
767 if ((reg2 < -16) || (reg2 > 15))
768 error("PC relative overflow in JR (outside of -16 to 15)");
775 return MalformedOpcode(MALF_LPAREN);
778 EVAL_REG_RETURN_IF_ERROR(reg2, FU_REGTWO);
781 return MalformedOpcode(MALF_RPAREN);
787 DepositRISCInstructionWord(parm, reg2, reg1);
790 // We should never get here. If we do, somebody done fucked up. :-D
792 return error("Unknown RISC opcode type");