1 //////////////////////////////////////////////////////////////////////////////
3 //////////////////////////////////////////////////////////////////////////////
10 //////////////////////////////////////////////////////////////////////////////
17 #define gpu_control_ram_base 0x00f02100
18 #define gpu_work_ram_base 0x00f03000
24 void gpu_update_register_banks(void);
25 void gpu_check_irqs(void);
26 void gpu_set_irq_line(int irqline, int state);
27 unsigned gpu_byte_read(unsigned int offset);
28 unsigned gpu_word_read(unsigned int offset);
29 unsigned gpu_long_read(unsigned int offset);
30 void gpu_byte_write(unsigned offset, unsigned data);
31 void gpu_word_write(unsigned offset, unsigned data);
32 void gpu_long_write(unsigned offset, unsigned data);
33 uint32 gpu_get_pc(void);
34 void gpu_releaseTimeslice(void);
35 void gpu_reset_stats(void);
36 uint32 gpu_read_pc(void);