2 // RMAC - Reboot's Macro Assembler for all Atari computers
3 // AMODE.H - Addressing Modes
4 // Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
14 // 68000 and 68020 addressing modes
15 #define DREG 000 // Dn
16 #define AREG 010 // An
17 #define AIND 020 // (An)
18 #define DINDW 0112 // (Dn.w)
19 #define DINDL 0113 // (Dn.l)
20 #define APOSTINC 030 // (An)+
21 #define APREDEC 040 // -(An)
22 #define ADISP 050 // (d16,An) d16(An)
23 #define AINDEXED 060 // (d8,An,Xn) d8(An,Xn)
24 #define ABSW 070 // xxx.W
25 #define ABSL 071 // xxx or xxx.L
26 #define PCDISP 072 // (d16,PC) d16(PC)
27 #define PCINDEXED 073 // (d16,PC,Xn) d16(PC,Xn)
28 #define IMMED 074 // #data
29 #define ABASE 0100 // (bd,An,Xn)
30 #define MEMPOST 0101 // ([bd,An],Xn,od)
31 #define MEMPRE 0102 // ([bc,An,Xn],od)
32 #define PCBASE 0103 // (bd,PC,Xn)
33 #define PCMPOST 0104 // ([bd,PC],Xn,od)
34 #define PCMPRE 0105 // ([bc,PC,Xn],od)
38 #define AM_NONE 0111 // Nothing
39 #define CACHES 0120 // Instruction/Data/Both Caches (IC/DC/BC)
40 #define CREG 0121 // Control registers (see CREGlut in mach.c)
41 #define FREG 0122 // FPU registers (fp0-fp7)
42 #define FPSCR 0123 // FPU system control registers (fpiar, fpsr, fpcr)
44 // Addressing-mode masks
45 #define M_DREG 0x00000001L // Dn
46 #define M_AREG 0x00000002L // An
47 #define M_AIND 0x00000004L // (An)
48 #define M_APOSTINC 0x00000008L // (An)+
49 #define M_APREDEC 0x00000010L // -(An)
50 #define M_ADISP 0x00000020L // (d16,An) d16(An)
51 #define M_AINDEXED 0x00000040L // (d8,An,Xn) d8(An,Xn)
52 #define M_ABSW 0x00000080L // xxx.W
53 #define M_ABSL 0x00000100L // xxx or xxx.L
54 #define M_PCDISP 0x00000200L // (d16,PC) d16(PC)
55 #define M_PCINDEXED 0x00000400L // (d16,PC,Xn) d16(PC,Xn)
56 #define M_IMMED 0x00000800L // #data
57 #define M_ABASE 0x00001000L // (bd,An,Xn)
58 #define M_MEMPOST 0x00002000L // ([bd,An],Xn,od)
59 #define M_MEMPRE 0x00004000L // ([bd,An,Xn],od)
60 #define M_PCBASE 0x00008000L // (bd,PC,Xn)
61 #define M_PCMPOST 0x00010000L // ([bd,PC],Xn,od)
62 #define M_PCMPRE 0x00020000L // ([bc,PC,Xn],od)
63 #define M_AM_USP 0x00040000L // USP
64 #define M_AM_SR 0x00080000L // SR
65 #define M_AM_CCR 0x00100000L // CCR
66 #define M_AM_NONE 0x00200000L // (nothing)
67 #define M_BITFLD 0x00400000L // 68020 bitfield
68 #define M_CREG 0x00800000L // Control registers
69 #define M_FREG 0x01000000L // FPn
70 #define M_FPSCR 0x02000000L // fpiar, fpsr, fpcr
71 #define M_CACHE40 0x04000000L // 68040 cache registers (IC40,DC40,BC40)
73 // Addr mode categories
74 #define C_ALL 0x00000FFFL
75 #define C_DATA 0x00000FFDL
76 #define C_MEM 0x00000FFCL
77 #define C_CTRL 0x000007E4L
78 #define C_ALT 0x000001FFL
79 #define C_ALL030 0x0003FFFFL
80 #define C_CTRL030 0x0003F7E4L
81 #define C_DATA030 0x0003FFFDL
82 #define C_MOVES (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPRE | M_MEMPOST)
83 #define C_BF1 (M_DREG | M_AIND | M_AINDEXED | M_ADISP | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE)
84 #define C_BF2 (C_BF1 | M_PCDISP | M_PCINDEXED | M_PCBASE | M_PCMPOST | M_PCMPRE)
85 #define C_PMOVE (M_AIND | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPRE | M_MEMPOST)
87 #define C_ALTDATA (C_DATA & C_ALT)
88 #define C_ALTMEM (C_MEM & C_ALT)
89 #define C_ALTCTRL (C_CTRL & C_ALT)
90 #define C_LABEL (M_ABSW | M_ABSL)
91 #define C_NONE M_AM_NONE
93 #define C_CREG (M_AM_USP | M_CREG)
96 #define TIMES1 00000 // (empty or *1)
97 #define TIMES2 01000 // *2
98 #define TIMES4 02000 // *4
99 #define TIMES8 03000 // *8
101 #define M_FC (M_IMMED | M_DREG | M_CREG)
102 #define M_MRN (M_DREG | M_AREG | M_CREG)
105 #define EXT_D 0x0000 // Dn
106 #define EXT_A 0x8000 // An
107 #define EXT_W 0x0000 // Index Size Sign-Extended Word
108 #define EXT_L 0x0800 // Index Size Long Word
109 #define EXT_TIMES1 0x0000 // Scale factor 1
110 #define EXT_TIMES2 0x0200 // Scale factor 2
111 #define EXT_TIMES4 0x0400 // Scale factor 4
112 #define EXT_TIMES8 0x0600 // Scale factor 8
113 #define EXT_FULLWORD 0x0100 // Use full extension word format
114 #define EXT_BS 0x0080 // Base Register Suppressed
115 #define EXT_IS 0x0040 // Index Operand Suppressed
116 #define EXT_BDSIZE0 0x0010 // Base Displacement Size Null (Suppressed)
117 #define EXT_BDSIZEW 0x0020 // Base Displacement Size Word
118 #define EXT_BDSIZEL 0x0030 // Base Displacement Size Long
120 // Indirect and Indexing Operands
121 #define EXT_IISPRE0 0x0000 // No Memory Indirect Action
122 #define EXT_IISPREN 0x0001 // Indirect Preindexed with Null Outer Displacement
123 #define EXT_IISPREW 0x0002 // Indirect Preindexed with Word Outer Displacement
124 #define EXT_IISPREL 0x0003 // Indirect Preindexed with Long Outer Displacement
125 #define EXT_IISPOSN 0x0005 // Indirect Postindexed with Null Outer Displacement
126 #define EXT_IISPOSW 0x0006 // Indirect Postindexed with Word Outer Displacement
127 #define EXT_IISPOSL 0x0007 // Indirect Postindexed with Long Outer Displacement
128 #define EXT_IISNOI0 0x0000 // No Memory Indirect Action
129 #define EXT_IISNOIN 0x0001 // Memory Indirect with Null Outer Displacement
130 #define EXT_IISNOIW 0x0002 // Memory Indirect with Word Outer Displacement
131 #define EXT_IISNOIL 0x0003 // Memory Indirect with Long Outer Displacement
133 #define EXPRSIZE 128 // Maximum #tokens in an expression
135 // Addressing mode variables, output of amode()
138 extern int a0reg, a1reg, a2reg;
139 extern TOKEN a0expr[], a1expr[];
140 extern uint64_t a0exval, a1exval;
141 extern WORD a0exattr, a1exattr;
142 extern int a0ixreg, a1ixreg;
143 extern int a0ixsiz, a1ixsiz;
144 extern TOKEN a0oexpr[], a1oexpr[];
145 extern uint64_t a0oexval, a1oexval;
146 extern WORD a0oexattr, a1oexattr;
147 extern SYM * a0esym, * a1esym;
148 extern uint64_t a0bexval, a1bexval;
149 extern WORD a0bexattr, a1bexattr;
150 extern WORD a0bsize, a1bsize;
151 extern TOKEN a0bexpr[], a1bexpr[];
152 extern WORD a0extension, a1extension;
158 extern uint64_t bf0exval;
161 #define CGSPECIAL 0x8000 // Special (don't parse addr modes)
163 // Exported functions
166 int fpu_reglist_left(WORD *);
167 int fpu_reglist_right(WORD *);
169 #endif // __AMODE_H__